电子秤VHDL代码

-- 输入电压范围0-5V，显示0-255数位
--------------------库定义、包定义--------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
--------------------实体定义--------------------
ENTITY balance IS
port (
clk : IN STD_LOGIC; -- 全局时钟输入，12Mhz晶振产生
reset : IN STD_LOGIC; -- 复位输入
intr : IN STD_LOGIC; -- AD转换结束产生的中断输入
data_i : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- ADC转换后的数据输入
data_o : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- 数码管数据输出
l : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); -- 输出数码管位选
cs : OUT STD_LOGIC; -- ADC使能
wr : OUT STD_LOGIC; -- ADC写控制
rd : OUT STD_LOGIC -- ADC读控制
);
END balance;
--------------------结构体--------------------
ARCHITECTURE bhv OF balance IS
TYPE state IS (start, convert, read1, read2);-- 状态机定义
SIGNAL current_state, next_state : state; -- 状态定义
SIGNAL read_data : STD_LOGIC; -- 读数据寄存器
SIGNAL clock : STD_LOGIC; -- 扫描时钟
SIGNAL p : INTEGER RANGE 0 TO 255; -- 数据寄存器
SIGNAL b0,b1,b2 : INTEGER RANGE 0 TO 9; -- 3位数码管显示数据寄存器
SIGNAL cnt : INTEGER RANGE 0 TO 3 := 0; -- 扫描寄存器
BEGIN
--------------------显示进程--------------------
PROCESS(p, clk)
BEGIN
CASE p IS
WHEN 0|10|20|30|40|50|60|70|80|90|100|110|120|130|140|150|160|170|180|190|200|210|220|230|240|250 => b0 <= 0;
WHEN 1|11|21|31|41|51|61|71|81|91|101|111|121|131|141|151|161|171|181|191|201|211|221|231|241|251 => b0 <= 1;
WHEN 2|12|22|32|42|52|62|72|82|92|102|112|122|132|142|152|162|172|182|192|202|212|222|232|242|252 => b0 <= 2;
WHEN 3|13|23|33|43|53|63|73|83|93|103|113|123|133|143|153|163|173|183|193|203|213|223|233|243|253 => b0 <= 3;
WHEN 4|14|24|34|44|54|64|74|84|94|104|114|124|134|144|154|164|174|184|194|204|214|224|234|244|254 => b0 <= 4;
WHEN 5|15|25|35|45|55|65|75|85|95|105|115|125|135|145|155|165|175|185|195|205|215|225|235|245|255 => b0 <= 5;
WHEN 6|16|26|36|46|56|66|76|86|96|106|116|126|136|146|156|166|176|186|196|206|216|226|236|246 => b0 <= 6;
WHEN 7|17|27|37|47|57|67|77|87|97|107|117|127|137|147|157|167|177|187|197|207|217|227|237|247 => b0 <= 7;
WHEN 8|18|28|38|48|58|68|78|88|98|108|118|128|138|148|158|168|178|188|198|208|218|228|238|248 => b0 <= 8;
WHEN 9|19|29|39|49|59|69|79|89|99|109|119|129|139|149|159|169|179|189|199|209|219|229|239|249 => b0 <= 9;
WHEN OTHERS => NULL;
END CASE;
CASE p IS
WHEN 0|1|2|3|4|5|6|7|8|9|100|101|102|103|104|105|106|107|108|109|200|201|202|203|204|205|206|207|208|209 => b1 <= 0; WHEN 10|11|12|13|14|15|16|17|18|19|110|111|112|113|114|115|116|117|118|119|210|211|212|213|214|215|216|217|218|219 => b1 <= 1; WHEN 20|21|22|23|24|25|26|27|28|29|120|121|122|123|124|125|126|127|128|129|220|221|222|223|224|225|226|227|228|229 => b1 <= 2; WHEN 30|31|32|33|34|35|36|37|38|39|130|131|132|133|134|135|136|137|138|139|230|231|232|233|234|235|236|237|238|239 => b1 <= 3; WHEN 40|41|42|43|44|45|46|47|48|49|140|141|142|143|144|145|146|147|148|149|240|241|242|243|244|245|246|247|248|249 => b1 <= 4; WHEN 50|51|52|53|54|55|56|57|58|59|150|151|152|153|154|155|156|157|158|159|250|251|252|253|254|255 => b1 <= 5; WHEN 60|61|62|63|64|65|66|67|68|69|160|161|162|163|164|165|166|167|168|169 => b1 <= 6; WHEN 70|71|72|73|74|75|76|77|78|79|170|171|172|173|174|175|176|177|178|179 => b1 <= 7; WHEN 80|81|82|83|84|85|86|87|88|89|180|181|182|183|184|185|186|187|188|189 => b1 <= 8; WHEN 90|91|92|93|94|95|96|97|98|99|190|191|192|193|194|195|196|197|198|199 => b1 <= 9; WHEN OTHERS => NULL;
END CASE;
IF (p < 100) THEN b2 <= 0;
ELSIF (p >= 100 and p < 200) THEN b2 <= 1;
ELSIF (p >= 200) THEN b2 <= 2;
END IF;
END PROCESS;
--------------------分频进程--------------------
PROCESS(clk)
VARIABLE cnt1 : INTEGER RANGE 0 TO 100;
VARIABLE cnt2 : INTEGER RANGE 0 TO 20;
BEGIN
IF (clk'EVENT AND clk = '1') THEN
IF (cnt1 = 100) THEN
cnt1 := 0;
IF (cnt2 = 20) THEN
cnt2 := 0;
clock <= NOT clock;
IF (cnt = 3) THEN
cnt <= 0;
ELSE
cnt <= cnt + 1;
END IF;
ELSE
cnt2 := cnt2 + 1;
END IF;
ELSE
cnt1 := cnt1 + 1;
END IF;
END IF;
END PROCESS;
--------------------状态驱动进程--------------------
sync : PROCESS(clock, reset)
BEGIN
IF (reset = '0') THEN
current_state <= start;
ELSIF (clock'EVENT AND clock = '1') THEN
current_state <= next_state;
END IF;
END PROCESS sync;
--------------------ADC0804驱动进程--------------------
comb : PROCESS(current_state, intr)
BEGIN
CASE current_state IS
WHEN start => -- 启动状态
next_state <= convert;
cs <= '0';
wr <= '0';
rd <= '1';
read_data <= '0';
WHEN convert => -- 初始化
IF (intr = '0') THEN
next_state <= read1;
ELSE
next_state <= convert;
END IF;
cs <= '1';
wr <= '1';
rd <= '1';
read_data <= '0';
WHEN read1 => -- 读状态1
next_state <= read2;
cs <= '0';
wr <= '1';
rd <= '0';
read_data <= '1';
WHEN read2 => -- 读状态2
next_state <= start;
cs <= '1';
wr <= '1';
rd <= '1';
read_data <= '0';
WHEN OTHERS => -- 其他状态
next_state <= start;
END CASE;
END PROCESS comb;
--------------------读取ADC数据--------------------
get_data : PROCESS(clock, reset)
BEGIN
IF (reset = '0') THEN
p <= 0;
ELSIF (clock'EVENT AND clock = '1') THEN
IF (read_data = '1') THEN
p <= conv_integer(data_i);
END IF;
END IF;
END PROCESS;
--------------------显示进程--------------------
PROCESS(cnt)
FUNCTION b_to_s7(bcd8421 : INTEGER RANGE 0 TO 9) RETURN STD_LOGIC_VECTOR IS VARIABLE smg7 : STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
CASE bcd8421 IS -- 计算输出值
WHEN 0 => smg7 := "11111100"; -- ABCDEFGH
WHEN 1 => smg7 := "01100000";
WHEN 2 => smg7 := "11011010";
WHEN 3 => smg7 := "11110010";
WHEN 4 => smg7 := "01100110";
WHEN 5 => smg7 := "10110110";
WHEN 6 => smg7 := "10111110";
WHEN 7 => smg7 := "11100000";
WHEN 8 => smg7 := "11111110";
WHEN 9 => smg7 := "11110110";
WHEN OTHERS => smg7 := "10001110";
END CASE;
RETURN smg7;
END b_to_s7;
BEGIN
CASE cnt IS
WHEN 0 => l <= "110"; data_o <= b_to_s7(b0);
WHEN 1 => l <= "101"; data_o <= b_to_s7(b1);
WHEN 2 => l <= "011"; data_o <= b_to_s7(b2)。