VHDL源代码
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VHDL源代码：
library ieee; --显示器彩条发生器
use VGA is
port(clk,mode :in std_logic; --扫描时钟/显示模式选择时钟
d,hs,vs,r,g,b:out std_logic); --行，场同步/红，绿，蓝
end VGA;
architecture a of VGA is
signal hs1,vs1,fclk,cclk,divide_clk,dly: std_logic;
signal mmode :std_logic_vector(1 downto 0); --方式选择
signal cnt :std_logic_vector(2 downto 0);
signal fs :std_logic_vector(3 downto 0);
signal cc :std_logic_vector(4 downto 0); --行同步/横彩条生成 signal ll :std_logic_vector(8 downto 0); --长同步/竖彩条生成 signal grbh :std_logic_vector(3 downto 1); --X 横彩条
signal grby :std_logic_vector(3 downto 1); --Y 竖彩条
signal grbx :std_logic_vector(3 downto 1); --文字
signal grbt :std_logic_vector(3 downto 1); --图案
signal grbp :std_logic_vector(3 downto 1);
signal grb :std_logic_vector(3 downto 1);
signal x :integer range 0 to 800;
signal x1: integer range 0 to 800;
signal y1: integer range 0 to 600;
signal x2: integer range 0 to 800;
signal x3: integer range 0 to 800;
signal x4: integer range 0 to 800;
signal x5: integer range 0 to 800;
signal x7: integer range 0 to 800;
signal x8: integer range 0 to 800;
signal x9: integer range 0 to 800;
signal x10: integer range 0 to 800;
signal x11: integer range 0 to 800;
signal y2: integer range 0 to 600;
signal y3: integer range 0 to 600;
signal y4: integer range 0 to 600;
signal y5: integer range 0 to 600;
signal y6: integer range 0 to 600;
signal c: integer range 0 to 30;
begin
grb(3)<=(grbp(3) xor mode) and hs1 and vs1;
grb(2)<=(grbp(2) xor mode) and hs1 and vs1;
grb(1)<=(grbp(1) xor mode) and hs1 and vs1;
process(mode)
begin
if mode'event and mode='1' then
if mmode="11" then
mmode<="00";
else
mmode<=mmode+1;
end if;
end if;
end process; --四种模式
process (mmode)
begin
if mmode="00" then grbp<=grbx;
elsif mmode="01" then grbp<=grbh; --选择横彩条 elsif mmode="10" then grbp<=grby; --选择竖彩条
elsif mmode="11" then grbp<=grbh xor grby; --选择棋盘格 else grbp<="000";
end if;
end process;
process(clk) --3/4分频 begin
if clk'event and clk='1' then
cnt<=cnt+3;
dly<=cnt(2);
end if;
--if cnt<3 then
-- divide_clk<='0';
--elsif cnt<5 then
-- divide_clk<='1';
--else
-- cnt<="000";
--end if;
end process;
divide_clk<=(cnt(2) xor dly) and clk;
process(divide_clk) --13分频
begin
if divide_clk'event and divide_clk='1' then
if fs=12 then
fs<="0000";
else
fs<=fs+1;
end if;