EDA-常见实例源程序代码vhdl

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VHDL源代码

VHDL源代码：library ieee; --显示器彩条发生器use VGA isport(clk,mode :in std_logic; --扫描时钟/显示模式选择时钟d,hs,vs,r,g,b:out std_logic); --行，场同步/红，绿，蓝end VGA;architecture a of VGA issignal hs1,vs1,fclk,cclk,divide_clk,dly: std_logic;signal mmode :std_logic_vector(1 downto 0); --方式选择signal cnt :std_logic_vector(2 downto 0);signal fs :std_logic_vector(3 downto 0);signal cc :std_logic_vector(4 downto 0); --行同步/横彩条生成 signal ll :std_logic_vector(8 downto 0); --长同步/竖彩条生成 signal grbh :std_logic_vector(3 downto 1); --X 横彩条signal grby :std_logic_vector(3 downto 1); --Y 竖彩条signal grbx :std_logic_vector(3 downto 1); --文字signal grbt :std_logic_vector(3 downto 1); --图案signal grbp :std_logic_vector(3 downto 1);signal grb :std_logic_vector(3 downto 1);signal x :integer range 0 to 800;signal x1: integer range 0 to 800;signal y1: integer range 0 to 600;signal x2: integer range 0 to 800;signal x3: integer range 0 to 800;signal x4: integer range 0 to 800;signal x5: integer range 0 to 800;signal x7: integer range 0 to 800;signal x8: integer range 0 to 800;signal x9: integer range 0 to 800;signal x10: integer range 0 to 800;signal x11: integer range 0 to 800;signal y2: integer range 0 to 600;signal y3: integer range 0 to 600;signal y4: integer range 0 to 600;signal y5: integer range 0 to 600;signal y6: integer range 0 to 600;signal c: integer range 0 to 30;begingrb(3)<=(grbp(3) xor mode) and hs1 and vs1;grb(2)<=(grbp(2) xor mode) and hs1 and vs1;grb(1)<=(grbp(1) xor mode) and hs1 and vs1;process(mode)beginif mode'event and mode='1' thenif mmode="11" thenmmode<="00";elsemmode<=mmode+1;end if;end if;end process; --四种模式process (mmode)beginif mmode="00" then grbp<=grbx;elsif mmode="01" then grbp<=grbh; --选择横彩条 elsif mmode="10" then grbp<=grby; --选择竖彩条elsif mmode="11" then grbp<=grbh xor grby; --选择棋盘格 else grbp<="000";end if;end process;process(clk) --3/4分频 beginif clk'event and clk='1' thencnt<=cnt+3;dly<=cnt(2);end if;--if cnt<3 then-- divide_clk<='0';--elsif cnt<5 then-- divide_clk<='1';--else-- cnt<="000";--end if;end process;divide_clk<=(cnt(2) xor dly) and clk;process(divide_clk) --13分频beginif divide_clk'event and divide_clk='1' thenif fs=12 thenfs<="0000";elsefs<=fs+1;end if;end if;end process;process(fclk)beginif fclk'event and fclk='1' thenif cc=29 thencc<="00000";elsecc<=cc+1;end if;end if;end process;d<=fclk;process(cclk)beginif cclk'event and cclk='1' thenif ll=481 thenll<="000000000";elsell<=ll+1;end if;end if;end process;process(cc,ll)beginif cc>23 then --行同步hs1<='0';elsehs1<='1';end if;if ll>479 then --长同步 vs1<='0';elsevs1<='1';end if;end process;process(clk)beginif clk'event and clk='1' thenif hs1='0' thenx<=0;elsex<=x+1;end if;end if;end process;process(x,ll,cc,hs1,vs1)variable s1: integer range 0 to 3;beginif cc<3 then grbh<="111"; --竖彩条 elsif cc<6 then grbh<="110";elsif cc<9 then grbh<="101";elsif cc<12 then grbh<="100";elsif cc<15 then grbh<="011";elsif cc<18 then grbh<="010";elsif cc<21 then grbh<="001";else grbh<="000";end if;if ll<60 then grby<="111"; --横彩条 elsif ll<120 then grby<="110";elsif ll<180 then grby<="101";elsif ll<240 then grby<="100";elsif ll<300 then grby<="011";elsif ll<360 then grby<="010";elsif ll<420 then grby<="001";else grby<="000";end if;if x=4 thengrbx<="100";elsif x=180 thengrbx<="001";elsegrbx<="000";end if;if ll>20 and ll<24 thenif x<110 thengrbx<="100";end if;end if;if ll>30 and ll<33 thenif x<80 thengrbx<="100";end if;end if;if ll>445 and ll<449 thenif x>90 thengrbx<="001";end if;end if;if ll>437 and ll<440 thenif x>100 thengrbx<="001";end if;end if;--"湖"if ll>89 and ll<94 thenif x=100 or x=103 or x=106 or x=107 or x=108 then grbx<="110";end if;end if;if ll>93 and ll<98 thenif x=102 or x=103 or x=104 or x=106 or x=108 then grbx<="110";end if;end if;if ll>97 and ll<102 thenif x=100 or x=103 or x=106 or x=107 or x=108 then grbx<="110";end if;end if;if ll>101 and ll<106 thenif x=102 or x=103 or x=104 or x=106 or x=108 thengrbx<="110";end if;end if;if ll>105 and ll<110 thenif x=100 or x=102 or x=104 or x=106 or x=107 or x=108 then grbx<="110";end if;end if;if ll>109 and ll<114 thenif x=100 or x=102 or x=103 or x=104 or x=106 or x=108 then grbx<="110";end if;end if;if ll>113 and ll<118 thenif x=106 thengrbx<="110";end if;end if;--"南"if ll>121 and ll<126 thenif x=104 thengrbx<="110";end if;end if;if ll>125 and ll<130 thenif x>99 and x<109 thengrbx<="110";end if;if ll>129 and ll<134 thenif x=104 thengrbx<="110";end if;end if;if ll>133 and ll<138 thenif x>99 and x<109 thengrbx<="110";end if;end if;if ll>137 and ll<142 thenif x=100 or x=108 thengrbx<="110";end if;end if;if ll>141 and ll<146 thenif x=100 or x=103 or x=105 or x=108 thengrbx<="110";end if;end if;if ll>145 and ll<150 thenif x=100 or x=102 or x=103 or x=104 or x=105 or x=106 or x=108 then grbx<="110";end if;end if;if ll>149 and ll<154 thenif x=100 or x=104 or x=108 thengrbx<="110";end if;if ll>153 and ll<158 thenif x=100 or x=102 or x=103 or x=104 or x=105 or x=106 or x=108 thengrbx<="110";end if;end if;if ll>157 and ll<162 thenif x=100 or x=104 or x=108 thengrbx<="110";end if;end if;--"大"if ll>165 and ll<170 thenif x=103 or x=104 thengrbx<="110";end if;end if;if ll>169 and ll<174 thenif x=103 or x=104 thengrbx<="110";end if;end if;if ll>173 and ll<178 thenif x=100 or x=101 or x=102 or x=103 or x=104 or x=105 or x=106 or x=107 or x=108 thengrbx<="110";end if;end if;if ll>177 and ll<182 thenif x=103 or x=104 thengrbx<="110";end if;end if;if ll>181 and ll<186 thenif x=103 or x=104 thengrbx<="110";end if;end if;if ll>185 and ll<190 thenif x=103 or x=105 thengrbx<="110";end if;end if;if ll>189 and ll<194 thenif x=102 or x=103 or x=106 thengrbx<="110";end if;end if;if ll>193 and ll<198 thenif x=101 or x=102 or x=107 thengrbx<="110";end if;end if;if ll>197 and ll<202 thenif x=100 or x=101 or x=107 or x=108 then grbx<="110";end if;end if;--"学"if ll>205 and ll<210 thenif x=102 or x=104 or x=106 thengrbx<="110";end if;end if;if ll>209 and ll<214 thenif x=100 or x=101 or x=102 or x=103 or x=104 or x=105 or x=106 or x=107 or x=108 thengrbx<="110";end if;end if;if ll>213 and ll<218 thenif x=100 or x=108 thengrbx<="110";end if;end if;if ll>217 and ll<222 thenif x=102 or x=103 or x=104 or x=105 or x=106 thengrbx<="110";end if;end if;if ll>221 and ll<226 thenif x=105 thengrbx<="110";end if;end if;if ll>225 and ll<230 thenif x=104 thengrbx<="110";end if;end if;if ll>229 and ll<234 thenif x=100 or x=101 or x=102 or x=103 or x=104 or x=105 or x=106 or x=107 or x=108 thengrbx<="110";end if;end if;if ll>233 and ll<238 thenif x=104 thengrbx<="110";end if;end if;if ll>237 and ll<242 thenif x=104 thengrbx<="110";end if;end if;if ll>241 and ll<245 thenif x=103 or x=104 thengrbx<="110";end if;end if;if vs1'event and vs1='1' thenif c=20 thenc<=0;case s1 iswhen 0 =>if x1=120 thens1:=1;elsex1<=x1+1 ; end if;when 1 =>if y1=350 thens1:=2;elsey1<=y1+1; end if;when 2 =>if x1=35 thens1:=3;elsex1<=x1-1; end if;when 3 =>if y1=280 thens1:=0;elsey1<=y1-1; end if;end case;elsec<=c+1;end if;end if;--"HU NAN DA XUE"x2<=x1+1;x3<=x1+2;x4<=x1+3;x5<=x1+5;x7<=x1+7;x8<=x1+8;x9<=x1+9;x10<=x1+10;x11<=x1+11;--y1<=250;y2<=y1+4;y3<=y1+8;y4<=y1+12;y5<=y1+16;y6<=y1+20;if ll>=y1 and ll<y2 thenif x=x1 or x=x5 or x=x7 or x=x8 or x=x11 thengrbx<="101";end if;end if;if ll>=y2 and ll<y3 thenif x=x1 or x=x5 or x=x7 or x=x8 or x=x9 or x=x11 then grbx<="101";end if;end if;if ll>=y3 and ll<y4 thenif x=x1 or x=x2 or x=x3 or x=x4 or x=x5 or x=x7 or x=x9 or x=x11 then grbx<="101";end if;end if;if ll>=y4 and ll<y5 thenif x=x1 or x=x5 or x=x7 or x=x10 or x=x11 thengrbx<="101";end if;end if;if ll>=y5 and ll<y6 thenif x=x1 or x=x5 or x=x7 or x=x10 or x=x11 thengrbx<="101";end if;end if;if ll>100 and 11<150 then --图案设计if ll>121 and ll<126 thenif x>43 and x<57 thengrbx<="100";end if;elsif x=50 thengrbx<="100";end if;end if;if ll>150 and 11<200 thenif ll>171 and ll<176 thenif x>60 and x<74 thengrbx<="010";end if;elsif x=67 thengrbx<="010";end if;end if;if ll>200 and 11<250 then if ll>221 and ll<226 then if x>74 and x<88 then grbx<="001";end if;elsif x=81 thengrbx<="001";end if;end if;end process;fclk<=fs(2);cclk<=cc(4);hs<= not hs1;vs<= not vs1;g<=grb(3);r<=grb(2);b<=grb(1);end a;。

EDA 常见实例源程序代码vhdl

第4章用VHDL程序实现常用逻辑电路4.1 组合逻辑电路设计4.1.1 基本逻辑门library ieee;use iee.std_logic_1164.all;entity jbm isport(a,b: in bit;f1,f2,f3,f4,f5,f: out bit);end jbm;architecture a of jbm isbeginf1<=a and b; --构成与门f2<=a or b; --构成或门f<=not a; --构成非门f3<=a nand b; --构成与非门f4<=a nor b; --构成异或门f5<=not(a xor b); --构成异或非门即同门end;4.1.2 三态门library ieee;use ieee.std_logic_1164.all;entity tri_s isport(enable: in std_logic;datain: in std_logic_vector(7 downto 0);dataout: out std_logic_vector(7 downto0));end tri_s;architecture bhv of tri_s isbeginprocess(enable,datain)beginif enable='1' thendataout<=datain;elsedataout<="ZZZZZZZZ";end if;end process;end bhv;4.1.3 3-8译码器library ieee;use ieee.std_logic_1164.all;entity decoder3_8 isport(a,b,c,g1,g2a,g2b: in std_logic;y: out std_logic_vector(7 downto 0));end decoder3_8;architecture a of decoder3_8 issignal dz:std_logic_vector(2 downto 0);begindz<=c&b&a;process (dz,g1,g2a,g2b)beginif(g1='1'and g2a='0'and g2b='0')thencase dz iswhen "000"=> y<="11111110";when "001"=> y<="11111101";when "010"=> y<="11111011";when "011"=> y<="11110111";when "100"=> y<="11101111";when "101"=> y<="11011111";when "110"=> y<="10111111";when "111"=> y<="01111111";when others=>y<="XXXXXXXX";end case;elsey<="11111111";end if;end process;4.1.4 优先编码器library ieee;use ieee.std_logic_1164.allentity coder isport(din: in std_logic_vector(0 to 7);output: out std_logic_vector(0 to 2));end coder;architecture behave of coder issignal sint: std_logic_vevtor(4 downto 0);beginprocess(din)beginif (din(7)='0') thenoutput <= "000" ;elsif (din(6)='0') thenoutput <= "100" ;elsif (din(5)='0') thenoutput <= "010" ;elsif (din(4)='0') thenoutput <= "110" ;elsif (din(3)='0') thenoutput <= "001" ;elsif (din(2)='0') thenoutput <= "101" ;elsif (din(1)='0') thenoutput <= "011" ;elseoutput <= "111" ;end if;end process;end behav;4.1.5 7段码译码器library ieee;use ieee.std_logic_1164.allentity decl7s isport (a: in std_logic_vector (3 downto 0);led7s: out std_logic_vector(6 downto 0));end decl7s;architecture behave of decl7s isbeginprocess(a)begincase a iswhen "0000" => led7s <= "0111111" ;when "0001" => led7s <= "0000110" ;when "0010" => led7s <= "1011011" ;when "0011" => led7s <= "1001111" ;when "0100" => led7s <= "1100110" ;when "0101" => led7s <= "1101101" ;when "0110" => led7s <= "1111101" ;when "0111" => led7s <= "0000111" ;when "1000" => led7s <= "1111111" ;when "1001" => led7s <= "1101111" ;when "1010" => led7s <= "1110111" ;when "1011" => led7s <= "1111100" ;when "1100" => led7s <= "0111001" ;when "1101" => led7s <= "1011110" ;when "1110" => led7s <= "1111001" ;when "1111" => led7s <= "1110001" ;when others => null;end case;end process;end behave;4.1.6二-十进制BCD译码器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_signed.all;entity bcdymq isport(din : in integer range 15 downto 0;a,b : out integer range 9 downto 0);end;architecture fpq1 of bcdymq isbeginp1: process(din)beginif din<10 thena< =din;b< =0;elsea< =din-10;end if;end process p1;end;4.1.7 多位加（减）法器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_signed.all;entity jianfaqi isport(a,b : in std_logic_vector(0 to 3);c0: in std_logic;c1: out std_logic;d : out std_logic_vector(0 to 3));end;architecture a of jianfaqi isbeginprocessbeginif a>b+c0 thend<=a-(b+c0);c1<='0';elsec1<='1';d<=("10000")-(b+c0-a);end if;end process ;end ;4.2 时序逻辑电路设计4.2.1 触发器RS触发器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_signed.all;entity rsff isport(r,s,clk:in std_logic;q,qb:buffer std_logic);end rsff;architecture rsff_art of rsff issignal q_s,qb_s:std_logic;beginprocess(clk,r,s)beginif (clk'event and clk='1') thenif (s='1' and r='0') thenq_s<='0' ;qb_s<='1' ;elsif (s='0' and r='1') thenq_s <= '1' ;qb_s <= '0' ;elsif (s='0' and r='0') thenq_s <= q_s;qb_s <= qb_s;end if;q_s <= q_s;qb_s <= qb_s;end process;end rsff_art;同步复位D触发器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_signed.all;entity syndff isport(d,clk,reset:in std_logic;q,qb:out std_logic);end syndff;architecture dff_art of syndff isbeginprocess(clk)beginif (clk'event and clk='1') thenif (reset='0') thenq<='0';qb<='1';elseq<=d;qb<=not q;end if;end if;end process;end dff_art;JK触发器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_signed.all;entity asynjkff isport(j,k,clk,set.reset:in std_logic;q,qb:out std_logic);end asynjkff;architecture jkff_art of asynjkff issingal q_s,qb_s:std_logic;beginprocess(clk,set,reset)beginif (set='0' and reset='1' ) thenq_s<='1';qb_s<='0';elsif (set='1' and reset='0' ) thenq_s<='0';qb_s<='1';elsif (clk'event and clk='1') thenif (j='0' and k='1' ) thenq_s<='0';qb_s<='1';elsif (j='1' and k='0' ) thenq_s<='1';qb_s<='0';elsif (j='1' and k='1' ) thenq_s<=not q_s;qb_s<=not qb_s;end if;end if;q<= q_s;qb<= qb_s;end process;end jkff_art;T触发器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_signed.all;entity tff isport(t,clk: in std_logic;q: out std_logic);end;architecture tff_art of tff issignal q_temp: std_logic;beginp1:process(clk)beginif rising_edge(clk) thenif t='1' then --当T=1时T触发器具有2分频的功能q_temp<=not q_temp;elseq_temp<=q_temp;end if;end if;q<=q_temp;end process;q<=q_temp;end tff_art;4.2.2计数器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity cnt4 ISport( clk: in std_logic;q: out std_logic_vector(3 downto 0));end cnt4;architecture behave of cnt4 issignal q1: std_logic_vector(3 downto 0);beginprocess(clk)beginif (clk'event and clk = '1') thenq1<=q1+1;end if;end process;q<=q1;一般计数器设计library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity cnt10 isport( clk,rst,en,updown: in std_logic;cq: out std_logic_vector(3 downto 0));end cnt10;architecture behave of cnt10 isbeginprocess(clk,rst,en,updown)variable cqi:std_logic_vector(3 downto 0);beginif rst='1' thencqi:=(others=>'0'); --计数器异步复位elsif (clk'event and clk = '1') then --检测时钟上升沿if en='1'then --检测是否允许计数（同步使能）if updown='0'thenif cqi<9 thencqi:=cqi+1; --允许计数,检测是否小于9elsecqi:=(others=>'0'); --大于9，计数值清零end if;elseif cqi>0 thencqi:=cqi-1; --检测是否大于0elsecqi:=(others=>'1'); ---否则，计数值置1end if;end if;end if;end if;cq<=cqi; --将计数值向端口输出end process;end behave;4.2.3 分频器library ieee;use std_logic_1164.all;use std_logic_unsigned.all;entity freq1 isport(clk: in std_logic;d: in std_logic_vector(7 downto 0);fout: out std_logic);end;architecture one of dvf issignal full: std_logic;beginp_reg:process(clk)variable cnt8: std_logic_vector(7 downto 0);if clk'event and clk='1'then --检测时钟上升沿if cnt8=''11111111'' thencnt8:=d; --当CNT8计数计满时，输入数据D被同步预置给计数器CNT8full<='1';--同时使溢出标志信号FULL输出为高电平elsecnt8:=cnt8+1;--否则继续作加1计数full<='0'; --且输出溢出标志信号FULL为低电平end if;end if;end process p_reg;p_div:process(full)variable cnt2: std_logic;beginif full'event and full='1' thencnt2:=not cnt2; --如果溢出标志信号FULL为高电平，T触发器输出取反if cnt2='1'thenfout<='1';elsefout<='0';end if;end if;end process p_div;end;4.2.4 移位寄存器library ieee;use ieee.std_logic_1164.all;entity shift isport(clk,c0: in std_logic;--时钟和进位输入md: in std_logic_vector(2 downto 0);--移位模式控制字d: in std_logic_vector(7 downto 0);--待加载移位的数据qb: out std_logic_vector(7 downto 0);--移位数据输出cn: out std_logic);--进位输出end;architecture behave of shift issignal reg: std_logic_vector(7 downto 0);signal cy: std_logic;beginprocess(clk,md,c0)beginif clk'event and clk='1' thencase md iswhen "001" => reg (0) <= c0 ;reg (7 downto 1) <= reg (6 downto 0);cy <= reg (7); --带进位循环左移when "010" => reg (0) <= reg (7);reg (7 downto 1) <= reg (6 downto 0); --自循环左移when "011" => reg (7) <= reg (0);reg (6 downto 0) <= reg (7 downto 1); --自循环右移when "100" => reg (7) <= C0 ;reg (6 downto 0) <= reg (7 downto 1);cy <= reg (0); --带进位循环右移when "101" => reg (7 downto 0) <= d(7 downto 0); --加载待移数when others => reg<= reg ; cy<= cy ; --保持end case;end if;end process;qb(7 downto 0) <= reg (7 downto 0); cn <= cy; --移位后输出end behav;4.3 状态机逻辑电路设计4.3.1 一般状态机设计library ieee;use ieee.std_logic_1164.all;entity s_machine isport ( clk,reset : in std_logic;state_inputs : in std_logic_vector(0 to1);comb_outputs : out integer range 0 to 15 );end s_machine;architecture behv of s_machine istype fsm_st is (s0, s1, s2, s3); --数据类型定义，状态符号化signal current_state, next_state: fsm_st; --将现态和次态定义为新的数据类型beginreg: process(reset,clk) --主控时序进程beginif reset = '1' thencurrent_state <= s0; --检测异步复位信号elsif clk='1' and clk'event thencurrent_state <= next_state;end if;end process;com:process(current_state, state_inputs) --主控组合进程begincase current_state iswhen s0 => comb_outputs<= 5;if state_inputs = "00" thennext_state<=s0;elsenext_state<=s1;end if;when s1 => comb_outputs<= 8;if state_inputs = "00" thennext_state<=s1;elsenext_state<=s2;end if;when s2 => comb_outputs<= 12;if state_inputs = "11" thennext_state <= s0;elsenext_state <= s3;end if;when s3 => comb_outputs <= 14;if state_inputs = "11" thennext_state <= s3;elsenext_state <= s0;end if;end case;end process;end behv;4.3.2状态机的应用library ieee;use ieee.std_logic_1164.all;entity asm_led isport(clk,clr : in std_logic;led1,led2,led3:out std_logic);end;architecture a of asm_led istype states is (s0,s1,s2,s3,s4,s5); --对状态机的状态声明signal q: std_logic_vector( 0 to 2);signal state : states;beginp1: process(clk,clr)beginif(clr='0')thenstate<=s0;elsif (clk'event and clk='1') thencase state iswhen s0=> state <=s1;when s1=> state <=s2;when s2=> state <=s3;when s3=> state <=s4;when s4=> state <=s5;when s5=> state <=s0;when others => state<=s0;end case;end if;end process p1;p2: process (clr,state)beginif(clr='0') thenled1<='0';led2<='0';led3<='0';elsecase state iswhen s0=> led1<='1';led2<='0';led3<='0';when s1=> led1<='0';led2<='1';led3<='0';when s2=> led1<='0';led2<='1';led3<='0';when s3=> led1<='0';led2<='0';led3<='1';when s4=> led1<='0';led2<='0';led3<='1';when s5=> led1<='0';led2<='0';led3<='1';when others => null;end case;end if;end process p2;end ;第6章EDA仿真技术应用实例6.1带使能和片选端的16：4线优先编码器设计子模块设计源代码：library ieee;use ieee.std_logic_1164.all;entity pencoder isport(d:in std_logic_vector(7 downto 0);ei:in std_logic; --ei:enable inputgs,eo:out bit; --gs:chip select output;eo:enable outputq2,q1,q0:out std_logic);end pencoder;architecture encoder of pencoder isbeginprocess(d)beginif(d(0)='0' and ei='0')thenq2<='1';q1<='1';q0<='1';gs<='0';eo<='1';elsif(d(1)='0' and ei='0')thenq2<='1';q1<='1';q0<='0';gs<='0';eo<='1';elsif(d(2)='0' and ei='0')thenq2<='1';q1<='0';q0<='1';gs<='0';eo<='1';elsif(d(3)='0' and ei='0')thenq2<='1';q1<='0';q0<='0';gs<='0';eo<='1';elsif(d(4)='0' and ei='0')thenq2<='0';q1<='1';q0<='1';gs<='0';eo<='1';elsif(d(5)='0' and ei='0')thenq2<='0';q1<='1';q0<='0';gs<='0';eo<='1';elsif(d(6)='0' and ei='0')thenq2<='0';q1<='0';q0<='1';gs<='0';eo<='1';elsif(d(7)='0' and ei='0')then --d7 prioty encoderq2<='0';q1<='0';q0<='0';gs<='0';eo<='1';elsif(ei='1')thenq2<='1';q1<='0';q0<='1';gs<='1';eo<='1';elsif(d="11111111" and ei='0')thenq2<='1';q1<='1';q0<='1';gs<='1';eo<='0';end if;end process;end encoder;6.27段显示译码器设计译码器设计源代码：library ieee;use ieee.std_logic_1164.all;entity decoder47 isport(lt,ibr,ib_ybr:in bit;a: in std_logic_vector(3 downto 0);y:out std_logic_vector(6 downto 0));end decoder47;architecture art of decoder47 isbeginprocess(lt,ibr,ib_ybr,a)variable s: std_logic_vector(3 downto 0);begins:=a(3)&a(2)&a(1)&a(0);if lt='0' and ib_ybr='1' theny<="1111111"; --检查七段显示管是否正常elsif ibr='0' and a="0000" theny<="0000000";elsecase s iswhen"0000"=>y<="1111110"; --7Ewhen"0001"=>y<="0110000"; --30when"0010"=>y<="1101101"; --6Dwhen"0011"=>y<="1111001"; --79when"0100"=>y<="0110011"; --33when"0101"=>y<="1011011"; --5Bwhen"0110"=>y<="0011111"; --5Fwhen"0111"=>y<="1110000"; --70when"1000"=>y<="1111111"; --7Ewhen"1001"=>y<="1110011"; --7Bwhen"1010"=>y<="0001101"; --0Dwhen"1011"=>y<="0011001"; --19when"1100"=>y<="0100011"; --23when"1101"=>y<="1001011"; --4Bwhen"1110"=>y<="0001111"; --0Fwhen"1111"=>y<="0000000";end case;end if;end process;end art;6.3带异步清零端的12位二进制全加器设计子模块源代码：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity adder4b isport(clr,cin: in std_logic;a,b: in std_logic_vector(3 downto 0);s: out std_logic_vector(3 downto 0);cout:out std_logic);end adder4b;architecture art of adder4b issignal sint:std_logic_vector(4 downto 0);signal aa,bb:std_logic_vector(4 downto 0);beginprocess(clr)beginif clr='1'thensint<="00000";elseaa<='0'&a;bb<='0'&b;sint<=aa+bb+cin;end if;s<=sint(3 downto 0);cout<=sint(4);end process;end art;顶层模块设计源代码：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity adder12b isport(clr,cin: in std_logic;a,b: in std_logic_vector(11 downto 0);s: out std_logic_vector(11 downto 0);cout:out std_logic);end adder12b;architecture art of adder12b iscomponent adder4b isport(clr,cin: in std_logic;a,b: in std_logic_vector(3 downto 0);s: out std_logic_vector(3 downto 0);cout:out std_logic);end component;signal carry_out1:std_logic;signal carry_out2:std_logic;beginu1:adder4b port map(clr=>clr,cin=>cin,a=>a(3 downto 0),b=>b(3 downto 0),s=>s(3 downto 0),cout=>carry_out1);u2:adder4b port map(clr=>clr,cin=>carry_out1,a=>a(7 downto 4),b=>b(7 downto 4),s=>s(7 downto 4),cout=>carry_out2);u3:adder4b port map(clr=>clr,cin=>carry_out2,a=>a(11 downto 8),b=>b(11 downto 8),s=>s(11 downto 8),cout=>cout);end art;6.4 带异步清零/置位端的JK触发器设计带异步清零/置位端的JK触发器源程序如下：library ieee;use ieee.std_logic_1164.all;entity jkff_logic isport(j,k,clk,clr,set:in std_logic;q:out std_logic);end jkff_logic;architecture art of jkff_logic issignal q_s:std_logic;beginprocess(clk,clr,set,j,k)beginif set='0' thenq_s<='1'; --异步置位elsif clr='1' thenq<='0'; --异步复位elsif clk'event and clk='1' thenif (j='0') and (k='1') thenq_s<='0';elsif(j='1') and (k='0') thenq_s<='1';elsif(j='1') and (k='1') thenq_s<=not q_s;end if;end if;q<=q_s;end process;end art;6.5 4位锁存器设计子模块设计源代码：library ieee;use ieee.std_logic_1164.all;entity latch1b isport(d: in std_logic;ena: in std_logic; --使能端q: out std_logic);end latch1b;architecture art of latch1b isbeginprocess(d,ena)beginif ena='1' thenq<=d;end if;end process;end art;元件声明程序包设计源代码：library ieee;use ieee.std_logic_1164.all;package my_package iscomponent latch1port(d:in std_logic;ena:in std_logic;q: out std_logic);end component;end;顶层模块设计源代码：library ieee;use ieee.std_logic_1164.all;use work.my_package.all; --使用用户自定义的程序包entity latch4d isport(d: in std_logic_vector(3 downto 0);oen: in bit;q:out std_logic_vector(3 downto 0));end latch4d;architecture one of latch4d issignal sig_save:std_logic_vector(3 downto 0);begingetlatch:for n in 0 to 3 generate --用for_generate语句循环例化4个1位锁存器latchx:latch1 port map(d(n),g,sig_save(n)); --关联end generate;q<=sig_save when oen='0'else"ZZZZ";end one;6.6 32进制多样型计数器设计（1）32进制同步加法计数器源程序32进制同步加法计数器源程序如下：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity counter_plus isport(clk,clr:in std_logic;dout0,dout1: out std_logic_vector(3 downto 0));end;architecture art of counter_plus issignal d0,d1:std_logic_vector(3 downto 0); --d0代表个位，d1代表十位beginprocess(clk,clr,)beginif clr='1'thend1<=(others=>'0');d0<="0000"; --同步清零elsif clk'event and clk='1' thenif(d1=3 and d0=1)thend1<="0000";d0<="0000"; --计数到32时清零elsif(d0=1) thend0<="0000";d1<=d1+1;elsed0<=d0+1;end if;end if;dout1<=d1;dout0<=d0;end process;end art;（2）32进制同步减法计数器源程序32进制同步减法计数器源程序如下：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity counter_sub isport(clk,clr:in std_logic;dout0,dout1: out std_logic_vector(3 downto 0));end;architecture art of counter_sub issignal d0,d1:std_logic_vector(3 downto 0); --d0代表个位，d1代表十位beginprocess(clk,clr)beginif clr='1' thend1<="0000";d0<="0000"; --异步清零elsif clk'event and clk='1' thenif(d1=0 and d0=0) thend1<="0011";d0<="0001"; --设定容量31elsif(d0=0) thend0<="0001";d1<=d1-1;elsed0<=d0-1;d1<=d1;end if;end if;dout1<=d1;dout0<=d0;end process;end art;（3）32进制同步可逆计数器源程序32进制同步可逆计数器源程序如下：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity counter_reversible isport(clk,clr,s:in std_logic; --s=1加法计数，s=0减法计数dout0,dout1: out std_logic_vector(3 downto 0));end;architecture art of counter_reversible issignal d0,d1:std_logic_vector(3 downto 0); --d0代表个位，d1代表十位beginprocess(clk,clr,s)beginif clr='1'thend1<="0000";d0<="0000"; --异步清零elsif (clk'event and clk='1' )thenif s='1' thenif(d1=3 and d0=1) thend1<="0000";d0<="0000"; --计数到31时清零elsif(d0=1) thend0<="0000";d1<=d1+1;else d0<=d0+1;end if;elsif s='0' thenif(d1=0 and d0=0)thend1<="0011";d0<="0001"; --设定容量31elsif(d0=0) thend0<="0001";d1<=d1-1;elsed0<=d0-1;d1<=d1;end if;end if;end if;dout1<=d1;dout0<=d0;end process;end art;（4）32进制异步加法计数器源程序32进制异步加法计数器源程序如下：①子模块D触发器源程序设计。

vhdl语言100例程序

vhdl语言100例程序以下是100个关于VHDL语言的程序示例：1. 用VHDL编写一个计数器模块2. 用VHDL编写一个SR-Latch模块3. 用VHDL编写一个JK-Flip Flop模块4. 用VHDL编写一个D-Flip Flop模块5. 用VHDL编写一个T-Flip Flop模块6. 用VHDL编写一个复位计数器模块7. 用VHDL编写一个移位寄存器模块8. 用VHDL编写一个状态机模块9. 用VHDL编写一个MUX模块10. 用VHDL编写一个DeMUX模块11. 用VHDL编写一个加法器模块12. 用VHDL编写一个减法器模块13. 用VHDL编写一个乘法器模块14. 用VHDL编写一个除法器模块15. 用VHDL编写一个比较器模块16. 用VHDL编写一个位逻辑模块17. 用VHDL编写一个字逻辑模块18. 用VHDL编写一个数据选择器模块19. 用VHDL编写一个FIFO队列模块20. 用VHDL编写一个LIFO栈模块21. 用VHDL编写一个流水线模块22. 用VHDL编写一个中断控制器模块23. 用VHDL编写一个时钟分频器模块24. 用VHDL编写一个IO控制器模块25. 用VHDL编写一个SPI通信控制器模块26. 用VHDL编写一个I2C通信控制器模块27. 用VHDL编写一个UART通信控制器模块28. 用VHDL编写一个哈希函数模块29. 用VHDL编写一个随机数产生器模块30. 用VHDL编写一个CRC校验器模块31. 用VHDL编写一个AES加密算法模块32. 用VHDL编写一个DES加密算法模块33. 用VHDL编写一个SHA加密算法模块34. 用VHDL编写一个MD5加密算法模块35. 用VHDL编写一个RSA加密算法模块36. 用VHDL编写一个卷积滤波器模块37. 用VHDL编写一个峰值检测器模块38. 用VHDL编写一个平滑滤波器模块39. 用VHDL编写一个中值滤波器模块40. 用VHDL编写一个微处理器模块41. 用VHDL编写一个信号发生器模块42. 用VHDL编写一个信号采集器模块43. 用VHDL编写一个频率计算器模块44. 用VHDL编写一个相位计算器模块45. 用VHDL编写一个时序分析器模块46. 用VHDL编写一个正弦波产生器模块47. 用VHDL编写一个余弦波产生器模块48. 用VHDL编写一个数字滤波器模块49. 用VHDL编写一个数字信号处理器模块50. 用VHDL编写一个数字识别模块51. 用VHDL编写一个自动售货机模块52. 用VHDL编写一个二进制加法器模块53. 用VHDL编写一个二进制减法器模块54. 用VHDL编写一个二进制乘法器模块55. 用VHDL编写一个二进制除法器模块56. 用VHDL编写一个自然对数模块57. 用VHDL编写一个指数函数模块58. 用VHDL编写一个三角函数模块59. 用VHDL编写一个高斯滤波器模块60. 用VHDL编写一个激光传感器模块61. 用VHDL编写一个超声波传感器模块62. 用VHDL编写一个光电传感器模块63. 用VHDL编写一个温度传感器模块64. 用VHDL编写一个气压传感器模块65. 用VHDL编写一个陀螺仪模块67. 用VHDL编写一个电流传感器模块68. 用VHDL编写一个电容传感器模块69. 用VHDL编写一个磁场传感器模块70. 用VHDL编写一个通信电缆模块71. 用VHDL编写一个电源控制器模块72. 用VHDL编写一个电机控制器模块73. 用VHDL编写一个汽车控制器模块74. 用VHDL编写一个飞机控制器模块75. 用VHDL编写一个摄像头模块76. 用VHDL编写一个音频控制器模块77. 用VHDL编写一个扬声器控制器模块78. 用VHDL编写一个拨号器模块79. 用VHDL编写一个振动控制器模块80. 用VHDL编写一个压力控制器模块81. 用VHDL编写一个过滤器模块82. 用VHDL编写一个微波发射模块84. 用VHDL编写一个智能电表模块85. 用VHDL编写一个闹钟模块86. 用VHDL编写一个计时器模块87. 用VHDL编写一个时间戳模块88. 用VHDL编写一个脉冲宽度模块89. 用VHDL编写一个电路仿真模块90. 用VHDL编写一个电路控制模块91. 用VHDL编写一个电路测试模块92. 用VHDL编写一个电路优化模块93. 用VHDL编写一个电路布局模块94. 用VHDL编写一个电路验证模块95. 用VHDL编写一个数字信号发生器模块96. 用VHDL编写一个数字信号反演器模块97. 用VHDL编写一个数字信号滤波器模块98. 用VHDL编写一个数字信号加速器模块99. 用VHDL编写一个数字信号降噪器模块100. 用VHDL编写一个数字信号解调器模块VHDL语言是一种硬件描述语言，它用于描述数字电路和系统。

EDA含有(程序-示例图全套)实验报告(吐血推荐)

实验报告(2012----2013学年第一学期)课程名称：EDA技术专业班级：学号：姓名：实验一：原理图输入法设计与仿真实验时间：2012年10月19日（第七周）六、实验心得实验二七人表决器的设计3、引脚匹配实验三显示电路设计一、实验目的1、学习7段数码显示译码器设计；2、学习VHDL 的多层设计方法。

二、实验仪器设备1、PC 机一台2、GW48-PK2系列SOPC/EDA 实验开发系统三、实验原理1、七段数码显示工作原理（共阴极接法）7 段数码是纯组合电路，通常的小规模专用IC ，如74 或4000系列的器件只能作十进制BCD 码译码，然而数字系统中的数据处理和运算都是2 进制的，所以输出表达都是16 进制的，为了满足16 进制数的译码显示，最方便的方法就是利用译码程序在FPGA/CPLD 中来实现。

作为7 段译码器，输出信号LED7S 的7 位分别接数码管的7 个段，高位在左，低位在右。

例如当LED7S 输出为“1101101”时，数码管的7 个段：g 、f 、e 、d 、c 、b 、a 分别接1、1、0、1、1、0、1；接有高电平的段发亮，于是数码管显示“5”。

注意，这里没有考虑表示小数点的发光管，如果要考虑，需要增加段h 。

2、显示代码概念显示代码a b cdefg四、实验内容1、编写7段译码器VHDL 源程序。

2、在Quartus Ⅱ软件上编译和仿真。

3、锁定管脚，建议选择实验电路模式6，显示译码输出用数码8 显示译码输出(PIO46-PIO40)，键8、键7、键6 和键5 四位控制输入。

4编程下载与硬件验证。

5、记录系统仿真和硬件验证结果。

五、实验结果：2、波形仿真图：4、引脚锁定：六、实验心得：其实本实验的显示我们在模电里面就学习过了，也用集成块进行过实验，本实验用程序加硬件完成。

真所谓条条道路通罗马！实验四四位全加器一、实验目的通过实验让学生熟悉Quartus Ⅱ的VHDL 文本设计流程全过程，掌握组合逻辑电路的文本输入设计法，通过对设计电路的仿真和硬件验证，让学生进一步了解加法器的功能。

vhdl编程实例

vhdl编程实例VHDL编程实例- 设计与实现一个4位的全加器在本篇文章中，我们将一步一步地回答如何设计和实现一个4位的全加器。

VHDL编程语言将是我们用于描述和模拟这个电路的工具。

第一步：理解全加器的原理在编写代码之前，我们首先需要理解全加器的原理。

全加器是一种用于对两个二进制数字进行相加的电路。

它接收三个输入信号：两个位的输入（A 和B）以及一个进位输入（C_in）。

全加器的输出结果为一个位的和（S）和一个进位输出（C_out）。

我们可以使用如下的真值表来描述全加器的输出结果：输入信号输出结果A B C_in S C_out0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1了解了全加器的工作原理后，我们可以开始编写代码了。

第二步：编写全加器的VHDL代码我们将使用VHDL语言来描述和模拟全加器。

下面是一个简单的4位全加器的VHDL代码实现：vhdlEntity声明entity full_adder isport (A, B : in std_logic_vector(3 downto 0);C_in : in std_logic;S : out std_logic_vector(3 downto 0);C_out : out std_logic);end full_adder;Architecture声明architecture Behavioral of full_adder isbeginprocess(A, B, C_in)variable carry : std_logic;begincarry := C_in;for i in 0 to 3 loopS(i) <= A(i) xor B(i) xor carry;carry := (A(i) and B(i)) or (carry and (A(i) xor B(i)));end loop;C_out <= carry;end process;end Behavioral;在此代码中，我们首先声明了一个实体（entity）和一个架构（architecture）。

EDA技术及应用-VHDL版(第三版)(潭会生)第7章详解

第7章 EDA技术实验
CLK CLR ENA
CNT10
CLK
U0
CLR
ENA
CQ[3..0] CO
DOUT[3..0] S0
CNT10
CLK
U1
CLR
ENA
CQ[3..0] CO
DOUT[7..4] S1
CNT10
CLK CLR ENA
U2 CQ[3..0] CO
DOUT[11..8] S2
CNT10 U3
第7章 EDA技术实验
ห้องสมุดไป่ตู้验证清零功能
验证使能有效
验证计数功能
预计可能结果
图7.2 CNT10仿真输入设置及可能结果估计图
第7章 EDA技术实验
4) 管脚锁定文件根据图7.1所示的CNT9999电路原理图，本设计实体的输入有时钟信号CLK、清零信号CLR和计数使能信号ENA，输出为DOUT[15..0]，据此可选择实验电路结构图NO.0，对应实验模式0。根据图7.5所示的实验电路结构图NO.0和图7.1确定引脚的锁定。选用EPM7128S-PL84芯片，其引脚锁定过程如表 7.1所示，其中CLK接CLOCK2，CLR接键3，ENA接键4，计数结果DOUT[3..0]、DOUT[7..4]、DOUT[11..8]、 DOUT[15..12]经外部译码器译码后，分别在数码管1、数码管2、数码管3、数码管4上显示。
第7章 EDA技术实验
3．实验要求 (1) 画出系统的原理框图，说明系统中各主要组成部分的功能。 (2) 编写各个VHDL源程序。 (3) 根据系统的功能，选好测试用例，画出测试输入信号波形或编好测试程序。 (4) 根据选用的EDA实验开发装置编好用于硬件验证的管脚锁定表格或文件。 (5) 记录系统仿真、逻辑综合及硬件验证结果。 (6) 记录实验过程中出现的问题及解决办法。

EDA VHDL程序

10线－4线优先编码器的VHDL描述LIBRARY IEEE ;USE IEEE.STD_LOGIC_1164.ALL;ENTITY coder ISPORT ( din : IN STD_LOGIC_VECTOR(9 DOWNTO 0);output : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) );END coder;ARCHITECTURE behav OF CODER ISSIGNAL SIN : STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINPROCESS (DIN)BEGINIF (din(9)='0') THEN SIN <= "1001" ;ELSIF (din(8)=‟0‟) THEN SIN <= "1000" ;ELSIF (din(7)='0') THEN SIN <= "0111" ;ELSIF (din(6)='0') THEN SIN <= "0110" ;ELSIF (din(5)='0') THEN SIN <= "0101" ;ELSIF (din(4)='0') THEN SIN <= "0100" ;ELSIF (din(3)='0') THEN SIN <= "0011" ;ELSIF (din(2)='0') THEN SIN <= "0010" ;ELSIF (din(1)='0') THEN SIN <= "0001" ;ELSE SIN <= “0000” ;END IF；END PROCESS ；Output <= sin ；END behav;计数器1 LIBRARY IEEE;2 USE IEEE.STD_LOGIC_1164.ALL;3 use IEEE.std_logic_unsigned.all;4 ENTITY CNT4 IS5 PORT ( CLK : IN STD_LOGIC ;6 Q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)) ;7 END CNT4;8 ARCHITECTURE bhv OF CNT4 IS9 SIGNAL Q1 : STD_LOGIC_VECTOR(3 DOWNTO 0);10 BEGIN11 PROCESS (CLK) BEGIN12 IF RISING_EDGE(CLK) zhen13 IF Q1 < 15 THEN14 Q1 <= Q1 + 1 ;15 ELSE16 Q1 <= (OTHERS => '0');17 END IF;18 END IF;19 END PROCESS ;20 Q <= Q1;21 END bhv;228位分频器程序设计LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY PULSE ISPORT ( CLK : IN STD_LOGIC;D : IN STD_LOGIC_VECTOR (7 DOWNTO 0);FOUT : OUT STD_LOGIC );END;ARCHITECTURE one OF PULSE ISSIGNAL FULL : STD_LOGIC;BEGINP_REG: PROCESS(CLK)VARIABLE CNT8 : STD_LOGIC_VECTOR(7 DOWNTO 0);BEGINIF CLK‟EVENT AND CLK = …1‟ THENIF CNT8 = "11111111" THENCNT8 := D; --当CNT8计数计满时，输入数据D被同步预置给计数器CNT8FULL <= '1'; --同时使溢出标志信号FULL输出为高电平ELSE CNT8 := CNT8 + 1; --否则继续作加1计数FULL <= '0'; --且输出溢出标志信号FULL为低电平END IF;END IF;END PROCESS P_REG;P_DIV: PROCESS(FULL)VARIABLE CNT2 : STD_LOGIC;BEGINIF FULL'EVENT AND FULL = '1' THENCNT2 <= NOT CNT2; --如果溢出标志信号FULL为高电平，D触发器输出取反IF CNT2 = '1' THEN FOUT <= '1';ELSE FOUT <= '0';END IF;END IF;END PROCESS P_DIV;END;同步递增计数器USE IEEE.STD_LOGIC_1164.ALL;USE IEEE STD_LOGIC_UNSIGNED.ALL;ENTITY Exe_8 IS ；PORT ( CLK: IN STD_LOGIC;Q: BUFFER STD_LOGIC_VECTOR (7 DOWNTO 0));END Exe_8;ARCHITECTURE a OF Exe_8 ISBEGINPROCESS(CLK)VARIABLE QTEMP : STD_LOGIC_VECTOR(7 DOWNTO 0);BEGINIF CLK'EVENT AND CLK='1' THENQTEMP:=QTEMP+1;END IF;Q<=QTEMP;END PROCESS;END a;描述下列VHDL程序的逻辑功能:要求：指出输入、输出端子；实体功能说明；画出逻辑功能图。

EDA代码

ready_set <='1';
INCNT <="0000";
scan_code <=SHIFTIN(7 DOWNTO 0);
IF SHIFTIN(7 DOWNTO 0)=x"F0" THEN
release <='1';
பைடு நூலகம்
ELSE
release <='0';
END IF;
IF (SHIFTIN(7 DOWNTO 0)/=X"E0") AND (release='0') THEN
begin if preset='0' then
bcd10<="0000"; co_1<='0'; else if clk='1'and clk'event then
if bcd1="1000" and bcd10="0101" then co_1<='1';
elsif bcd1="1001" and bcd10="0101" then bcd10<="0000"; co_1<='0';
entity baoshi is port(clk_2KHz,clk_1KHz,clk1Hz:in std_logic; bcd10S,bcd1S,bcd10M,bcd1M:in std_logic_vector(3 downto 0); clkout:out std_logic);
end baoshi;

EDA的一些程序代码

8-3优先编码器设计（1）VHDL代码LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY LS183 ISPORT (A,B,C,D,E,F,G,H: IN STD_LOGIC;L :OUT STD_LOGIC_VECTOR(2 DOWNTO 0);VGA :OUT STD_LOGIC_VECTOR(3 DOWNTO 0));END ENTITY;ARCHITECTURE BHV OF LS183 ISSIGNAL ABC : STD_LOGIC_VECTOR(7 DOWNTO 0);BEGINABC <= A & B & C & D & E & F & G & H; -- 并置A，B，C三个端口到信号ABC，便于编程VGA <= "0001"; -- 实验箱功能选择位设置PROCESS (ABC)BEGINIF ABC(0) = '0' THEN L <= "000";ELSIF ABC(1 DOWNTO 0) = "01" THEN L<="001";ELSIF ABC(2 DOWNTO 0) = "011" THEN L<="010";ELSIF ABC(3 DOWNTO 0) = "0111" THEN L<="011";ELSIF ABC(4 DOWNTO 0) = "01111" THEN L<="100";ELSIF ABC(5 DOWNTO 0) = "011111" THEN L<="101";ELSIF ABC(6 DOWNTO 0) = "0111111" THEN L<="110";ELSIF ABC(7 DOWNTO 0) = "01111111" THEN L<="111";END IF;END PROCESS;END ARCHITECTURE;时序仿真Test Bench文件内容（不含注释）及仿真波形图仿真时制作的Test Bench文件添加：WAIT FOR 200 ns; A<='0'; B<='1'; C<='1';D<='1';E<='1';F<='1';G<='1';H<='0';W AIT FOR 200 ns; A<='1'; B<='0'; C<='1';D<='1';E<='1';F<='1';G<='0';H<='1';W AIT FOR 200 ns; A<='1'; B<='1'; C<='0';D<='0';E<='0';F<='0';G<='1';H<='1';W AIT FOR 200 ns; A<='1'; B<='1'; C<='1';D<='0';E<='0';F<='1';G<='1';H<='1';W AIT FOR 200 ns; A<='1'; B<='1'; C<='1';D<='0';E<='1';F<='1';G<='1';H<='1';W AIT FOR 200 ns; A<='1'; B<='1'; C<='0';D<='1';E<='1';F<='1';G<='1';H<='1';W AIT FOR 200 ns; A<='1'; B<='0'; C<='1';D<='1';E<='1';F<='1';G<='1';H<='1';W AIT FOR 200 ns; A<='0'; B<='1'; C<='1';D<='1';E<='1';F<='1';G<='1';H<='1';8421码奇偶校验位发生器设计（1）VHDL代码LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL;ENTITY xor42 ISPORT (B8,B4,B2,B1: IN STD_LOGIC;P, NP:OUT STD_LOGIC;VGA :OUT STD_LOGIC_VECTOR(3 DOWNTO 0));END ENTITY;ARCHITECTURE BHV OF XOR42 ISSIGNAL e,f,g : STD_LOGIC;BEGINVGA <= "0001";e <= B8 XOR B4;f <= B2 XOR B1;g <= e XOR f;p <= g;NP <=g XOR '1';END ARCHITECTURE;注意：在Entity中务必添加VGA功能选择端口：VGA :OUT STD_LOGIC_VECTOR(3 DOWNTO 0)在Architecture中务必添加功能选择设置：VGA <= "0001";（2）时序仿真Test Bench文件内容（不含注释）及仿真波形图LIBRARY ieee;USE ieee.std_logic_1164.all;ENTITY xor42_vhd_tst ISEND xor42_vhd_tst;ARCHITECTURE xor42_arch OF xor42_vhd_tst IS-- constants-- signalsSIGNAL B1 : STD_LOGIC;SIGNAL B2 : STD_LOGIC;SIGNAL B4 : STD_LOGIC;SIGNAL B8 : STD_LOGIC;SIGNAL NP : STD_LOGIC;SIGNAL P : STD_LOGIC;SIGNAL VGA : STD_LOGIC_VECTOR(3 DOWNTO 0); COMPONENT xor42PORT (B1 : IN STD_LOGIC;B2 : IN STD_LOGIC;B4 : IN STD_LOGIC;B8 : IN STD_LOGIC;NP : OUT STD_LOGIC;P : OUT STD_LOGIC;VGA : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) );END COMPONENT;BEGINi1 : xor42PORT MAP (-- list connections between master ports and signals B1 => B1,B2 => B2,B4 => B4,B8 => B8,NP => NP,P => P,VGA => VGA);init : PROCESS-- variable declarationsBEGIN-- code that executes only onceWAIT FOR 100 ns; B8<='0';B4<='0';B2<='0';B1<='0'; WAIT FOR 100 ns; B8<='0';B4<='0';B2<='0';B1<='1'; WAIT FOR 100 ns; B8<='0';B4<='0';B2<='1';B1<='0'; WAIT FOR 100 ns; B8<='0';B4<='0';B2<='1';B1<='1'; WAIT FOR 100 ns; B8<='0';B4<='1';B2<='0';B1<='0'; WAIT FOR 100 ns; B8<='0';B4<='1';B2<='0';B1<='1'; WAIT FOR 100 ns; B8<='0';B4<='1';B2<='1';B1<='0'; WAIT FOR 100 ns; B8<='0';B4<='1';B2<='1';B1<='1'; WAIT FOR 100 ns; B8<='1';B4<='0';B2<='0';B1<='0'; WAIT FOR 100 ns; B8<='1';B4<='0';B2<='0';B1<='1'; WAIT FOR 100 ns; B8<='1';B4<='0';B2<='1';B1<='0';WAIT FOR 100 ns; B8<='1';B4<='0';B2<='1';B1<='1'; WAIT FOR 100 ns; B8<='1';B4<='1';B2<='0';B1<='0'; WAIT FOR 100 ns; B8<='1';B4<='1';B2<='0';B1<='1'; WAIT FOR 100 ns; B8<='1';B4<='1';B2<='1';B1<='0'; WAIT FOR 100 ns; B8<='1';B4<='1';B2<='1';B1<='1'; WAIT;END PROCESS init;always : PROCESS-- optional sensitivity list-- ( )-- variable declarationsBEGIN-- code executes for every event on sensitivity list WAIT;END PROCESS always;END xor42_arch;\半加器设计（1）VHDL代码LIBRARY IEEE; --半加器USE IEEE.STD_LOGIC_1164.ALL;ENTITY h_adder ISPORT (a,b: IN STD_LOGIC;co,so:OUT STD_LOGIC);END ENTITY;ARCHITECTURE fh1 OF h_adder ISSIGNAL abc:STD_LOGIC_VECTOR(1 DOWNTO 0); BEGINabc<=a & b;PROCESS(abc)BEGINCASE abc ISWHEN"00"=>so<='0';co<='0';WHEN"01"=>so<='1';co<='0';WHEN"10"=>so<='1';co<='0';WHEN"11"=>so<='0';co<='1';WHEN OTHERS=>NULL;END CASE;END PROCESS;END ARCHITECTURE fh1;注意：在Entity中务必添加VGA功能选择端口：VGA :OUT STD_LOGIC_VECTOR(3 DOWNTO 0)在Architecture中务必添加功能选择设置：VGA <= "0001";（2）时序仿真Test Bench文件内容（不含注释）及仿真波形图LIBRARY ieee;USE ieee.std_logic_1164.all;ENTITY f_adder_vhd_tst ISEND f_adder_vhd_tst;ARCHITECTURE f_adder_arch OF f_adder_vhd_tst IS-- constants-- signalsSIGNAL ain : STD_LOGIC;SIGNAL bin : STD_LOGIC;SIGNAL cin : STD_LOGIC;SIGNAL cout : STD_LOGIC;SIGNAL sum : STD_LOGIC;SIGNAL VGA : STD_LOGIC_VECTOR(3 DOWNTO 0);COMPONENT f_adderPORT (ain : IN STD_LOGIC;bin : IN STD_LOGIC;cin : IN STD_LOGIC;cout : OUT STD_LOGIC;sum : OUT STD_LOGIC;VGA : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));END COMPONENT;BEGINi1 : f_adderPORT MAP (-- list connections between master ports and signalsain => ain,bin => bin,cin => cin,cout => cout,sum => sum,VGA => VGA);init : PROCESS-- variable declarationsBEGIN-- code that executes only onceWAIT FOR 100 ns; ain<='0';bin<='0';cin<='0';WAIT FOR 100 ns; ain<='0';bin<='0';cin<='1';WAIT FOR 100 ns; ain<='0';bin<='1';cin<='0';WAIT FOR 100 ns; ain<='0';bin<='1';cin<='1';WAIT FOR 100 ns; ain<='1';bin<='0';cin<='0';WAIT FOR 100 ns; ain<='1';bin<='0';cin<='1';WAIT FOR 100 ns; ain<='1';bin<='1';cin<='0';WAIT FOR 100 ns; ain<='1';bin<='1';cin<='1';WAIT;END PROCESS init;always : PROCESS-- optional sensitivity list-- ( )-- variable declarationsBEGIN-- code executes for every event on sensitivity listWAIT;END PROCESS always;END f_adder_arch;带使能输入及同步清零的增1计数器（1）VHDL代码注意：在Entity中务必添加VGA功能选择端口：VGA :OUT STD_LOGIC_VECTOR(3 DOWNTO 0)在Architecture中务必添加功能选择设置：VGA <= "0001";LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CNT16 ISPORT (CLK,CLR,EN : IN STD_LOGIC;Q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);VGA : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));END CNT16;ARCHITECTURE behav OF CNT16 ISBEGINVGA <="0001";PROCESS (CLK,CLR,EN)V ARIABLE QI : STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINIF CLR = '1' THEN QI := (OTHERS =>'0');ELSIF CLK'EVENT AND CLK='1' THENIF EN ='1' THEN QI:=QI+1;ELSE QI := (OTHERS =>'0');END IF;END IF;Q <= QI;END PROCESS;END behav;（2）时序仿真Test Bench文件内容（不含注释）及仿真波形图生成Test Bench模板文件，做以下修改：在Architecture的常数声明部分添加……-- constantsCONSTANT clk_period : TIME := 40 ns; -- 该常数用于设置时钟周期，40 ns两个进程修改如下：init : PROCESS-- variable declarationsBEGIN-- code that executes only onceWAIT FOR 100 ns; en <='1';WAIT FOR 1500 ns; clr<='1';WAIT FOR 200 ns; clr<='0';WAIT;END PROCESS init;always : PROCESSBEGIN-- code executes for every event on sensitivity listclk<='1'; WAIT FOR clk_period/2;-- 时钟信号的Test Bench的一般描述clk<='0'; WAIT FOR clk_period/2;END PROCESS always;……其中黑体部分，是时钟信号仿真Test Bench的描述方式之一。

EDA中的VHDL代码

Eda中常用的程序集合1.六十进制计数器：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity jsq60 isport (clk : in std_logic;co : out std_logic;y : out integer range 0 to 59); end jsq60;architecture one of jsq60 issignal yy : integer range 0 to 59; beginprocess(clk)beginif clk'event and clk = '1' thenyy<=yy+1;end if;if yy=15 thenco<='1';elseco<='0';end if;end process;y<=yy;end one;2.一百进制计数器：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity jsq100 isport (clk : in std_logic;co : out std_logic;y : out integer range 0 to 99); end jsq100;architecture one of jsq100 issignal yy : integer range 0 to 99; beginprocess(clk)beginif clk'event and clk = '1' thenyy<=yy+1;end if;if yy=99 thenco<='1';elseco<='0';end if;end process;y<=yy;end one;3.三八译码器：library ieee;use ieee.std_logic_1164.all;entity ym3_8 isport(a:in std_logic_vector(2 downto 0);b:out std_logic_vector(0 to 7)); end ym3_8;architecture rtl of ym3_8 isbeginprocess(a)begincase a iswhen"000"=> b<="11111110";when"001"=> b<="11111101";when"010"=> b<="11111011";when"011"=> b<="11110111";when"100"=> b<="11101111";when"101"=> b<="11011111";when"110"=> b<="10111111";when"111"=> b<="01111111";when others=>b<="00000000";end case;end process;end rtl;4.三人表决器的四种方法：附程序代码library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity bjq3 isport (a,b,c:in std_logic;y:out std_logic);end;architecture one of bjq3 isbeginy<=(a and b ) or (a and c) or (b and c ); end;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity bjq3 isport (a,b,c:in std_logic;y:out std_logic);end;architecture one of bjq3 issignal m:std_logic_vector(2 downto 0);beginm<=a & b & c;y<='0' when (m="000")or(m="001")or(m="010")or(m=" 100" )else'1';end;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity bjq3 isport (a,b,c:in std_logic;y:out std_logic);end;architecture one of bjq3 issignal m: std_logic_vector(2 downto 0); beginm<=a&b&c;with m selecty<='0'when "000"|"001"|"010"|"100", '1'when others;end;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity bjq3 isport (m:in std_logic_vector(2 downto 0);y:out std_logic);end;architecture one of bjq3 isbeginprocess (m)begincase m iswhen "000"|"001"|"010"|"100"=>y<='0';when others =>y<='1';end case;end process;end;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity bjq3 isport (m:in std_logic_vector(2 downto 0);y:out std_logic);end;architecture one of bjq3 isbeginprocess (m)beginif m="000" then y<='0';elsif m="001"then y<='0';elsif m="010"then y<='0';elsif m="011"then y<='1';elsif m="100"then y<='0';elsif m="101"then y<='1';elsif m="110"then y<='1';elsif m="111"then y<='1';end if;end process;end;、5.八三编码器library ieee;use ieee.std_logic_1164.all;entity yxbm8_3 isport( a: in std_logic_vector(7 downto 0);b: out std_logic_vector(2 downto 0));end yxbm8_3;architecture one of yxbm8_3 isbeginprocess(a)beginif a(7)<='0' then b<="000";elsif a(6)<='0' then b<="001";elsif a(5)<='0' then b<="010";elsif a(4)<='0' then b<="011";elsif a(3)<='0' then b<="100";elsif a(2)<='0' then b<="101";elsif a(1)<='0' then b<="110";else b<="111";end if;end process;end one;6.六选一，四选一数码选择；；；LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;entity mux61 isport(d0,d1,d2,d3,d4,d5,a0,a1,a2:instd_logic;y:out std_logic);end mux61;architecture rtl of mux61 issignal a:std_logic_vector(2 downto 0); beginprocess(a0,a1,a2)begina<=a2&a1&a0;case a iswhen "000"=>y<=d0;when "001"=>y<=d1;when "010"=>y<=d2;when "011"=>y<=d3;when "100"=>y<=d4;when "101"=>y<=d5;when others=>null;end case;end process;end rtl;library ieee;use ieee.std_logic_1164.all;entity mux41a isport (d0,d1,d2,d3,a1,a0:in std_logic; Y:outstd_logic);end entity mux41a;architecture one of mux41a issignal m,n,o,p:std_logic;begin m<=(not a1) and (not a0)andd0;n<=(not a1) and a0 and d1;o<=a1 and (not a0) and d2; p<=a1 and a0 and d3 ;y<=m or n or o or p;end one;LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY max4_1 ISPORT(a,b,c,d,s1,s2 : IN STD_LOGIC;y : OUT STD_LOGIC);END ENTITY max4_1;ARCHITECTURE hf1 OF max4_1 ISSIGNAL ss : STD_LOGIC_VECTOR (0 TO 1); BEGINss<=s2&s1;PROCESS(ss)BEGINCASE ss ISWHEN "00" => y<=a;WHEN "01" => y<=b;WHEN "10" => y<=c;WHEN "11" => y<=d; WHEN OTHERS => NULL; END CASE;END PROCESS;END ARCHITECTURE hf1;。

EDA技术-VHDL-EDA技术-VHDL-3.3 8-3编码器a

8-3编码器程序设计与仿真实验1 实验目的(1) 熟悉软件的使用，了解使用EDA工具进行设计的全过程。

(2) 学会用VHDL语言进行逻辑电路设计。

2 实验原理8-3编码器有八个输入信号，输出是（2n＝8， n=3）三位二进制代码。

其编码表如表3.3.1所示。

表3.3.1 三位二进制编码器的编码表输入输出Y2 Y1Y0I0 0 0 0I10 0 1I20 1 0I30 1 1I4 1 0 0I5 1 0 1I6 1 1 0I7 1 1 1由编码表写出逻辑表达式如下：Y2=I4+I5+I6+I7Y1=I2+I3+I6+I7Y0=I1+I3+I5+I73 实验内容(1) 用VHDL语言编写8-3编码器源程序。

(2) 进行综合、优化及功能仿真。

4 实验预习与思考(1) 熟悉8-3编码器的工作原理。

(3) 如何在波形测试台窗口编辑输入信号。

(4) 在结构体中有几类功能描述语句，各起什么作用。

5 VHDL仿真实验(1)为此工程新建一个文件夹。

双击图标，启动QuartusⅡ软件工作平台。

新建工程设计文件名为encoder8_3.vhd。

在新建的VHDL模型窗口下编写的源程序如下：library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity encoder8_3 is --实体说明Port ( reset : in std_logic;input : in std_logic_vector(7 downto 0);output : out std_logic_vector(2 downto 0));end encoder8_3;architecture Behavioral of encoder8_3 is --结构体beginprocess(reset,input) --进程beginif ( reset = '1') thenoutput <= "000";elsecase input iswhen "00000001" => output <= "000";when "00000010" => output <= "001";when "00000100" => output <= "010";when "00001000" => output <= "011";when "00010000" => output <= "100";when "00100000" => output <= "101";when "01000000" => output <= "110";when "10000000" => output <= "111";when others=> output<="000";end case;end if;end process;end Behavioral;(2) 创建工程及全程编译完成源代码输入后即可创建工程。

eda实验程序vhdl语言

一、填空：1、完整VHDL语言程序包含、、、、五部分。

2、VHDL语言设计的基本单元是；其由和两部分组成。

3、PROCESS语句有三个敏感信号，他们顺序改变一次，则PROCESS语句执行次。

4、VHDL语言构造体的描述方式有、、三种；5、VHDL语言构造体的子结构描述有、、三种。

6、VHDL语言的客体有、、。

7、时钟上升沿的描述方式有、。

8、VHDL描述语句按执行顺序可分为、；他们的关系是。

9、在LOOP语句有两种形式，它们是和。

10、循环控制语句有和两条语句；在LOOP 语句中若想跳出本次循环应使用语句；若想结束整个循环体应使用语句。

11、常用的端口定义模式有、、、四种。

12、选用可编程逻辑器件完成一个设计时，从技术角度上来讲，选择器件的依据是：。

13、VHDL设计的最基本模块是：。

14、VHDL允许用三种描述方式来设计，即、、和，或者是这些方式的任意组合。

15、用VHDL设计某系统时，用到一种可枚举类型的数据，它的可能取值为：red，yellow，blue，orange，green。

用color来表示这种数据类型，试写出这种数据类型的定义：16、在利用HDL的硬件设计方法中，设计者将自上至下分成3个层次对系统硬件进行设计。

第一层次是；第二层次是；第三层次是。

17、由综合工具产生门级网络表后，在最终完成硬件设计时，可以有两种选择：第一种是做出；第二种是利用完成硬件电路设计。

18、一个完整的VHDL语言程序通常包含实体、构造体、配置、包集合和库5个部分。

它们的作用分别为：实体用于描述；构造体用于描述；包集合存放格设计模块都能共享的等；配置用于库存放已经编译的；19、在用VHDL语言进行设计时，一个基本设计单元，不管是简单的数字电路还是复杂的数字电路，其基本构成是一致的。

它们都是由和两部分构成。

20、EDA即电子设计自动化。

所谓自动化是指。

EDA技术方法中，是进行设计验证的主要手段。

21、在LOOP语句中若想跳出本次循环应使用语句；若想结束循环状态应使用语句。

EDA 第3章 VHDL语言 3.3全加器的VHDL描述

3.3 全加器的VHDL描述
3.3.2 CASE语句
1. CASE语句
CASE <表达式> IS When <选择值或标识符> => <顺序语句>; ... ; <顺序语句> ； When <选择值或标识符> => <顺序语句>; ... ; <顺序语句> ； ...
WHEN OTHERS => <顺序语句>;
component元件名port端口名表endcomponent文件名33vhdl333例化语句在组件映射部分其中的端口名是在元件组件定义语句中的端口名表中已定义好的元件端口的名字或者说是顶层文件中待连接的各个元件本身的端口名
3.3 全加器的VHDL描述
目的：进一步学习VHDL的语法
重点：1、CASE语句的用法
3.3 全加器的VHDL描述
【例3-17】 LIBRARY IEEE ; --或门逻辑描述 USE IEEE.STD_LOGIC_1164.ALL; ENTITY or2a IS PORT (a, b :IN STD_LOGIC; c : OUT STD_LOGIC ); END ENTITY or2a； ARCHITECTURE one OF or2a IS BEGIN c <= a OR b ; END ARCHITECTURE one ;
3.3 全加器的VHDL描述
3.3.1 半加器描述 –真值表描述方法
【例3-16】 LIBRARY IEEE; --半加器描述(2)：真值表描述方法 USE IEEE.STD_LOGIC_1164.ALL; ENTITY h_adder IS PORT (a, b : IN STD_LOGIC; co, so : OUT STD_LOGIC); END ENTITY h_adder; ARCHITECTURE fh1 OF h_adder is SIGNAL abc : STD_LOGIC_VECTOR(1 DOWNTO 0) ; --定义标准逻辑位矢量数据类型 BEGIN abc <= a & b ; --a相并b，即a与b并置操作 PROCESS(abc) BEGIN CASE abc IS --类似于真值表的CASE语句 WHEN "00" => so<='0'; co<='0' ; WHEN "01" => so<='1'; co<='0' ; WHEN "10" => so<='1'; co<='0' ; WHEN "11" => so<='0'; co<='1' ; WHEN OTHERS => NULL ; END CASE; END PROCESS; END ARCHITECTURE fh1 ;

EDA_VHDL_并入串出移位寄存器

WAIT; END PROCESS init; …
… always : PROCESS -- optional sensitivity list -- ( ) -- variable declarations BEGIN wait for 50ns; clk<=not clk; END PROCESS always; …
--load=0则预置数
elsif clk’event and clk=’1’then
qq(7 downto 1)<=qq(6 downto 0);
end if;
y<=qq(7); --高位赋予串行输出端口
dataout<=qq;
end process;
end yw_arch;
--否则上升沿到 --左移
init : PROCESS
-- variable declarations
BEGIN
wait for 100ns;load<='1';
wait for 100ns;data<="10010110";
wait for 100ns;load<='0';
wait for 100ns;load<='1'; -- code that executes only once
Template Writer 新建test bench文件，作为 modelsim仿真的测试平台；根据需求修改test bench文件
并入、并出和串出移位寄存器
5.通过AssignmentsSettingSimulation Compile test bench添加仿真测试平台，相关设置如右图所示

EDA试验程序VHDL

EDA 试验程序VHDLLIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYDECL7SISPORT(A:INSTD_LOGIC_VECTOR(3DOWNTO0); LED7S:OUTSTD_LOGIC_VECTOR(6DOWNTO0));END;ARCHITECTUREoneOFDECL7SISBEGINPROCESS(A) BEGINCASEAISWHEN"0000"=LED7S="0111111"; WHEN"0001"=LED7S="0000110";WHEN"0010"=LED7S="1011011";WHEN"0011"=LED7S="1001111";WHEN"0100"=LED7S="1100110";WHEN"0101"=LED7S="1101101";WHEN"0110"=LED7S="1111101";WHEN"0111"=LED7S="0000111";WHEN"1000"=LED7S="1111111";WHEN"1001"=LED7S="1101111";WHEN"1010"=LED7S="1110111";WHEN"1011"=LED7S="1111100"; WHEN"1100"=LED7S="0111001"; WHEN"1101"=LED7S="1011110"; WHEN"1110"=LED7S="1111001"; WHEN"1111"=LED7S="1110001"; WHENOTHERS=NULL;ENDCASE;ENDPROCESS;END;数控分频器的设计LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL; ENTITYDVFISPORT(CLK:INSTD_LOGIC;D:INSTD_LOGIC_VECTOR(7DOWNTO0);FOUT:OUTSTD_LOGIC);END; ARCHITECTUREoneOFDVFISSIGNALFULL:STD_LOGIC; BEGINP_REG:PROCESS(CLK)VARIABLECNT8:STD_LOGIC_VECTOR(7DOWNTO0);BEGINIFCLK'EVENTANDCLK='1'THENIFCNT8="11111111"THENCNT8:=D; FULL='1';ELSECNT8:=CNT8+1;FULL='0';ENDIF;ENDIF;ENDPROCESSP_REG;P_DIV:PROCESS(FULL)VARIABLECNT2:STD_LOGIC;BEGINIFFULL'EVENTANDFULL='1'THENCNT2:=NOTCNT2;IFCNT2='1'THENFOUT='1';ELSEFOUT='0';ENDIF;ENDIF;ENDPROCESSP_DIV;END;8位数码扫描显示电路设计LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYSCAN_LEDISPORT(CLK:INSTD_LOGIC;SG:OUTSTD_LOGIC_VECTOR(6DOWNTO0);BT:OUTSTD_LOGIC_VECTOR(7DOWNTO0));END;ARCHITECTUREoneOFSCAN_LEDISSIGNALCNT8:STD_LOGIC_VECTOR(2DOWNTO0); SIGNALA:INTEGERRANGE0TO15;BEGINP1:PROCESS(CNT8)BEGINCASECNT8ISWHEN"000"=BT="00000001";A=1;WHEN"001"=BT="00000010";A=3;WHEN"010"=BT="00000100";A=5;WHEN"011"=BT="00001000";A=7;WHEN"100"=BT="00010000";A=9;WHEN"101"=BT="00100000";A=11;WHEN"110"=BT="01000000";A=13;WHEN"111"=BT="10000000";A=15;WHENOTHERS=NULL;ENDCASE;ENDPROCESSP1;P2:PROCESS(CLK)BEGINIFCLK'EVENTANDCLK='1'THENCNT8=CNT8+1; ENDIF;ENDPROCESSP2;P3:PROCESS(A)BEGINCASEAISWHEN0=SG="0111111";WHEN1=SG="0000110"; WHEN2=SG="1011011";WHEN3=SG="1001111";WHEN4=SG="1100110";WHEN5=SG="1101101";WHEN6=SG="1111101";WHEN7=SG="0000111";WHEN8=SG="1111111";WHEN9=SG="1101111";WHEN10=SG="1110111";WHEN11=SG="1111100";WHEN12=SG="0111001";WHEN13=SG="1011110";WHEN14=SG="1111001";WHEN15=SG="1110001"; WHENOTHERS=NULL;ENDCASE;ENDPROCESSP3;END;用QuatussII设计正弦信号发生器LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYSINGTISPORT(CLK:INSTD_LOGIC;DOUT:OUTSTD_LOGIC_VECTOR(7DOWNTO0));END;ARCHITECTUREDACCOFSINGTISCOMPONENTdata_romPORT(address:INSTD_LOGI C_VECTOR(5DOWNTO0);inclock:INSTD_LOGIC;q:OUTSTD_LOGIC_VECTOR(7DOWNTO0));ENDCOMPONENT;SIGNALQ1:STD_LOGIC_VECTOR(5DOWNTO0)BEGINPROCESS(CLK)BEGINIFCLK'EVENTANDCLK='1'THENQ1=Q1+1;ENDIF;ENDPROCESS;u1:data_romPORTMAP(address=Q1,q=DOUT,inclock=CLK);END;7-7LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYFTCTRLISPORT(CLKK:INSTD_LOGIC;CNT_EN:OUTSTD_LOGIC;RST_CNT:OUTSTD_LOGIC;LOAD:OUTSTD_LOGIC);ENDFTCTRL; ARCHITECTUREbehavOFFTCTRLISSIGNALDiv2CLK:STD_LOGIC; BEGINPROCESS(CLKK)BEGINIFCLKK'EVENTANDCLKK='1'THENDiv2CLK=NOTDiv2clk; ENDIF;ENDPROCESS;PROCESS(CLKK,Div2CLK)BEGINIFCLKK='0'ANDDiv2CLK='0'THENRST_CNT='1'; ELSERST_CNT='0';ENDIF;ENDPROCESS;LOAD=NOTDiv2CLK;CNT_EN=Div2CLK;ENDbehav;7-8LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYREG32BISPORT(LK:INSTD_LOGIC;DIN:INSTD_LOGIC_VECTOR(31DOWNTO0);DOUT:OUTSTD_LOGIC_VECTOR(31DOWNTO0));ENDREG32B;ARCHITECTUREbehavOFREG32BISBEGINPROCESS(LK,DIN)BEGINIFLK'EVENTANDLK='1'THENDOUT=DIN;ENDIF;ENDPROCESS;ENDbehav;7-9LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYCOUNTER32BISPORT(FIN:INSTD_LOGIC;CLR:INSTD_LOGIC;ENABL:INSTD_LOGIC;DOUT:OUTSTD_LOGIC_VECTOR(31DOWNTO0));ENDCOUNTER32B;ARCHITECTUREbehavOFCOUNTER32BISSIGNALCQI:STD_LOGIC_VECTOR(31DOWNT O0);BEGINPROCESS(FIN,CLR,ENABL)BEGINIFCLR='1'THENCQI=(OTHERS='0');ELSIFFIN'EVENTANDFIN='1'THENIFENABL='1'THENCQI=CQI+1;ENDIF; ENDIF;ENDPROCESS;DOUT=CQI;ENDbehav;7-10LIBRARYIEEE;LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYFREQTESTISPORT(CLK1HZ:INSTD_LOGIC;FSIN:INSTD_LOGIC;DOUT:OUTSTD_LOGIC_VECTOR(31DOWNTO0));ENDFREQTEST; ARCHITECTUREstrucOFFREQTESTISCOMPONENTFTCTRLPORT(CLKK:INSTD_LOGIC; CNT_EN:OUTSTD_LOGIC;RST_CNT:OUTSTD_LOGIC;LOAD:OUTSTD_LOGIC);ENDCOMPONENT;COMPONENTCOUNTER32BPORT(FIN:INSTD_LOGIC;CLR:INSTD_LOGIC;ENABL:INSTD_LOGIC;DOUT:OUTSTD_LOGIC_VECTOR(31DOWNTO0)); ENDCOMPONENT;COMPONENTREG32BPORT(LK:INSTD_LOGIC;DIN:INSTD_LOGIC_VECTOR(31DOWNTO0);DOUT:OUTSTD_LOGIC_VECTOR(31DOWNTO0)); ENDCOMPONENT;SIGNALTSTEN1:STD_LOGIC;SIGNALCLR_CNT1:STD_LOGIC;SIGNALLOAD1:STD_LOGIC;SIGNALDTO1:STD_LOGIC_VECTOR(31DOWNTO0); SIGNALCARRY_OUT1:STD_LOGIC_VECTOR(31DOWNTO0); BEGINU1:FTCTRLPORTMAP(CLKK=CLK1HZ,CNT_EN=TSTEN1, RST_CNT=CLR_CNT1,Load=Load1);U2:REG32BPORTMAP(LK=Load1,DIN=DTO1,DOUT=DOUT); U3:COUNTER32BPORTMAP(FIN=FSIN,CLR=CLR_CNT1, ENABL=TSTEN1,DOUT=DTO1);ENDstruc;序列检测器设计LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYSCHKISPORT(DIN,CLK,CLR:INSTD_LOGIC;AB:OUTSTD_LOGIC_VECTOR(3DOWNTO0));ENDSCHK;ARCHITECTUREbehavOFSCHKISSIGNALQ:INTEGERRANGE0TO8;SIGNALD:STD_LOGIC_VECTOR(7DOWNTO0);BEGIND="11101010";PROCESS(CLK,CLR)BEGINIFCLR='1'THENQ=0;ELSIFCLK'EVENT'ANDCLK='1'THENCASEQISWHEN0=IFDIN=D(7)THENQ=1;ELSEQ =0;ENDIF;WHEN1=IFDIN=D(6)THENQ=2;ELSEQ=0;ENDIF;WHEN2=IFDIN=D(5)THENQ=3;ELSEQ=0;ENDIF;WHEN3=IFDIN=D(4)THENQ=4;ELSEQ=0;ENDIF;WHEN4=IFDIN=D(3)THENQ=5;ELSEQ=0;ENDIF;WHEN5=IFDIN=D(2)THENQ=6;ELSEQ=0;ENDIF;WHEN6=IFDIN=D(1)THENQ=7;ELSEQ=0;ENDIF;WHEN7=IFDIN=D(0)THENQ=8;ELSEQ=0;ENDIF;WHENOTHERS=Q=0;ENDCASE;ENDIF;ENDPROCESS;PROCESS(Q)BEGINIFQ=8THENAB="1010"; ELSEAB="1011";ENDIF;ENDPROCESS;ENDbehav;。

(完整word版)EDA-常见实例源程序代码vhdl

第4章用VHDL程序实现常用逻辑电路4.1 组合逻辑电路设计4.1.1 基本逻辑门library ieee;use iee.std_logic_1164.all;entity jbm isport(a,b: in bit;f1,f2,f3,f4,f5,f: out bit);end jbm;architecture a of jbm isbeginf1<=a and b; --构成与门f2<=a or b; --构成或门f<=not a; --构成非门f3<=a nand b; --构成与非门f4<=a nor b; --构成异或门f5<=not(a xor b); --构成异或非门即同门end;4.1.2 三态门library ieee;use ieee.std_logic_1164.all;entity tri_s isport(enable: in std_logic;datain: in std_logic_vector(7 downto 0);dataout: out std_logic_vector(7 downto0));end tri_s;architecture bhv of tri_s isbeginprocess(enable,datain)beginif enable='1' thendataout<=datain;elsedataout<="ZZZZZZZZ";end if;end process;end bhv;4.1.3 3-8译码器library ieee;use ieee.std_logic_1164.all;entity decoder3_8 isport(a,b,c,g1,g2a,g2b: in std_logic;y: out std_logic_vector(7 downto 0));end decoder3_8;architecture a of decoder3_8 issignal dz:std_logic_vector(2 downto 0);begindz<=c&b&a;process (dz,g1,g2a,g2b)beginif(g1='1'and g2a='0'and g2b='0')thencase dz iswhen "111"=> y<="01111111";when others=>y<="XXXXXXXX";end case;elseend if;end process;4.1.4 优先编码器library ieee;use ieee.std_logic_1164.allentity coder isport(din: in std_logic_vector(0 to 7);output: out std_logic_vector(0 to 2));end coder;architecture behave of coder issignal sint: std_logic_vevtor(4 downto 0);beginprocess(din)beginif (din(7)='0') thenoutput <= "000" ;elsif (din(6)='0') thenoutput <= "100" ;elsif (din(5)='0') thenoutput <= "010" ;elsif (din(4)='0') thenoutput <= "110" ;elsif (din(3)='0') thenoutput <= "001" ;elsif (din(2)='0') thenoutput <= "101" ;elsif (din(1)='0') thenoutput <= "011" ;elseoutput <= "111" ;end if;end process;end behav;4.1.5 7段码译码器library ieee;use ieee.std_logic_1164.allentity decl7s isport (a: in std_logic_vector (3 downto 0);led7s: out std_logic_vector(6 downto 0));end decl7s;architecture behave of decl7s isbeginprocess(a)begincase a iswhen "0000" => led7s <= "0111111" ;when "0001" => led7s <= "0000110" ;when "0010" => led7s <= "1011011" ;when "0011" => led7s <= "1001111" ;when "0100" => led7s <= "1100110" ;when "0101" => led7s <= "1101101" ;when "0110" => led7s <= "1111101" ;when "0111" => led7s <= "0000111" ;when "1000" => led7s <= "1111111" ;when "1001" => led7s <= "1101111" ;when "1010" => led7s <= "1110111" ;when "1011" => led7s <= "1111100" ;when "1100" => led7s <= "0111001" ;when "1101" => led7s <= "1011110" ;when "1110" => led7s <= "1111001" ;when "1111" => led7s <= "1110001" ;when others => null;end case;end process;end behave;4.1.6二-十进制BCD译码器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_signed.all;entity bcdymq isport(din : in integer range 15 downto 0;a,b : out integer range 9 downto 0);end;architecture fpq1 of bcdymq isbeginp1: process(din)beginif din<10 thena< =din;b< =0;elsea< =din-10;b< =1;end if;end process p1;end;4.1.7 多位加（减）法器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_signed.all;entity jianfaqi isport(a,b : in std_logic_vector(0 to 3);c0: in std_logic;c1: out std_logic;d : out std_logic_vector(0 to 3));end;architecture a of jianfaqi isbeginprocessbeginif a>b+c0 thend<=a-(b+c0);c1<='0';elsec1<='1';d<=("10000")-(b+c0-a);end if;end process ;end ;4.2 时序逻辑电路设计4.2.1 触发器RS触发器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_signed.all;entity rsff isport(r,s,clk:in std_logic;q,qb:buffer std_logic);end rsff;architecture rsff_art of rsff issignal q_s,qb_s:std_logic;beginprocess(clk,r,s)beginif (clk'event and clk='1') thenif (s='1' and r='0') thenq_s<='0' ;qb_s<='1' ;elsif (s='0' and r='1') thenq_s <= '1' ;qb_s <= '0' ;elsif (s='0' and r='0') thenq_s <= q_s;qb_s <= qb_s;end if;end if;q_s <= q_s;qb_s <= qb_s;end process;end rsff_art;同步复位D触发器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_signed.all;entity syndff isport(d,clk,reset:in std_logic;q,qb:out std_logic);end syndff;architecture dff_art of syndff isbeginprocess(clk)beginif (clk'event and clk='1') thenif (reset='0') thenq<='0';qb<='1';elseq<=d;qb<=not q;end if;end if;end process;end dff_art;JK触发器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_signed.all;entity asynjkff isport(j,k,clk,set.reset:in std_logic;q,qb:out std_logic);end asynjkff;architecture jkff_art of asynjkff issingal q_s,qb_s:std_logic;beginprocess(clk,set,reset)beginif (set='0' and reset='1' ) thenq_s<='1';qb_s<='0';elsif (set='1' and reset='0' ) thenq_s<='0';qb_s<='1';elsif (clk'event and clk='1') thenif (j='0' and k='1' ) thenq_s<='0';qb_s<='1';elsif (j='1' and k='0' ) thenq_s<='1';qb_s<='0';elsif (j='1' and k='1' ) thenq_s<=not q_s;qb_s<=not qb_s;end if;end if;q<= q_s;qb<= qb_s;end process;end jkff_art;T触发器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_signed.all;entity tff isport(t,clk: in std_logic;q: out std_logic);end;architecture tff_art of tff issignal q_temp: std_logic;beginp1:process(clk)beginif rising_edge(clk) thenif t='1' then --当T=1时T触发器具有2分频的功能q_temp<=not q_temp;elseq_temp<=q_temp;end if;end if;q<=q_temp;end process;q<=q_temp;end tff_art;4.2.2计数器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity cnt4 ISport( clk: in std_logic;q: out std_logic_vector(3 downto 0));end cnt4;architecture behave of cnt4 issignal q1: std_logic_vector(3 downto 0);beginprocess(clk)beginif (clk'event and clk = '1') thenq1<=q1+1;end if;end process;q<=q1;end behave;一般计数器设计library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity cnt10 isport( clk,rst,en,updown: in std_logic;cq: out std_logic_vector(3 downto 0));end cnt10;architecture behave of cnt10 isbeginprocess(clk,rst,en,updown)variable cqi:std_logic_vector(3 downto 0);beginif rst='1' thencqi:=(others=>'0'); --计数器异步复位elsif (clk'event and clk = '1') then --检测时钟上升沿if en='1'then --检测是否允许计数（同步使能）if updown='0'thenif cqi<9 thencqi:=cqi+1; --允许计数,检测是否小于9elsecqi:=(others=>'0'); --大于9，计数值清零end if;elseif cqi>0 thencqi:=cqi-1; --检测是否大于0elsecqi:=(others=>'1'); ---否则，计数值置1end if;end if;end if;end if;cq<=cqi; --将计数值向端口输出end process;end behave;4.2.3 分频器library ieee;use std_logic_1164.all;use std_logic_unsigned.all;entity freq1 isport(clk: in std_logic;d: in std_logic_vector(7 downto 0);fout: out std_logic);end;architecture one of dvf issignal full: std_logic;beginp_reg:process(clk)variable cnt8: std_logic_vector(7 downto 0);beginif clk'event and clk='1'then --检测时钟上升沿if cnt8='''' thencnt8:=d; --当CNT8计数计满时，输入数据D被同步预置给计数器CNT8full<='1';--同时使溢出标志信号FULL输出为高电平elsecnt8:=cnt8+1;--否则继续作加1计数full<='0'; --且输出溢出标志信号FULL为低电平end if;end if;end process p_reg;p_div:process(full)variable cnt2: std_logic;beginif full'event and full='1' thencnt2:=not cnt2; --如果溢出标志信号FULL为高电平，T触发器输出取反if cnt2='1'thenfout<='1';elsefout<='0';end if;end if;end process p_div;end;4.2.4 移位寄存器library ieee;use ieee.std_logic_1164.all;entity shift isport(clk,c0: in std_logic;--时钟和进位输入md: in std_logic_vector(2 downto 0);--移位模式控制字d: in std_logic_vector(7 downto 0);--待加载移位的数据qb: out std_logic_vector(7 downto 0);--移位数据输出cn: out std_logic);--进位输出end;architecture behave of shift issignal reg: std_logic_vector(7 downto 0);signal cy: std_logic;beginprocess(clk,md,c0)beginif clk'event and clk='1' thencase md iswhen "001" => reg (0) <= c0 ;reg (7 downto 1) <= reg (6 downto 0);cy <= reg (7); --带进位循环左移when "010" => reg (0) <= reg (7);reg (7 downto 1) <= reg (6 downto 0); --自循环左移when "011" => reg (7) <= reg (0);reg (6 downto 0) <= reg (7 downto 1); --自循环右移when "100" => reg (7) <= C0 ;reg (6 downto 0) <= reg (7 downto 1);cy <= reg (0); --带进位循环右移when "101" => reg (7 downto 0) <= d(7 downto 0); --加载待移数when others => reg<= reg ; cy<= cy ; --保持end case;end if;end process;qb(7 downto 0) <= reg (7 downto 0); cn <= cy; --移位后输出end behav;4.3 状态机逻辑电路设计4.3.1 一般状态机设计library ieee;use ieee.std_logic_1164.all;entity s_machine isport ( clk,reset : in std_logic;state_inputs : in std_logic_vector(0 to1);comb_outputs : out integer range 0 to 15 );end s_machine;architecture behv of s_machine istype fsm_st is (s0, s1, s2, s3); --数据类型定义，状态符号化signal current_state, next_state: fsm_st; --将现态和次态定义为新的数据类型beginreg: process(reset,clk) --主控时序进程beginif reset = '1' thencurrent_state <= s0; --检测异步复位信号elsif clk='1' and clk'event thencurrent_state <= next_state;end if;end process;com:process(current_state, state_inputs) --主控组合进程begincase current_state iswhen s0 => comb_outputs<= 5;if state_inputs = "00" thennext_state<=s0;elsenext_state<=s1;end if;when s1 => comb_outputs<= 8;if state_inputs = "00" thennext_state<=s1;elsenext_state<=s2;end if;when s2 => comb_outputs<= 12;if state_inputs = "11" thennext_state <= s0;elsenext_state <= s3;end if;when s3 => comb_outputs <= 14;if state_inputs = "11" thennext_state <= s3;elsenext_state <= s0;end if;end case;end process;end behv;4.3.2状态机的应用library ieee;use ieee.std_logic_1164.all;entity asm_led isport(clk,clr : in std_logic;led1,led2,led3:out std_logic);end;architecture a of asm_led istype states is (s0,s1,s2,s3,s4,s5); --对状态机的状态声明signal q: std_logic_vector( 0 to 2);signal state : states;beginp1: process(clk,clr)beginif(clr='0')thenstate<=s0;elsif (clk'event and clk='1') thencase state iswhen s0=> state <=s1;when s1=> state <=s2;when s2=> state <=s3;when s3=> state <=s4;when s4=> state <=s5;when s5=> state <=s0;when others => state<=s0;end case;end if;end process p1;p2: process (clr,state)beginif(clr='0') thenled1<='0';led2<='0';led3<='0';elsecase state iswhen s0=> led1<='1';led2<='0';led3<='0';when s1=> led1<='0';led2<='1';led3<='0';when s2=> led1<='0';led2<='1';led3<='0';when s3=> led1<='0';led2<='0';led3<='1';when s4=> led1<='0';led2<='0';led3<='1';when s5=> led1<='0';led2<='0';led3<='1';when others => null;end case;end if;end process p2;end ;第6章EDA仿真技术应用实例6.1带使能和片选端的16：4线优先编码器设计子模块设计源代码：library ieee;use ieee.std_logic_1164.all;entity pencoder isport(d:in std_logic_vector(7 downto 0);ei:in std_logic; --ei:enable inputgs,eo:out bit; --gs:chip select output;eo:enable outputq2,q1,q0:out std_logic);end pencoder;architecture encoder of pencoder isbeginprocess(d)beginif(d(0)='0' and ei='0')thenq2<='1';q1<='1';q0<='1';gs<='0';eo<='1';elsif(d(1)='0' and ei='0')thenq2<='1';q1<='1';q0<='0';gs<='0';eo<='1';elsif(d(2)='0' and ei='0')thenq2<='1';q1<='0';q0<='1';gs<='0';eo<='1';elsif(d(3)='0' and ei='0')thenq2<='1';q1<='0';q0<='0';gs<='0';eo<='1';elsif(d(4)='0' and ei='0')thenq2<='0';q1<='1';q0<='1';gs<='0';eo<='1';elsif(d(5)='0' and ei='0')thenq2<='0';q1<='1';q0<='0';gs<='0';eo<='1';elsif(d(6)='0' and ei='0')thenq2<='0';q1<='0';q0<='1';gs<='0';eo<='1';elsif(d(7)='0' and ei='0')then --d7 prioty encoderq2<='0';q1<='0';q0<='0';gs<='0';eo<='1';elsif(ei='1')thenq2<='1';q1<='0';q0<='1';gs<='1';eo<='1';'0')thenq2<='1';q1<='1';q0<='1';gs<='1';eo<='0';end if;end process;end encoder;6.27段显示译码器设计译码器设计源代码：library ieee;use ieee.std_logic_1164.all;entity decoder47 isport(lt,ibr,ib_ybr:in bit;a: in std_logic_vector(3 downto 0);y:out std_logic_vector(6 downto 0));end decoder47;architecture art of decoder47 isbeginprocess(lt,ibr,ib_ybr,a)variable s: std_logic_vector(3 downto 0);begins:=a(3)&a(2)&a(1)&a(0);if lt='0' and ib_ybr='1' theny<="1111111"; --检查七段显示管是否正常elsif ibr='0' and a="0000" theny<="0000000";elsecase s iswhen"0000"=>y<="1111110"; --7Ewhen"0001"=>y<="0110000"; --30when"0010"=>y<="1101101"; --6Dwhen"0011"=>y<="1111001"; --79when"0100"=>y<="0110011"; --33when"0101"=>y<="1011011"; --5Bwhen"0110"=>y<="0011111"; --5Fwhen"0111"=>y<="1110000"; --70when"1000"=>y<="1111111"; --7Ewhen"1001"=>y<="1110011"; --7Bwhen"1010"=>y<="0001101"; --0Dwhen"1011"=>y<="0011001"; --19when"1100"=>y<="0100011"; --23when"1101"=>y<="1001011"; --4Bwhen"1110"=>y<="0001111"; --0Fwhen"1111"=>y<="0000000";end case;end if;end process;end art;6.3带异步清零端的12位二进制全加器设计子模块源代码：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity adder4b isport(clr,cin: in std_logic;a,b: in std_logic_vector(3 downto 0);s: out std_logic_vector(3 downto 0);cout:out std_logic);end adder4b;architecture art of adder4b issignal sint:std_logic_vector(4 downto 0);signal aa,bb:std_logic_vector(4 downto 0);beginprocess(clr)beginif clr='1'thensint<="00000";elseaa<='0'&a;bb<='0'&b;sint<=aa+bb+cin;end if;s<=sint(3 downto 0);cout<=sint(4);end process;end art;顶层模块设计源代码：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity adder12b isport(clr,cin: in std_logic;a,b: in std_logic_vector(11 downto 0);s: out std_logic_vector(11 downto 0);cout:out std_logic);end adder12b;architecture art of adder12b iscomponent adder4b isport(clr,cin: in std_logic;a,b: in std_logic_vector(3 downto 0);s: out std_logic_vector(3 downto 0);cout:out std_logic);end component;signal carry_out1:std_logic;signal carry_out2:std_logic;beginu1:adder4b port map(clr=>clr,cin=>cin,a=>a(3 downto 0),b=>b(3 downto 0),s=>s(3 downto 0),cout=>carry_out1);u2:adder4b port map(clr=>clr,cin=>carry_out1,a=>a(7 downto 4),b=>b(7 downto 4),s=>s(7 downto 4),cout=>carry_out2);u3:adder4b port map(clr=>clr,cin=>carry_out2,a=>a(11 downto 8),b=>b(11 downto 8),s=>s(11 downto 8),cout=>cout);end art;6.4 带异步清零/置位端的JK触发器设计带异步清零/置位端的JK触发器源程序如下：library ieee;use ieee.std_logic_1164.all;entity jkff_logic isport(j,k,clk,clr,set:in std_logic;q:out std_logic);end jkff_logic;architecture art of jkff_logic issignal q_s:std_logic;beginprocess(clk,clr,set,j,k)beginif set='0' thenq_s<='1'; --异步置位elsif clr='1' thenq<='0'; --异步复位elsif clk'event and clk='1' thenif (j='0') and (k='1') thenq_s<='0';elsif(j='1') and (k='0') thenq_s<='1';elsif(j='1') and (k='1') thenq_s<=not q_s;end if;end if;q<=q_s;end process;end art;6.5 4位锁存器设计子模块设计源代码：library ieee;use ieee.std_logic_1164.all;entity latch1b isport(d: in std_logic;ena: in std_logic; --使能端q: out std_logic);end latch1b;architecture art of latch1b isbeginprocess(d,ena)beginif ena='1' thenq<=d;end if;end process;end art;元件声明程序包设计源代码：library ieee;use ieee.std_logic_1164.all;package my_package iscomponent latch1port(d:in std_logic;ena:in std_logic;q: out std_logic);end component;end;顶层模块设计源代码：library ieee;use ieee.std_logic_1164.all;use work.my_package.all; --使用用户自定义的程序包entity latch4d isport(d: in std_logic_vector(3 downto 0);oen: in bit;q:out std_logic_vector(3 downto 0));end latch4d;architecture one of latch4d issignal sig_save:std_logic_vector(3 downto 0);begingetlatch:for n in 0 to 3 generate --用for_generate语句循环例化4个1位锁存器latchx:latch1 port map(d(n),g,sig_save(n)); --关联end generate;q<=sig_save when oen='0'else"ZZZZ";end one;6.6 32进制多样型计数器设计（1）32进制同步加法计数器源程序library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity counter_plus isport(clk,clr:in std_logic;dout0,dout1: out std_logic_vector(3 downto 0));end;architecture art of counter_plus issignal d0,d1:std_logic_vector(3 downto 0); --d0代表个位，d1代表十位beginprocess(clk,clr,)beginif clr='1'thend1<=(others=>'0');d0<="0000"; --同步清零elsif clk'event and clk='1' thenif(d1=3 and d0=1)thend1<="0000";d0<="0000"; --计数到32时清零elsif(d0=1) thend0<="0000";d1<=d1+1;elsed0<=d0+1;end if;end if;dout1<=d1;dout0<=d0;end process;end art;（2）32进制同步减法计数器源程序32进制同步减法计数器源程序如下：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity counter_sub isport(clk,clr:in std_logic;dout0,dout1: out std_logic_vector(3 downto 0));end;architecture art of counter_sub issignal d0,d1:std_logic_vector(3 downto 0); --d0代表个位，d1代表十位beginprocess(clk,clr)beginif clr='1' thend1<="0000";d0<="0000"; --异步清零elsif clk'event and clk='1' thenif(d1=0 and d0=0) thend1<="0011";d0<="0001"; --设定容量31elsif(d0=0) thend0<="0001";d1<=d1-1;elsed0<=d0-1;d1<=d1;end if;end if;dout1<=d1;dout0<=d0;end process;end art;32进制同步可逆计数器源程序如下：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity counter_reversible isport(clk,clr,s:in std_logic; --s=1加法计数，s=0减法计数dout0,dout1: out std_logic_vector(3 downto 0));end;architecture art of counter_reversible issignal d0,d1:std_logic_vector(3 downto 0); --d0代表个位，d1代表十位beginprocess(clk,clr,s)beginif clr='1'thend1<="0000";d0<="0000"; --异步清零elsif (clk'event and clk='1' )thenif s='1' thenif(d1=3 and d0=1) thend1<="0000";d0<="0000"; --计数到31时清零elsif(d0=1) thend0<="0000";d1<=d1+1;else d0<=d0+1;end if;elsif s='0' thenif(d1=0 and d0=0)thend1<="0011";d0<="0001"; --设定容量31elsif(d0=0) thend0<="0001";d1<=d1-1;elsed0<=d0-1;d1<=d1;end if;end if;end if;dout1<=d1;dout0<=d0;end process;end art;（4）32进制异步加法计数器源程序32进制异步加法计数器源程序如下：①子模块D触发器源程序设计。

EDA程序编程

1、用AHDL语言编写图中的组合逻辑电路。

. 参考答案：SUBDESIGN decode1(a0,a1,b:input;out1,out2:output;)beginout1=a0&!a1out2=out1&b;end;2、门电路构成的半加器结构如下图半加器h_adder表示如下：图中SO为相加和的输出，CO为进位输出信号。

用VHDL语言对半加器进行描述。

参考答案：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL；ENTITY half adder ISPORT(a,b: IN STD_LOGIC;So,co：OUT STD_LOGIC);END half_adder；ARCHITECYURE hahav1 OF half_adder ISSIGNAL c,d：STD_LOGICBEGINc＜＝a OR b：d＜＝a NAND b；co＜＝NOT d AFTER 5ns；so＜＝c AND d AFTER 5ns;END behav1;3、本题为一个4位加法器的VHDL语言描述，4位加法器其输入为a0、a1、a2、a3、b0、b1、b2、b3、进位输入为cin；输出为s0、s1、s2、s3，进位输出为cout。

请完善本程序。

文件名为adder_4bits.vhdLIBRARY IEEE;USE IEEE.STD.LOGIC_1164.ALL;ENTITY adder_4bits ISPORT ( a0,a1,a2,a3 :IN STD_LOGIC;b0,b1,b2,b3,cin :IN STD_LOGIC;s0,s1,s2,s3 :OUT STD_LOGIC);END adder_4bits ;ARCHITECTURE strc OF adder_4bits ISCOMPONENT full_adderPORT(a,b,cin:IN std_LOGIC;S,co:OUT std_logic);END COMPONENT;SIGNAL U0_c,U1_c,U2_c:STD_LOGIC;１BEGINU0:full_adder PORT MAP (a0,b0,cin,s0,U0_c);U1:full_adder PORT MAP (a1,b1,U0_c,s1,U1_c);U2:full_adder PORT MAP (a2,b2,U1_c,s2,U2_c);U3:full_adder PORT MAP (a3,b3,U2_c,s3,cout);End strc;4、用VHDL语言描述不带复位/置位端的D触发器。

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