vhdl各种实验程序代码
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1.三与门
library ieee;
use ieee.std_logic_1164.all;
entity yumen is
port(a,b,c : in std_logic;
f : out std_logic);
end yumen;
architecture and3_1 of yumen is
begin
f<=a and b and c;
end architecture and3_1;
2.三八译码器
library ieee;
use ieee.std_logic_1164.all;
entity jg is
port(a,b,c,g1,g2a,g2b:in std_logic;
y:out std_logic_vector(7 downto 0));
end entity jg;
architecture rt1 of jg is
signal indata:std_logic_vector(2 downto 0); begin
indata<=c&b&a;
process(indata,g1,g2a,g2b)is
begin
if(g1='1' and g2a='0' and g2b='0')then case indata is
when"000"=>y<="11111110"; when"001"=>y<="11111101"; when"010"=>y<="11111011"; when"011"=>y<="11110111"; when"100"=>y<="11101111"; when"101"=>y<="11011111"; when"110"=>y<="10111111"; when"111"=>y<="01111111";
when others=>y<="xxxxxxxx";
end case;
else
y<="11111111";
end if;
end process;
end rt1; 3.同步复位/置位、下降沿触发的d触发器ibrary ieee;
use ieee.std_logic_1164.all;
entity adff is
port(clk,d,r,s:in std_logic;
q:out std_logic);
end adff;
architecture rtl of adff is
signal q_temp,qb_temp:std_logic;
begin
process(clk,r,s)
begin
if(clk'event and clk='0')then
if(r='0' and s='1')then
q_temp<='1';
if(r='1' and s='0')then
q_temp<='0';
else
q_temp<=d;
end if;
end if;
end if;
end process;
q<=q_temp;
end rtl;
4.异步复位/置位、上升沿触发的d发器ibrary ieee;
use ieee.std_logic_1164.all;
entity adff is
port(clk,d,r,s:in std_logic;
q:out std_logic);
end adff;
architecture rtl of adff is
signal q_temp,qb_temp:std_logic;
begin
process(clk,r,s)
begin
if(r='0' and s='1')then
q_temp<='1';
elsif(r='1' and s='0')then
q_temp<='0';
elsif(clk'event and clk='1')then
q_temp<=d;
end if;
end process;
q<=q_temp;
end rtl;
5.四分频器
ibrary ieee;
use ieee.std_logic_1164.all;
entity one is
port( clk1:in std_logic;
clk4:out std_logic);
end one;
architecture one1 of one is
signal data1:integer range 0 to 10;
signal q1:std_logic;
begin
process(clk1)
begin
if rising_edge(clk1) then
if(data1=1) then
data1<=0;
q1<=not q1;
else
data1<=data1+1;
end if;
end if;
clk4<=q1;
end process;
end architecture one1;
6.四选一library ieee;
use ieee.std_logic_1164.all;
entity mux4 is
port(input:in std_logic_vector(3 downto 0); a,b:in std_logic;
y : out std_logic);
end mux4 ;
architecture rtl of mux4 is
signal sel:std_logic_vector(1 downto 0); begin
sel<=b & a;
process (input,sel)
begin
if (sel="00") then
y <= input(0);
elsif (sel="01") then
y <= input(1);
elsif (sel="10") then
y <= input(2);
else
y <= input(3);
end if;
end process;
end rtl; 7.五分频器
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity fenpin5 is
port (rst,clkin :in std_logic;
clkout:out std_logic);
end fenpin5;
architecture rtl of fenpin5 is
signal count1,count2: std_logic_vector(7 downto 0);
signal tmp,tmp1,tmp2: std_logic;
begin
tmp<=tmp1 and tmp2;
clkout<=tmp xor tmp1;
process(clkin,rst)
begin
if rst ='1'then
count1 <= "00000000";
tmp1<= '0';
elsif clkin'event and clkin='1' then
if count1 = "00000100" then
count1 <= "00000000";
else
count1 <= count1 + 1;
if count1 < "00000010" then
tmp1<= '0';
else
tmp1<= '1';
end if;
end if;
end if;
end process;
end rtl;