UPSD3213B-24T1T中文资料
不间断电源系统-UPS
2． 安装说明..................................................................................7-14 2.1 拆包、检验.....................................................................................7 2.2 输入、输出电源线及保护接地安装.................................................7 2.3 安装...........................................................................................7-9 2.4 长效型外接电池操作程序.........................................................9-10 2.5 并机操作................................................................................10-14
UPSD3233AV-40T1中文资料
1/8DATA BRIEFINGJune 2002Complete data available on Data-on-Disc CD-ROM or at .µPSD3200FAMILYFlash Programmable System Devicewith 8032Microcontroller CoreFEATURES SUMMARYs The µPSD3200Family combines a Flash PSD architecture with an 8032microcontroller core The µPSD3200Family of Flash PSDs features dual banks of Flash memory,SRAM,general purpose I/O and programmable logic,supervi-sory functions and access via USB,I 2C,ADC,DDC and PWM channels,and an on-board 8032microcontroller core,with two UARTs,three 16-bit Timer/Counters and one External Interrupt.As with other Flash PSD families,the µPSD3200Family is also in-system program-mable (ISP)via a JTAG ISP interface.sLarge 8KByte SRAM with battery back-up optionsDual bank Flash memories–128KByte or 256KByte main Flash memory –32KByte secondary Flash memorysContent Security–Block access to Flash memorysProgrammable Decode PLD for flexible address mapping of all memories.s High-speed clock standard 8032core (12-cycle)s USB Interface (µPSD3234A-40U6only)s I 2C interface for peripheral connections s Five Pulse Width Modulator (PWM)channels s Standalone Display Data Channel (DDC)s Six I/O ports with up to 50I/O pins s 3000gate PLD with 16macrocells s Supervisor functionss In-System Programming (ISP)via JTAG s Zero-Power Technology sSingle Supply Voltage –4.5to 5.5V –3.0to 3.6VFigure 1.PackagesTQFP52(T)TQFP80(U)µPSD3200FAMILY2/8SUMMARY DESCRIPTION s Dual bank Flash memories–Concurrent operation,read from memory one while erasing and writing the other.In-Appli-cation Programming (IAP)for remote updates –Large 128KByte or 256KByte main Flash memory for application code,operating sys-tems,or bit maps for graphic user interfaces –Large 32KByte secondary Flash memory di-vided in small sectors.Eliminate external EE-PROM with software EEPROM emulation –Secondary Flash memory is large enough for sophisticated communication protocol (USB)during IAP while continuing critical system taskssLarge SRAM with battery back-up option –8KByte SRAM for RTOS,high-level languag-es,communication buffers,and stackssProgrammable Decode PLD for flexible address mapping of all memories–Place individual Flash and SRAM sectors on any address boundary –Built-in page register breaks restrictive 8032limit of 64KByte address space –Special register swaps Flash memory seg-ments between 8032“program”space and “data”space for efficient In-Application Pro-grammingsHigh-speed clock standard 8032core (12-cycle)–40MHz operation at 5V,24MHz at 3.3V –Two UARTs with independent baud rate,three 16-bit Timer/Counters and two External InterruptssUSB Interface (µPSD3234A-40U6only)–Supports USB 1.1Slow Mode (1.5Mbit/s)–Control endpoint 0and interrupt endpoints 1and 2sI 2C interface for peripheral connections –Capable of master or slave operation sFive Pulse Width Modulator (PWM)channels –Four 8-bit PWM units–One 16-bit PWM unitsStandalone Display Data Channel (DDC)–For use in monitor,projector,and TV applica-tions –Compliant with VESA standards DDC1and DDC2B –Eliminate external DDC PROM s Six I/O ports with up to 50I/O pins–Multifunction I/O:GPIO,DDC,I 2C,PWM,PLD I/O,supervisor,and JTAG –Eliminates need for external latches and logics3000gate PLD with 16macrocells–Create glue logic,state machines,delays,etc.–Eliminate external PALs,PLDs,and 74HCxx –Simple PSDsoft Express software ...FreesSupervisor functions–Generates reset upon low voltage or watch-dog time-out.Eliminate external supervisor device –Reset In pinsIn-System Programming (ISP)via JTAG –Program entire chip in 10-25seconds with no involvement of 8032–Allows efficient manufacturing,easy product testing,and Just-In-Time inventory –Eliminate sockets and pre-programmed parts –Program with FlashLINK TM cable and any PCsContent Security–Programmable Security Bit blocks access of device programmers and readerssZero-Power Technology–Memories and PLD automatically reach standby current between input changessPackages –52-pin TQFP–80-pin TQFP:allows access to 8032address/data/control signals for connecting to external peripherals3/8µPSD3200FAMILYFigure 2.µPSD3200Family Functional ModulesAI066194Channel ADC1Mb or 2Mb Main FlashDecode PLD64Kb SRAMCPLD -16MACROCELLSJTAG ISP Port 1Port 32UARTS Interrupt3Timer /Counters256Byte SRAM8051Core Port 3,UART,Intr,Timers,I2CPSD Internal Bus8032Internal BusUSB &TransceiverPort 1,Timers and 2nd UART and ADCDDC w/256Byte SRAM PWM 5Channels Port 4PWM and DDCDedicated USB PinsPort A &B,PLD I/O and GPIOPort D GPIO Port C,JTAG,PLD I/O and GPIOVCC,GND,XTAL256Kb Secondary FlashDedicated PinsI2CPort 0,2Ext.BusReset LogicLVD &WDTBus InterfaceResetD0-D7A0-A15RD,PSEN WR,ALEPage Register PSD MODULEMCU MODULEµPSD3200FAMILY4/8Table 1.80-Pin Package Pin DescriptionNote:PSD Port A and MCU Address/Data bus are added for 80-pin deviceSignal Name In/Out FunctionBasicAlternateAD7-AD0I/O Multiplexed Address/Data bus A11-A8I/O External Address BusRxD2-RxD1I/O General I/O port pinsUART Receive TxD2-TxD1I/O UART TransmitINT1-INT0I/O Interrupt inputs /timer gate controls T2-T0I/O Counter inputsSDA1-SDA2I/OI 2C Bus serial data I/O /DDC interface SCL1-SCL2I/O I 2C Bus clock I/OVSYNC I/O VSYNC input for DDC interface T2EX I/O Timer 2Trigger input ADC3-ADC0I/O ADC Channels inputPWM4-PWM0I/O 8-bit Pulse Width Modulation outputsUSB-,USB+I/O USB I/OAVREF O Reference Voltage input for ADC RD_O Read signal,external bus WR_O Write signal,external bus PSEN_O PSEN signal,external bus ALE O Address Latch signal,external bus RESET_I Active low reset inputXTAL1I Oscillator input pin for system clock XTAL2OOscillator output pin for system clockPA7-P A0I/O General I/O port pins1.PLD Macro-cell outputs2.PLD inputstched Address Out (A0-A7)4.Peripheral I/O mode PB7-PB0I/O General I/O port pins1.PLD Macro-cell outputs2.PLD inputstched Address Out (A0-A7)PC7-PC0I/O General I/O port pins1.PLD Macro-cell outputs2.PLD inputs3.SRAM stand by voltage input (VSTBY)4.JTAG Interface (TDI,TDO,TMS,TCK,TSTA T,TERR)5.SRAM battery-on indicator (PC4)PD2-PD1I/O General I/O port pin1.PLD I/O2.Clock input to PLD and APD3.Chip select to PSD ModuleµPSD3200FAMILY Figure3.TQFP52ConnectionsNote:NC=Not ConnectedPU=Pull-up resistor required(2kΩfor3V devices,7.5kΩfor5V devices)39P1.5/ADC1 38P1.4/ADC0 37P1.3/TXD1 36P1.2/RXD1 35P1.1/T2X 34P1.0/T233V CC32XTAL231XTAL130P3.7/SCL1 29P3.6/SDA1 28P3.5/T127P3.4/T0PD1 PC7 PC6 PC5 PU PC4 NC V CC GND PC3 PC2 PC1 PC0 12345678910111213525154948474645444342414PBPB1PB2PB3PB4PB5VREFGNDRST-INPB6PB7ADC3ADC21415161718192212223242526P4.7/PWM4P4.6/PWM3P4.5/PWM2P4.4/PWM1P4.3/PWMGNDP4.2/DDCVSYNCP4.1/DDCSCLP4./DDCSDAP3./RXDP3.1/TXDP3.2/EXINTP3.3/EXINT1AI05790B5/8µPSD3200FAMILY6/8Figure 4.TQFP80ConnectionsNote: 1.NC =Not ConnectedB-needs a pull-up resistor (see the description of the USB function)60P1.5/ADC1 59P1.4/ADC0 58P1.3/TXD1 57P2.3,A11 56P1.2/RXD1 55P2.2,A10 54P1.1/T2X 53P2.1,A9 52P1.0/T2 51P2.0,A8 50V CC 49XTAL2 48XTAL1 47P0.7,AD7 46P3.7/SCL1 45P0.6,AD6 44P3.6/SDA1 43P0.5,AD5 42P3.5/T1 41P0.4,AD4PD2 P3.3/EXINT1 PD1 PD0,ALE PC7 PC6 PC5 USB- PC4 USB+ NC V CC GND PC3 PC2 PC1 NC P4.7/PWM4 P4.6/PWM3 PC0123 45 6 7 8 9 10 11 12 13 14 15 16 1718 192080 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61P B 0P 3.2/E X I N T 0P B 1P 3.1/T X DP B 2P 3.0/R X DP B 3P B 4P B 5N CV R E FG N DR E S E T -I NP B 6P B 7R D ,C N T L 1P 1.7/A D C 3P S E N ,C N T L 2W R ,C N T L 0P 1.6/A D C 22122232425262728293031323334353637383940P A 7 P A 6 P 4.5/P W M 2 P A 5 P 4.4/P W M 1 P A 4 P 4.3/P W M 0 P A 3 G N D P 4.2/D C C V S Y N C P 4.1/D D C S C L P A 2 P 4.0/D D C S D A P A 1 P A 0 A D 0,P 0.0 A D 1,P 0.1 A D 2,P 0.2 A D 3,P 0.3 P 3.4/T 0AI05791µPSD3200FAMILY PART NUMBERINGTable2.Ordering Information SchemeFor a list of available options(speed,package, etc.)or for further information on any aspect of this device,please contact your nearest ST Sales Of-fice.Example:uPSD3234B V–24U6TDevice TypeuPSD=Microcontroller PSDFamily3=8032corePLD Size2=16Macrocells3=32MacrocellsSRAM Size1=16Kbit3=64Kbit5=256KbitMain Flash Memory Size3=1Mbit4=2Mbit5=4MbitIP MixA=USB,I2C,PWM,DDC,ADC,(2)UARTsSupervisor(Reset Out,Reset In,LVD,WD)B=I2C,PWM,DDC,ADC,(2)UARTsSupervisor(Reset Out,Reset In,LVD,WD)Operating Voltageblank=V CC=4.5to5.5VV=V CC=3.0to3.6VSpeed24=24MHz40=40MHzPackageT=52-pin TQFPU=80-pin TQFPTemperature Range1=0to70°C(commercial)6=–40to85°C(industrial)OptionT=Tape&Reel Packing7/8µPSD3200FAMILYInformation furnished is believed to be accurate and reliable.However,STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use.No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics.Specifications mentioned in this publication are subject to change without notice.This publication supersedes and replaces all information previously supplied.STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.The ST logo is registered trademark of STMicroelectronicsAll other names are the property of their respective owners©2002STMicroelectronics-All Rights ReservedSTMicroelectronics group of companiesAustralia-Brazil-Canada-China-Finland-France-Germany-Hong Kong-India-Israel-Italy-Japan-Malaysia-Malta-Morocco-Singapore-Spain-Sweden-Switzerland-United Kingdom-United States.8/8。
Ups 技术参数要求
UPS 技术参数要求
主要性能
工频机、整机质保三年。
应用尖端技术
DDC（Direct Digital Control）直接数字控制/DSP（Digital Signal Processor）数字信号处理/ASIC（Application Specified IC）专用IC/CPU（微处理器）。
完全满足从0到100%负载跃变
在某些情况下，UPS必须能够提供瞬间满负载的要求，
而无需切换到旁路，并保持输出稳定可靠。
大屏幕触目屏、全中文显示监控操作方便
运行状态、操作程序、测量值、故障检修资料、图像资料显示等，通过菜
单操作，操作更加方便。
保护功能齐全
设有多种系统保护功能，对超压、低压、过流、过载、短路、波型失真等有保护报警功能，因此机器故障率很低。
采用瞬时波形控制方式，实现输出电压失真小
电流局部循环控制，使逆变器完全适应负载启动时的冲击电流，以及电涌时的过电流等进行高速控制；使UPS对负载变动进行快速响应。
通信方便
RS232通讯端真正实现多用途通和远程监视,可对负载和UPS主机进行英特网操作。
具备集中监控管理功能能。
并机
具备多机并机功能。
智能电池管理功能
UPS可通过内部软件设定电池的充电电流。
每三个月自动进行半小时均充操作。
UPS对电池实现自动维护，无需人工操作。
从而延长电池使用寿命。
开关机自动管理功能
可以在电脑上任意设置自动关机时间，无须人工操作。
可以在UPS主机上安装网络适配器，无论在什么地方都可以监控到UPS的运行和自动开关机。
技术参数。
UPS说明书
PMU不间断电源(UPS)使用说明书河南铭诺电气设备有限公司一、简介1.1前言PMU--系列工频在线式UPS电源是为了保障计算机服务器、网络电子设备、精密电子仪器、自动化电气设备等系列电子、电气设备高效安全运行而精心设计的高可靠性的不间断电源设备。
PMU—系列UPS电源产品能安全排除市电(AC)电网如：市电中断（Power Fil）、暂态过电压（Switching Transients）、电压下降（Power Sags）、电涌（Power Surges）、高压脉冲（High V oltage Spakes）、电线噪声（Electrical Line Noise）、频率偏移（Frepuency Variatuon）、持续低电压（Brownout）等故障，并能为电子、电气设备提供纯正弦波的电源，保障电子、电气设备高效、安全运行。
该系列UPS电源采用了国际先进SPWM脉宽调制技术，并用了高性能IGBT及SCR的完美结合技术，精心高标准设计、高标准制造而成。
该系列UPS电源稳定、可靠的完美品质赢得了广大国内外客户的青睐，从而成为选用率最高的在线式UPS不间断电源。
1.2注意事项本说明书能让您很容易地操作及维护本系统。
为使本系统能充分发挥其功能，请注意以下事项：1.在使用前务必详阅此说明书。
2.遵照指示步骤，依法操作。
3.机器搬运时应小心轻放。
4.请依照说明书上相关条款进行安装、使用和维护。
5.系统内部有危险电压，请勿打开机盖，避免造成人员触电伤害或系统损坏。
6.避免超负载使用，以免造成市电断电后UPS出现掉电现象。
7.请妥善保存该说明书，以供日后参考用。
8.机器若有异常现象，请依据「异常处理程序」处理。
9.请保持UPS表面清洁、干净。
二、安全1.为了降低设备负载接地不良而引起的电击危险，在连接RS232 SNMP接口时，应将市电输入电源、旁路输入电源断开，只有在连接了全部信号接头后才能闭合市电输入电源和旁路输入电源。
UPS说明书
U P S 不断电电源供给器智能在线网络保护不断电系统3KVA/6KVA/10KVA/12KVA/15KVA/20KVA/30KVA■产品使用手册■1. 导论------------------------------------------------------------------------------------------------22. 重要安全指示-----------------------------------------------------------------------------------23. UPS介绍------------------------------------------------------------------------------------------34. 产品介绍------------------------------------------------------------------------------------------55. 安装------------------------------------------------------------------------------------------------66. 操作说明-----------------------------------------------------------------------------------------87. 监控软件选配及计算机接口端口--------------------------------------------------------98. 保养及保存方法------------------------------------------------------------------------------109. 异常状况排除---------------------------------------------------------------------------------1110. 附录A 规格---------------------------------------------------------------------------------15在线式不断电系统电源供应器(UPS)提供一个连续且稳定的电源给需要保护的设备使用，使您的设备免于遭受下列电源的困扰。
UPSD3234B-24T1中文资料
– Eliminate external PALs, PLDs, and 74HCxx – Simple PSDsoft Express software ...Free s Supervisor functions – Generates reset upon low voltage or watch-
s High-speed clock standard 8032 core (12-cycle)
– 40 MHz operation at 5 V, 24 MHz at 3.3 V
– Two UARTs with independent baud rate, three 16-bit Timer/Counters and two External Interrupts
– Multifunction I/O: GPIO, DDC, I2C, PWM, PLD I/O, supervisor, and JTAG
– Eliminates need for external latches and logic s 3000 gate PLD with 16 macrocells
s High-speed clock standard 8032 core (12-cycle)
s USB Interface (µPSD3234A-40U6 only) s I2C interface for peripheral connections
s Five Pulse Width Modulator (PWM) channels
– Large 128 KByte or 256 KByte main Flash memory for application code, operating systems, or bit maps for graphic user interfaces
MDT系列3B UPS中文说明书
为了保持安装环境的温度如上所述，请装设适当的排热系统（请参照“规格”章节确 认 kcal/KW/B.T.U 参考值）。您可以参考下列的做法：
136A
40
175A/500V～
80A/380V～ 2*100A/415V～ 2*100A/415V～ 2*100A/415V～ 100A/500V～ 175A/500V～ 182A 182A
182A
市电/负载/电池、配接
Hale Waihona Puke 10KVA15、20KVA
7
30KVA
40KVA
配线线径请参阅下表
机种 KVA
FSCR max min Normial
10
56A/500V～
40A/380V～
63A/415V～
63A/415V～
80A/415V～ 56A/500V～ 56A/500V～
50A
50A
45A
15
100A/500V～
63A/380V～
100A/415V～ 100A/415V～ 100A/415V～ 56A/500V～ 100A/500V～ 70A
6
设置输出入配线
保护
UPS 内部
输出入的保护开关与保险丝如表 A 所列（请查询方块图）。更换保险丝时请依照零件
表所示的规格与型号。
表A
内部保护装置
UPS 型式 KVA
整流器、 输出保险丝
开关
电池 保险丝
旁路
最大 输入
输出
UPS说明书技术参数
不间断电源u n i n t e r r u p t i b l e p o w e rs u p p l yU P S(6···250)K V A产品使用说明书目录1．产品介绍---------------------------------------------2 2．操作要求---------------------------------------------2 3．注意事项---------------------------------------------2 4．工作原理---------------------------------------------3 5．前板介绍---------------------------------------------7 6．安装---------------------------------------------------87. 主要技术指标---------------------------------------118. 告警说明---------------------------------------------159. UPS启动程序-------------------------------------17 10．UPS维修关机程序------------------------------17 11. 紧急关机程序--------------------------------------17 12．前显示板说明-------------------------------------18 13．并机系统启动操作步骤-------------------------21 14．并机系统关机步骤---------- --------------------2215. 并机系统紧急关机步骤--------------------------2216. 附页—开机注意事项----------------------------- 241．产品介绍三三系列三进三出全数字化UPS，是采用先进的微电子、电力电子、数字控制技术，集数字化、信息化、网络化为一体的高智能型产品，具有强大的信息采集系统、信号处理系统、监测系统和完善的保护系统。
UPSD3313B-24T1中文资料
1/8DATA BRIEFINGJune 2002Complete data available on Data-on-Disc CD-ROM or at .µPSD3200FAMILYFlash Programmable System Devicewith 8032Microcontroller CoreFEATURES SUMMARYs The µPSD3200Family combines a Flash PSD architecture with an 8032microcontroller core The µPSD3200Family of Flash PSDs features dual banks of Flash memory,SRAM,general purpose I/O and programmable logic,supervi-sory functions and access via USB,I 2C,ADC,DDC and PWM channels,and an on-board 8032microcontroller core,with two UARTs,three 16-bit Timer/Counters and one External Interrupt.As with other Flash PSD families,the µPSD3200Family is also in-system program-mable (ISP)via a JTAG ISP interface.sLarge 8KByte SRAM with battery back-up optionsDual bank Flash memories–128KByte or 256KByte main Flash memory –32KByte secondary Flash memorysContent Security–Block access to Flash memorysProgrammable Decode PLD for flexible address mapping of all memories.s High-speed clock standard 8032core (12-cycle)s USB Interface (µPSD3234A-40U6only)s I 2C interface for peripheral connections s Five Pulse Width Modulator (PWM)channels s Standalone Display Data Channel (DDC)s Six I/O ports with up to 50I/O pins s 3000gate PLD with 16macrocells s Supervisor functionss In-System Programming (ISP)via JTAG s Zero-Power Technology sSingle Supply Voltage –4.5to 5.5V –3.0to 3.6VFigure 1.PackagesTQFP52(T)TQFP80(U)µPSD3200FAMILY2/8SUMMARY DESCRIPTION s Dual bank Flash memories–Concurrent operation,read from memory one while erasing and writing the other.In-Appli-cation Programming (IAP)for remote updates –Large 128KByte or 256KByte main Flash memory for application code,operating sys-tems,or bit maps for graphic user interfaces –Large 32KByte secondary Flash memory di-vided in small sectors.Eliminate external EE-PROM with software EEPROM emulation –Secondary Flash memory is large enough for sophisticated communication protocol (USB)during IAP while continuing critical system taskssLarge SRAM with battery back-up option –8KByte SRAM for RTOS,high-level languag-es,communication buffers,and stackssProgrammable Decode PLD for flexible address mapping of all memories–Place individual Flash and SRAM sectors on any address boundary –Built-in page register breaks restrictive 8032limit of 64KByte address space –Special register swaps Flash memory seg-ments between 8032“program”space and “data”space for efficient In-Application Pro-grammingsHigh-speed clock standard 8032core (12-cycle)–40MHz operation at 5V,24MHz at 3.3V –Two UARTs with independent baud rate,three 16-bit Timer/Counters and two External InterruptssUSB Interface (µPSD3234A-40U6only)–Supports USB 1.1Slow Mode (1.5Mbit/s)–Control endpoint 0and interrupt endpoints 1and 2sI 2C interface for peripheral connections –Capable of master or slave operation sFive Pulse Width Modulator (PWM)channels –Four 8-bit PWM units–One 16-bit PWM unitsStandalone Display Data Channel (DDC)–For use in monitor,projector,and TV applica-tions –Compliant with VESA standards DDC1and DDC2B –Eliminate external DDC PROM s Six I/O ports with up to 50I/O pins–Multifunction I/O:GPIO,DDC,I 2C,PWM,PLD I/O,supervisor,and JTAG –Eliminates need for external latches and logics3000gate PLD with 16macrocells–Create glue logic,state machines,delays,etc.–Eliminate external PALs,PLDs,and 74HCxx –Simple PSDsoft Express software ...FreesSupervisor functions–Generates reset upon low voltage or watch-dog time-out.Eliminate external supervisor device –Reset In pinsIn-System Programming (ISP)via JTAG –Program entire chip in 10-25seconds with no involvement of 8032–Allows efficient manufacturing,easy product testing,and Just-In-Time inventory –Eliminate sockets and pre-programmed parts –Program with FlashLINK TM cable and any PCsContent Security–Programmable Security Bit blocks access of device programmers and readerssZero-Power Technology–Memories and PLD automatically reach standby current between input changessPackages –52-pin TQFP–80-pin TQFP:allows access to 8032address/data/control signals for connecting to external peripherals3/8µPSD3200FAMILYFigure 2.µPSD3200Family Functional ModulesAI066194Channel ADC1Mb or 2Mb Main FlashDecode PLD64Kb SRAMCPLD -16MACROCELLSJTAG ISP Port 1Port 32UARTS Interrupt3Timer /Counters256Byte SRAM8051Core Port 3,UART,Intr,Timers,I2CPSD Internal Bus8032Internal BusUSB &TransceiverPort 1,Timers and 2nd UART and ADCDDC w/256Byte SRAM PWM 5Channels Port 4PWM and DDCDedicated USB PinsPort A &B,PLD I/O and GPIOPort D GPIO Port C,JTAG,PLD I/O and GPIOVCC,GND,XTAL256Kb Secondary FlashDedicated PinsI2CPort 0,2Ext.BusReset LogicLVD &WDTBus InterfaceResetD0-D7A0-A15RD,PSEN WR,ALEPage Register PSD MODULEMCU MODULEµPSD3200FAMILY4/8Table 1.80-Pin Package Pin DescriptionNote:PSD Port A and MCU Address/Data bus are added for 80-pin deviceSignal Name In/Out FunctionBasicAlternateAD7-AD0I/O Multiplexed Address/Data bus A11-A8I/O External Address BusRxD2-RxD1I/O General I/O port pinsUART Receive TxD2-TxD1I/O UART TransmitINT1-INT0I/O Interrupt inputs /timer gate controls T2-T0I/O Counter inputsSDA1-SDA2I/OI 2C Bus serial data I/O /DDC interface SCL1-SCL2I/O I 2C Bus clock I/OVSYNC I/O VSYNC input for DDC interface T2EX I/O Timer 2Trigger input ADC3-ADC0I/O ADC Channels inputPWM4-PWM0I/O 8-bit Pulse Width Modulation outputsUSB-,USB+I/O USB I/OAVREF O Reference Voltage input for ADC RD_O Read signal,external bus WR_O Write signal,external bus PSEN_O PSEN signal,external bus ALE O Address Latch signal,external bus RESET_I Active low reset inputXTAL1I Oscillator input pin for system clock XTAL2OOscillator output pin for system clockPA7-P A0I/O General I/O port pins1.PLD Macro-cell outputs2.PLD inputstched Address Out (A0-A7)4.Peripheral I/O mode PB7-PB0I/O General I/O port pins1.PLD Macro-cell outputs2.PLD inputstched Address Out (A0-A7)PC7-PC0I/O General I/O port pins1.PLD Macro-cell outputs2.PLD inputs3.SRAM stand by voltage input (VSTBY)4.JTAG Interface (TDI,TDO,TMS,TCK,TSTA T,TERR)5.SRAM battery-on indicator (PC4)PD2-PD1I/O General I/O port pin1.PLD I/O2.Clock input to PLD and APD3.Chip select to PSD ModuleµPSD3200FAMILY Figure3.TQFP52ConnectionsNote:NC=Not ConnectedPU=Pull-up resistor required(2kΩfor3V devices,7.5kΩfor5V devices)39P1.5/ADC1 38P1.4/ADC0 37P1.3/TXD1 36P1.2/RXD1 35P1.1/T2X 34P1.0/T233V CC32XTAL231XTAL130P3.7/SCL1 29P3.6/SDA1 28P3.5/T127P3.4/T0PD1 PC7 PC6 PC5 PU PC4 NC V CC GND PC3 PC2 PC1 PC0 12345678910111213525154948474645444342414PBPB1PB2PB3PB4PB5VREFGNDRST-INPB6PB7ADC3ADC21415161718192212223242526P4.7/PWM4P4.6/PWM3P4.5/PWM2P4.4/PWM1P4.3/PWMGNDP4.2/DDCVSYNCP4.1/DDCSCLP4./DDCSDAP3./RXDP3.1/TXDP3.2/EXINTP3.3/EXINT1AI05790B5/8µPSD3200FAMILY6/8Figure 4.TQFP80ConnectionsNote: 1.NC =Not ConnectedB-needs a pull-up resistor (see the description of the USB function)60P1.5/ADC1 59P1.4/ADC0 58P1.3/TXD1 57P2.3,A11 56P1.2/RXD1 55P2.2,A10 54P1.1/T2X 53P2.1,A9 52P1.0/T2 51P2.0,A8 50V CC 49XTAL2 48XTAL1 47P0.7,AD7 46P3.7/SCL1 45P0.6,AD6 44P3.6/SDA1 43P0.5,AD5 42P3.5/T1 41P0.4,AD4PD2 P3.3/EXINT1 PD1 PD0,ALE PC7 PC6 PC5 USB- PC4 USB+ NC V CC GND PC3 PC2 PC1 NC P4.7/PWM4 P4.6/PWM3 PC0123 45 6 7 8 9 10 11 12 13 14 15 16 1718 192080 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61P B 0P 3.2/E X I N T 0P B 1P 3.1/T X DP B 2P 3.0/R X DP B 3P B 4P B 5N CV R E FG N DR E S E T -I NP B 6P B 7R D ,C N T L 1P 1.7/A D C 3P S E N ,C N T L 2W R ,C N T L 0P 1.6/A D C 22122232425262728293031323334353637383940P A 7 P A 6 P 4.5/P W M 2 P A 5 P 4.4/P W M 1 P A 4 P 4.3/P W M 0 P A 3 G N D P 4.2/D C C V S Y N C P 4.1/D D C S C L P A 2 P 4.0/D D C S D A P A 1 P A 0 A D 0,P 0.0 A D 1,P 0.1 A D 2,P 0.2 A D 3,P 0.3 P 3.4/T 0AI05791µPSD3200FAMILY PART NUMBERINGTable2.Ordering Information SchemeFor a list of available options(speed,package, etc.)or for further information on any aspect of this device,please contact your nearest ST Sales Of-fice.Example:uPSD3234B V–24U6TDevice TypeuPSD=Microcontroller PSDFamily3=8032corePLD Size2=16Macrocells3=32MacrocellsSRAM Size1=16Kbit3=64Kbit5=256KbitMain Flash Memory Size3=1Mbit4=2Mbit5=4MbitIP MixA=USB,I2C,PWM,DDC,ADC,(2)UARTsSupervisor(Reset Out,Reset In,LVD,WD)B=I2C,PWM,DDC,ADC,(2)UARTsSupervisor(Reset Out,Reset In,LVD,WD)Operating Voltageblank=V CC=4.5to5.5VV=V CC=3.0to3.6VSpeed24=24MHz40=40MHzPackageT=52-pin TQFPU=80-pin TQFPTemperature Range1=0to70°C(commercial)6=–40to85°C(industrial)OptionT=Tape&Reel Packing7/8µPSD3200FAMILYInformation furnished is believed to be accurate and reliable.However,STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use.No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics.Specifications mentioned in this publication are subject to change without notice.This publication supersedes and replaces all information previously supplied.STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.The ST logo is registered trademark of STMicroelectronicsAll other names are the property of their respective owners©2002STMicroelectronics-All Rights ReservedSTMicroelectronics group of companiesAustralia-Brazil-Canada-China-Finland-France-Germany-Hong Kong-India-Israel-Italy-Japan-Malaysia-Malta-Morocco-Singapore-Spain-Sweden-Switzerland-United Kingdom-United States.8/8。
常州信宝UPS-B系列中文说明
充电时间
整机效率
市电断电转换时间
2KVA/1.6KW
3KVA/2.4KW
5KVA/4KW 3.75KVA/3KW
6KVA/4.8KW
220VAC+35%/-26%
5% 单相
13A
21A
26A
34/38A
220Vac 5% 可调
50 60 HZ
2% 0.5%停电时
正弦波
08 1 滞后 <3% 线性负载 电压最大变化 4%内 100%负载投入或切离
一 UPS 系统结构方块图 如图二十三所示
7 运转环境温度 0 40
四 安装方法 一 输入
1 禁止使用一般家庭用插座 因一般插座最大只用 15A 会造成过载 烧毁
2 请利用就近配电盒内 2Fra bibliotek0V 之电力接至 UPS 输入端 如图十一
图二十三 UPS 系统结构方块图
二 UPS 正常运转时之运作方法 当 UPS 正常运转时 市电电源经由滤波器滤除高阶波杂讯 如图二十四 所示 一路充电器对电池组充电 保持电池电力於满电位 另一路经由整 流器 整流成直流电 经变流器转成纯净之正弦波电源 再经由静态开关 滤波送至用户设备使用
109/218Vdc
#5
7 OUTPUT POWER 输出功率百分比%显示
100%
#6
8 TEMPERATURE 机内温度
25
#7
8. LCD 显示循环切换钮 数位讯号显示项目切换钮 9. UPS 开关机循环按键 UPS 日常开关机循环按键
1 按一下开关机循环按键 后 UPS 变流器开始启动 约 20 秒后转换成 UPS 变 流器供电输出 UPS 由内 部供电装置提供纯净的交 流输出电源
UPS不间断电源
UPS不间断电源学习资料不间断电源 - UPS定义山特 A 系列 UPSUPS是不间断电源(uninterruptible power system)的英文简称，是能够提供持续、稳定、不间断的电源供应的重要外部设备。
从原理上来说，UPS是一种集数字和模拟电路，自动控制逆变器与免维护贮能装置于一体的电力电子设备；从功能上来说，UPS可以在市电出现异常时，有效地净化市电；还可以在市电突然中断时持续一定时间给电脑等设备供电,使你能有充裕的时间应付；从用途上来说，随着信息化社会的来临，UPS广泛地应用于从信息采集、传送、处理、储存到应用的各个环节，其重要性是随着信息应用重要性的日益提高而增加的。
不间断电源 - UPS组成德国Piller不间断电源UPSUPS电源系统由4部分组成：整流、储能、变换和开关控制。
其系统的稳压功能通常是由整流器完成的，整流器件采用可控硅或高频开关整流器，本身具有可根据外电的变化控制输出幅度的功能，从而当外电发生变化时（该变化应满足系统要求），输出幅度基本不变的整流电压。
净化功能由储能电池来完成，由于整流器对瞬时脉冲干扰不能消除，整流后的电压仍存在干扰脉冲。
储能电池除可存储直流直能的功能外，对整流器来说就象接了一只大容器电容器，其等效电容量的大小，与储能电池容量大小成正比。
由于电容两端的电压是不能突变的，即利用了电容器对脉冲的平滑特性消除了脉冲干扰，起到了净化功能，也称对干扰的屏蔽。
频率的稳定则由变换器来完成，频率稳定度取决于变换器的振荡频率的稳定程度。
为方便UPS电源系统的日常操作与维护，设计了系统工作开关，主机自检故障后的自动旁路开关，检修旁路开关等开关控制。
不间断电源如图所示，在电网电压工作正常时，给负载供电如所示，而且，同时给储能电池充电；当突发停电时，UPS电源开始工作，由储能电池工给负载所需电源，维持正常的生产（如粗黑→所示）；当由于生产需要，负载严重过载时，由电网电压经整流直接给负载供电（如虚线所示）。
山特UPS电压说明书
3C10KS
3C15KS
3C20KS
警告：本产品用于第2类环境中的商业和工业用途，可能需要采取安装限制或附 加措施以抑制骚扰。
注：建议UPS输出线不大于10m，外接通信线、并机线及温度侦测线等不大于3m，否 则，可能需要采取安装限制或附加措施以抑制骚扰。
高海拔地区负载量=额定功率×降额系数（和海拔对应的） 海拔（m） 1000 1500 2000 2500 3000 3500 降额系数 100% 95% 91% 86% 82% 78%
感谢您使用山特产品！ 请严格遵守本手册和机器上的所有警告及操作说明，并妥善保管本手 册。在没有阅读完所有的安全说明和操作说明以前，请不要操作本 机。
严正声明
产品防伪
为了切实保障您的用电安全，帮助您购买到真正的山特 UPS，请注意以下事项：
1. 认准山特注册商标：
、
2. 山特电子（深圳）有限公司在中国从未以任何形式授权委托其它公司生产 UPS；
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版权声明
山特公司致力于技术创新，不断提供更好的产品和服务满足客户需求，对产品设计、 技术规格的更新，恕不另行通知。产品以实物为准。 请到山特网站 下载最新版的产品说明书。
使用保养 1. 使用环境及保存方法对本产品的使用寿命及可靠性有一定影响，请不要在以下工作
环境中使用：
A. 超出技术指标规定（温度0℃～40℃，相对湿度20%～90%）的高、低温和潮湿 场所；
B. 有振动、易受撞的场所； C. 有金属性粉尘、腐蚀性物质、盐份和可燃性气体的场所。 2. 如果长时间放置不使用，必须将UPS（不带电池）存放在干燥的环境中，存贮温度 范围：－25℃～＋55℃。UPS开机之前，必须先让环境温度回暖至0℃以上，并维 持2小时以上。
UPS常规 DTS、DTT系列说明书(2015.07.30)
目录第一章重要指示 (3)1.1.应用条件 (3)1.2.工作环境 (3)1.3.安全守则 (4)第二章产品信息 (6)2.1.产品命名规则 (6)2.2.主要性能特点 (8)2.3.技术参数 (9)第三章UPS外观简介 (13)3.1.DTS(DTT)—10～60KV A (13)3.2.DTS(DTT)—80～120KV A (14)3.3.显示面板功能简介 (15)3.4.其他 (16)第四章UPS组成部分简介 (17)4.1.整流器 (17)4.2.逆变器 (17)4.3.直流供电 (17)4.4.静态开关 (18)4.5.显示与触摸屏操作 (18)4.6.RS232智能通讯 (32)4.7.RS485智能通讯 (32)4.8.SNMP与远程网络通讯 (33)4.9.干接点工作状态通讯 (33)第五章UPS的工作原理 (35)5.1.整机工作原理 (35)5.2.市电工作模式 (36)5.3.直流逆变工作模式 (37)5.4.旁路运行模式 (37)5.5.手动维修旁路模式 (37)第六章UPS安装 (38)6.1.拆卸与检视 (38)6.2.UPS定位 (38)6.3.UPS电线缆连接 (39)6.4.接线检查 (40)第七章操作与管理 (41)7.1.开机前的准备工作 (41)7.2.第一次开机 (41)7.3.市电运行模式测试 (41)7.4.直流运行模式测试 (41)7.5.并机部分开机流程 (41)7.6.日常运行管理 (42)第八章日常护理 (43)8.1.预防维护 (43)8.2.报警与指示说明 (43)8.3.异常处理 (45)第九章搬运要求 (50)9.1.运输标识 (50)9.2.装卸与运输 (50)第十章装箱清单 (52)第一章 重要指示本手册包含电力UPS 的安装和使用的指导，并包含使用中的异常处理和维护: 在使用本产品前请仔细阅读本手册。
本手册必须由专业人员阅读理解并保存。
dsm UPS中文说明书
UPS说明书DSP6-1/1 DSP6-1/1-N DSP10-1/1 DSP10-1/1-N DSM10-3/1 DSM15-3/1 DSM20-3/1感谢您选用了CHAT UNION （捷联公司）的产品本文件内含有设备的操作信息任何人在开启UPS前，一定要仔细认真的阅读此文件1．…………………………………………………………….介绍1．1……………………………………………………………..型号介绍1．2……………………………………………………………..内部标记介绍2．………………………………………………………………安全说明3．………………………………………………………………安装说明3．１…………………………………………………………….拆包装及检测3．２…………………………………………………………….显示板说明3．３…………………………………………………………….外观及接口说明4．………………………………………………………………电路连接4．１…………………………………………………………….单机的连接4．２…………………………………………………………….并联机的连接5．………………………………………………………………操作说明5．1………………………………………………………………开机/关机5．2………………………………………………………………单机的操作说明5．3………………………………………………………………并联机的操作说明6．……………………………………………………………….远程通讯7．……………………………………………………………….故障及处理8．……………………………………………………………….指示灯和ＵＰＳ的状态9．……………………………………………………………….生产标准10．…………………………………………………………….技术参数11．…………………………………………………………….服务热线12．……………………………………………………………...保修条款1.简介1.1型号介绍DSM系列UPS电源是采用双变换纯在线技术设计,可以保护您的设备免受来自市电的各种干扰。
在线式UPS说明书-20120629
目录1. 重要安全事项 (1)2. 安装和设定 (2)2-1. 背面板图 (2)2-2. 设定UPS (2)3. 操作使用 (3)3-1. 按钮的操作 (3)3-2. LED面板 (4)4. 故障排除 (6)5. 存放和保养 (6)6. 电气规格 (7)●在需要搬运本台UPS 系统时，务必先以原包装材料包好，以防止并减缓意外的冲撞。
●本UPS系统在由寒冷环境直接送入室内等温暖环境时，内部可能会有结露情形。
此时，务必等到完全干燥后，才可进行安装。
为此，在移至安装场所后，请至少放置2小时，让UPS适应该环境后，再行安装。
●本UPS系统绝不可安装在附近有水或充满湿气的环境。
●本UPS系统绝不可安装在阳光直晒或附近有加热器类设备的场所。
●绝不可阻塞或遮蔽本UPS外壳上的通风孔。
●绝不可将可导致本UPS系统过载的设备(如激光打印机)连接到本UPS系统的输出插座。
●电源线等线路在配置上应避免会遭到踩踏或发生绊倒的地方。
●本UPS系统在设计上可由没有经验的人士使用和安装。
●本UPS系统插入的插座必须是个接地防雷插座，并应于靠近系统而易于取用。
●只能使用符合VDE测试标准、取得CE认证的电源线(例如您的计算机的主电源线) 将本UPS 系统连上屋内配线之插座(防雷插座)和将负载设备插上本UPS系统●在安装本产品时，应计算本UPS系统和插入的设备的总泄漏电流，确保总合不会超过3.5mA。
●绝不可在运作中断开UPS系统的主电源线或是使用中的屋内配线插座(防雷插座)，因为，如此一来，对UPS系统连同插上的负载设备的接地保护会失效。
●UPS系统内含电源(电池)，因此即便在未插在插座上，系统上的输出插座或输出终端器的部份仍会带电。
●防止液体或其他异物进入UPS系统内部。
●本UPS系统使用了具有危险性的电压电源；因此，任何维修仅允许具备维修资格的人员进行维修。
●注意–有触电风险。
即便本产品已由插座(屋内配线插座)取下，由于内部组件仍与内建的电池相连，所以仍带电而具危险性。
UPS
X光机---UPS内容的整理侯丽叶整理2010-3-10 什么是UPS？UPS的中文意思为“不间断电源”，是英语“Uninterruptible Power Supply”的缩写，它可以保障计算机系统在停电之后，继续工作一段时间以使用户能够紧急存盘，使您不致因停电而影响工作或丢失数据。
UPS是一种含有储能装置，以逆变器为主要组成部分的恒压、恒频的不间断电源。
当市电正常时，UPS将市电稳压或稳压、稳频后供负载使用，同时向机内电池充电；当市电中断时（异常时），UPS立即在4-10毫秒内或“零”中断时间内将蓄电池的电源通过逆变转换的方式向负载继续供应电力，使负载维持正常的工作，以便保存资料并保护负载的软硬件不受损坏。
从原理上来说，UPS是一种集数字和模拟电路,自动控制逆变器与免维护贮能装置于一体的电力电子设备；从功能上来说，UPS可以在市电出现异常时,有效地净化市电；还可以在市电突然中断时持续一定时间给电脑等设备供电,使你能有充裕的时间应付；从用途上来说，随着信息化社会的来临，UPS广泛地应用于从信息采集、传送、处理、储存到应用的各个环节，其重要性是随着信息应用重要性的日益提高而增加的。
UPS的作用它在计算机系统和网络应用中，主要起到两个作用：一是应急使用，防止突然断电而影响正常工作，给计算机造成损害；二是消除市电上的电涌、瞬间高电压、瞬间低电压、电线噪声和频率偏移等“电源污染”，改善电源质量，为计算机系统提供高质量的电源。
UPS的分类及工作原理UPS按其工作方式分为离线式（off line）式、在线式（on line）和线上互动式(Line-interactive）三类。
下面我们分别讲讲三种ups的工作原理：1、离线式UPS离线式UPS平时处于蓄电池充电状态，在停电时逆变器紧急切换到工作状态，将电池提供的直流电转变为稳定的交流电输出，因此离线式UPS也被称为后备式UPS。
然而这种UPS存在一个切换时间问题，因此不适合用在关键性的供电不能中断的场所。
UPS的基础知识课件.doc
UPS的基本知识一、UPS的概况1、UPS的概念Uninteruptible Power System 的英文字首简称为UPS，即我们所说的不间断电源系统，依照字面上的解释即为电力系统停止供电时，在极短的时间内取代原有的电力设备，继续供电给负载系统使用。
其工作原理：首先在正常时利用整流装置将交流输入整流成直流电力，然后一路对蓄电池充电，一路籍以将直流电力供给逆变器，逆变器将直流电力转换成稳定的交流电力输出经静态开关装置供给负载使用。
当输入电力中断时，由储存在蓄电池内的直流电力供应逆变器工作转换成交流电力供负载使用。
待市电完成供电准备后，才停止由蓄电池输出转换。
二、UPS的组成概要依UPS内部构造可分为：电池组、充电器、逆变器及静态开关。
1、电池组UPS 所用的电池种类相当多，其差别在于极板材质、构造及电解液成份的不同，目前广泛UPS采用的为铅酸免加水电池，其优点在于重量轻、寿命长。
电池容量单位为安培/ 小时（Ah），数值越大则表示电池的容量越大，一般UPS标准放电时间在满载状态下最长不超过15 分钟，若使用者欲延长放电时间则需另外加长效型充电电路来使用，由于电池为UPS市电中断后的电力来源，故其电池的品质及可靠度是不容忽视的，所以电池的品牌亦是选择UPS 的指标，最好能尽量选世界知名品牌。
2、充电器电池充电器经由变压器与市电隔离，对电池充电及提供逆变器电力，此电源需有足够的容量，但又必需有一定限流装置电路来保护电池的寿命，一般而言，对已耗尽电力的电池进行充电，将花费其放电时间常数的8 ～10 倍才能回充至额定压的80％，故标准型小容量在线式每放一次电需8 小时以上的充电时间才能恢复电力。
3、静态开关静态开关可由两个单向可控硅组成，以可控硅的高速开关特性来补偿输出继电器触点跳接时间，使AC与INV 转换时，转换时间小于5ms，因为继电器的跳接时间不能满足UPS负载的要求（电脑允许断电的最短时间小于6ms）。
UPS基础知识
UPS基础知识第一篇：UPS基础知识【IT168 资讯】UPS 的中文意思为“不间断电源”，是英语“Uninterruptible Power Supply”的缩写，它可以保障计算机系统在停电之后继续工作一段时间以使用户能够紧急存盘，使您不致因停电而影响工作或丢失数据。
它在计算机系统和网络应用中，主要起到两个作用：一是应急使用，防止突然断电而影响正常工作，给计算机造成损害；二是消除市电上的电涌、瞬间高电压、瞬间低电压、电线噪声和频率偏移等“电源污染”，改善电源质量，为计算机系统提供高质量的电源。
从基本应用原理上讲，UPS 是一种含有储能装置，以逆变器为主要元件，稳压稳频输出的电源保护设备。
主要由整流器、蓄电池、逆变器和静态开关等几部分组成。
1)整流器：整流器是一个整流装置，简单的说就是将交流（AC）转化为直流（DC）的装置。
它有两个主要功能：第一，将交流电（AC）变成直流电(DC)，经滤波后供给负载，或者供给逆变器；第二，给蓄电池提供充电电压。
因此，它同时又起到一个充电器的作用；2)蓄电池：蓄电池是UPS 用来作为储存电能的装置，它由若干个电池串联而成，其容量大小决定了其维持放电（供电）的时间。
其主要功能是：1当市电正常时，将电能转换成化学能储存在电池内部。
2当市电故障时，将化学能转换成电能提供给逆变器或负载；3)逆变器：通俗的讲，逆变器是一种将直流电（DC）转化为交流电（AC）的装置。
它由逆变桥、控制逻辑和滤波电路组成；4)静态开关：静态开关又称静止开关，它是一种无触点开关，是用两个可控硅（SCR）反向并联组成的一种交流开关，其闭合和断开由逻辑控制器控制。
分为转换型和并机型两种。
转换型开关主要用于两路电源供电的系统，其作用是实现从一路到另一路的自动切换；并机型开关主要用于并联逆变器与市电或多台逆变器。
UPS 类型UPS 电源按其工作原理可分为后备式、在线式以及在线互动式三种。
(1)后备式UPS后备式UPS：平时处于蓄电池充电状态，在停电时逆变器紧急切换到工作状态，将电池提供的直流电转变为稳定的交流电输出，因此后备式UPS 也被称为离线式UPS。
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µPSD323XFlash Programmable System Devices with8032Microcontroller Core and64Kbit SRAM FEATURES SUMMARYs TheµPSD323X Devices combine a Flash PSD architecture with an8032microcontroller core.TheµPSD323X Devices of Flash PSDs feature dual banks of Flash memory,SRAM,general purpose I/O and programmable logic,supervi-sory functions and access via USB,I2C,ADC, DDC and PWM channels,and an on-board 8032microcontroller core,with two UARTs, three16-bit Timer/Counters and two External Interrupts.As with other Flash PSD families,the µPSD323X Devices are also in-system pro-grammable(ISP)via a JTAG ISP interface.s Large8KByte SRAM with battery back-up options Dual bank Flash memories–128KByte or256KByte main Flash memory –32KByte secondary Flash memorys Content Security–Block access to Flash memorys Programmable Decode PLD for flexible address mapping of all memories within8032space.s High-speed clock standard8032core(12-cycle) s USB Interface(some devices only)s I2C interface for peripheral connectionss5Pulse Width Modulator(PWM)channelss Analog-to-Digital Converter(ADC)s Standalone Display Data Channel(DDC)s Six I/O ports with up to50I/O pinss3000gate PLD with16macrocellss Supervisor functions with Watchdog Timers In-System Programming(ISP)via JTAGs Zero-Power Technologys Single Supply Voltage–4.5to5.5V–3.0to3.6V Figure1.52-lead,Thin,Quad,Flat Package Figure2.80-lead,Thin,Quad,Flat PackageTQFP52(T)TQFP80(U)元器件交易网1/176 November2002元器件交易网µPSD323XTABLE OF CONTENTSSUMMARY DESCRIPTION (11)µPSD323X Devices Product Matrix(Table1.) (12)TQFP52Connections(Figure3.) (12)TQFP80Connections(Figure4.) (13)80-Pin Package Pin Description(Table2.) (14)52PIN PACKAGE I/O PORT (16)ARCHITECTURE OVERVIEW (17)Memory Organization (17)Memory Map and Address Space(Figure5.) (17)Registers (17)8032MCU Registers(Figure6.) (17)Configuration of BA16-bit Registers(Figure7.) (18)Stack Pointer(Figure8.) (18)PSW(Program Status Word)Register(Figure9.) (19)Program Memory (19)Data memory (19)RAM (19)Interrupt Location of Program Memory(Figure10.) (19)XRAM-DDC (19)XRAM-PSD (19)SFR (20)RAM Address(Table3.) (20)Addressing Modes (20)Direct Addressing(Figure11.) (20)Indirect Addressing(Figure12.) (20)Indexed Addressing(Figure13.) (21)Arithmetic Instructions (21)Arithmetic Instructions(Table4.) (22)Logical Instructions (22)Logical Instructions(Table5.) (23)Data Transfers (24)Data Transfer Instructions that Access Internal Data Memory Space(Table6.) (24)Shifting a BCD Number Two Digits to the Right(using direct MOVs:14bytes)(Table7.) (25)Shifting a BCD Number Two Digits to the Right(using direct XCHs:9bytes)(Table8.) (25)Shifting a BCD Number One Digit to the Right(Table9.) (25)Data Transfer Instruction that Access External Data Memory Space(Table10.) (26)Lookup Table READ Instruction(Table11.) (26)Boolean Instructions (27)Boolean Instructions(Table12.) (27)Relative Offset (27)2/176元器件交易网µPSD323XJump Instructions (28)Unconditional Jump Instructions(Table13.) (28)Machine Cycles (29)Conditional Jump Instructions (29)State Sequence inµPSD323X Devices(Figure14.) (30)µPSD3200HARDWARE DESCRIPTION (31)µPSD323X Devices Functional Modules(Figure15.) (31)MCU MODULE DISCRIPTION (32)Special Function Registers (32)SFR Memory Map(Table15.) (32)List of all SFR(Table16.) (33)PSD Module Register Address Offset(Table17.) (37)INTERRUPT SYSTEM (39)External Int0 (39)Timer0and1Interrupts (39)Timer2Interrupt (39)I2C Interrupt (39)External Int1 (39)DDC Interrupt (39)USB Interrupt (39)USART Interrupt (40)Interrupt System(Figure16.) (40)SFR Register(Table18.) (41)Interrupt Priority Structure (41)Interrupts Enable Structure (41)Priority Levels(Table19.) (41)Description of the IE Bits(Table20.) (41)Description of the IEA Bits(Table21.) (42)Description of the IP Bits(Table22.) (42)Description of the IPA Bits(Table23.) (42)How Interrupts are Handled (43)Vector Addresses(Table24.) (43)POWER-SAVING MODE (44)Idle Mode (44)Power-Down Mode (44)Power-Saving Mode Power Consumption(Table25.) (44)Power Control Register (44)Pin Status During Idle and Power-down Mode(Table26.) (44)Description of the PCON Bits(Table27.) (44)Idle Mode (44)3/176元器件交易网µPSD323XI/O PORTS(MCU Module) (46)I/O Port Functions(Table28.) (46)P1SFS(91H)(Table29.) (46)P3SFS(93H)(Table30.) (46)P4SFS(94H)(Table31.) (46)PORT Type and Description (47)PORT Type and Description(Part1)(Figure17.) (47)PORT Type and Description(Part2)(Figure18.) (48)OSCILLATOR (49)Oscillator(Figure19.) (49)SUPERVISORY (49)RESET Configuration(Figure20.) (49)External Reset (50)Low VDD Voltage Reset (50)Watchdog Timer Overflow (50)USB Reset (50)WATCHDOG TIMER (51)Watchdog Timer Key Register(WDKEY:0AEH)(Table32.) (51)Description of the WDKEY Bits(Table33.) (51)RESET Pulse Width(Figure21.) (52)Watchdog Timer Clear Register(WDRST:0A6H)(Table34.) (52)Description of the WDRST Bits(Table35.) (52)TIMER/COUNTERS(TIMER0,TIMER1AND TIMER2) (53)Timer0and Timer1 (53)Control Register(TCON)(Table36.) (53)Description of the TCON Bits(Table37.) (53)TMOD Register(TMOD)(Table38.) (54)Description of the TMOD Bits(Table39.) (54)Timer/Counter Mode0:13-bit Counter(Figure22.) (55)Timer/Counter Mode2:8-bit Auto-reload(Figure23.) (55)Timer/Counter Mode3:Two8-bit Counters(Figure24.) (56)Timer2 (56)Timer/Counter2Control Register(T2CON)(Table40.) (57)Description of the T2CON Bits(Table41.) (57)Timer/Counter2Operating Modes(Table42.) (58)Timer2in Capture Mode(Figure25.) (58)Timer2in Auto-Reload Mode(Figure26.) (59)4/176元器件交易网µPSD323XSTANDARD SERIAL INTERFACE(UART) (60)Multiprocessor Communications (60)Serial Port Control Register (60)Serial Port Control Register(SCON)(Table43.) (60)Description of the SCON Bits(Table44.) (61)Timer1-Generated Commonly Used Baud Rates(Table45.) (62)Serial Port Mode0,Block Diagram(Figure27.) (65)Serial Port Mode0,Waveforms(Figure28.) (66)Serial Port Mode1,Block Diagram(Figure29.) (66)Serial Port Mode1,Waveforms(Figure30.) (67)Serial Port Mode2,Block Diagram(Figure31.) (67)Serial Port Mode2,Waveforms(Figure32.) (68)Serial Port Mode3,Block Diagram(Figure33.) (68)Serial Port Mode3,Waveforms(Figure34.) (69)ANALOG-TO-DIGITAL CONVERTOR(ADC) (70)ADC Interrupt (70)A/D Block Diagram(Figure35.) (70)ADC SFR Memory Map(Table46.) (71)Description of the ACON Bits(Table47.) (71)ADC Clock Input(Table48.) (71)PULSE WIDTH MODULATION(PWM) (72)4-channel PWM unit(PWM0-3) (72)Four-Channel8-bit PWM Block Diagram(Figure36.) (73)PWM SFR Memory Map(Table49.) (74)Programmable Period8-bit PWM (75)Programmable PWM4Channel Block Diagram(Figure37.) (75)PWM4Channel Operation (76)PWM4With Programmable Pulse Width and Frequency(Figure38.) (76)I2C INTERFACE (77)Block Diagram of the I2C Bus Serial I/O(Figure39.) (77)Serial Control Register(SxCON:S1CON,S2CON)(Table50.) (78)Description of the SxCON Bits(Table51.) (78)Selection of the Serial Clock Frequency SCL in Master Mode(Table52.) (78)Serial Status Register(SxSTA:S1STA,S2STA) (79)Data Shift Register(SxDAT:S1DAT,S2DAT) (79)Serial Status Register(SxSTA)(Table53.) (79)Description of the SxSTA Bits(Table54.) (79)Data Shift Register(SxDAT:S1DAT,S2DAT)(Table55.) (79)Address Register(SxADR:S1ADR,S2ADR) (80)Address Register(SxADR)(Table56.) (80)Start/Stop Hold Time Detection Register(S1SETUP,S2SETUP)(Table57.) (80)System Cock of40MHz(Table58.) (80)System Clock Setup Examples(Table59.) (80)Programmer’s Guide for I2C and DDC2 (81)5/176元器件交易网µPSD323XDDC INTERFACE (83)DDC Interface Block Diagram(Figure40.) (83)Special Function Register for the DDC Interface (84)DDC SFR Memory Map(Table60.) (84)Description of the DDCON Register Bits(Table61.) (85)SWNEB Bit Function(Table62.) (86)Host Type Detection (87)Host Type Detection(Figure41.) (87)DDC1Protocol (88)Transmission Protocol in the DDC1Interface(Figure42.) (88)DDC2B Protocol (89)Conceptual Structure of the DDC Interface(Figure43.) (89)USB HARDWARE (90)USB related registers (90)USB Address Register(UADR:0EEh)(Table63.) (90)Description of the UADR Bits(Table64.) (90)USB Interrupt Enable Register(UIEN:0E9h)(Table65.) (91)Description of the UIEN Bits(Table66.) (91)USB Interrupt Status Register(UISTA:0E8h)(Table67.) (91)Description of the UISTA Bits(Table68.) (92)USB Endpoint0Transmit Control Register(UCON0:0EAh)(Table69.) (93)Description of the UCON0Bits(Table70.) (93)USB Endpoint1(and2)Transmit Control Register(UCON1:0EBh)(Table71.) (94)Description of the UCON1Bits(Table72.) (94)USB Control Register(UCON2:0ECh)(Table73.) (95)Description of the UCON2Bits(Table74.) (95)USB Endpoint0Status Register(USTA:0EDh)(Table75.) (95)Description of the USTA Bits(Table76.) (95)USB Endpoint0Data Receive Register(UDR0:0EFh)(Table77.) (95)USB Endpoint0Data Transmit Register(UDT0:0E7h)(Table78.) (95)USB Endpoint1Data Transmit Register(UDT1:0E6h)(Table79.) (95)USB SFR Memory Map(Table80.) (96)Transceiver (97)Low Speed Driver Signal Waveforms(Figure44.) (97)Receiver Characteristics (98)Differential Input Sensitivity Over Entire Common Mode Range(Figure45.) (98)External USB Pull-Up Resistor (99)USB Data Signal Timing and Voltage Levels(Figure46.) (99)Receiver Jitter Tolerance(Figure47.) (99)Differential to EOP Transition Skew and EOP Width(Figure48.) (100)Differential Data Jitter(Figure49.) (100)Transceiver DC Characteristics(Table81.) (101)Transceiver AC Characteristics(Table82.) (101)6/176元器件交易网µPSD323XPSD MODULE (102)Functional Overview (102)PSD MODULE Block Diagram(Figure50.) (103)In-System Programming(ISP) (104)Methods of Programming Different Functional Blocks of the PSD MODULE(Table83.) (104)DEVELOPMENT SYSTEM (105)PSDsoft Express Development Tool(Figure51.) (105)PSD MODULE REGISTER DESCRIPTION AND ADDRESS OFFSET (106)Register Address Offset(Table84.) (106)PSD MODULE DETAILED OPERATION (107)MEMORY BLOCKS (107)Primary Flash Memory and Secondary Flash memory Description (107)Memory Block Select Signals (107)Instructions (108)Instructions(Table85.) (109)Power-down Instruction and Power-up Mode (110)READ (110)Status Bit(Table86.) (111)Programming Flash Memory (112)Data Polling Flowchart(Figure52.) (112)Data Toggle Flowchart(Figure53.) (113)Erasing Flash Memory (114)Specific Features (115)Sector Protection/Security Bit Definition–Flash Protection Register(Table87.) (115)Sector Protection/Security Bit Definition–Secondary Flash Protection Register(Table88.) (115)SRAM (116)Sector Select and SRAM Select (116)Priority Level of Memory and I/O Components in the PSD MODULE(Figure54.) (117)VM Register(Table89.) (117)Separate Space Mode(Figure55.) (118)Combined Space Mode(Figure56.) (118)Page Register (119)Page Register(Figure57.) (119)PLDs (120)DPLD and CPLD Inputs(Table90.) (120)The Turbo Bit in PSD MODULE (120)PLD Diagram(Figure58.) (121)Decode PLD(DPLD) (122)DPLD Logic Array(Figure59.) (122)Complex PLD(CPLD) (123)Macrocell and I/O Port(Figure60.) (123)Output Macrocell Port and Data Bit Assignments(Table91.) (124)7/176元器件交易网µPSD323XProduct Term Allocator (125)CPLD Output Macrocell(Figure61.) (125)Input Macrocells(IMC) (126)Input Macrocell(Figure62.) (126)I/O PORTS(PSD MODULE) (127)General Port Architecture (127)General I/O Port Architecture(Figure63.) (127)Port Operating Modes (128)MCU I/O Mode (128)PLD I/O Mode (128)Address Out Mode (128)Peripheral I/O Mode (128)JTAG In-System Programming(ISP) (128)Peripheral I/O Mode(Figure64.) (129)Port Operating Modes(Table92.) (129)Port Operating Mode Settings(Table93.) (129)I/O Port Latched Address Output Assignments(Table94.) (129)Port Configuration Registers(PCR) (130)Port Configuration Registers(PCR)(Table95.) (130)Port Pin Direction Control,Output Enable P.T.Not Defined(Table96.) (130)Port Pin Direction Control,Output Enable P.T.Defined(Table97.) (130)Port Direction Assignment Example(Table98.) (130)Port Data Registers (131)Drive Register Pin Assignment(Table99.) (131)Ports A and B–Functionality and Structure (132)Port A and Port B Structure(Figure65.) (132)Port C–Functionality and Structure (133)Port C Structure(Figure66.) (133)Port D–Functionality and Structure (134)Port D Structure(Figure67.) (134)External Chip Select (135)Port D External Chip Select Signals(Figure68.) (135)POWER MANAGEMENT (136)APD Unit(Figure69.) (136)Enable Power-down Flow Chart(Figure70.) (137)Power-down Mode’s Effect on Ports(Table101.) (137)PLD Power Management (138)PSD Chip Select Input(CSI,PD2) (138)Input Clock (138)Input Control Signals (138)Power Management Mode Registers PMMR01(Table102.) (138)Power Management Mode Registers PMMR21(Table103.) (139)APD Counter Operation(Table104.) (139)8/176元器件交易网µPSD323XRESET TIMING AND DEVICE STATUS AT RESET (140)Warm RESET (140)I/O Pin,Register and PLD Status at RESET (140)Reset of Flash Memory Erase and Program Cycles (140)Reset(RESET)Timing(Figure71.) (140)Status During Power-on RESET,Warm RESET and Power-down Mode(Table105.) (141)PROGRAMMING IN-CIRCUIT USING THE JTAG SERIAL INTERFACE (142)Standard JTAG Signals (142)JTAG Port Signals(Table106.) (142)JTAG Extensions (142)Security and Flash memory Protection (142)INITIAL DELIVERY STATE (142)AC/DC PARAMETERS (143)PLD ICC/Frequency Consumption(5V range)(Figure72.) (143)PLD ICC/Frequency Consumption(3V range)(Figure73.) (143)PSD MODULE Example,Typ.Power Calculation at V CC=5.0V(Turbo Mode Off)(Table107.).144MAXIMUM RATING (145)Absolute Maximum Ratings(Table108.) (145)DC AND AC PARAMETERS (146)Operating Conditions(5V Devices)(Table109.) (146)Operating Conditions(3V Devices)(Table110.) (146)AC Symbols for Timing(Table111.) (147)Switching Waveforms–Key(Figure74.) (147)DC Characteristics(5V Devices)(Table112.) (148)DC Characteristics(3V Devices)(Table113.) (150)External Program Memory READ Cycle(Figure75.) (152)External Program Memory AC Characteristics(with the5V MCU Module)(Table114.) (152)External Program Memory AC Characteristics(with the3V MCU Module)(Table115.) (153)External Clock Drive(with the5V MCU Module)(Table116.) (153)External Clock Drive(with the3V MCU Module)(Table117.) (153)External Data Memory READ Cycle(Figure76.) (154)External Data Memory WRITE Cycle(Figure77.) (154)External Data Memory AC Characteristics(with the5V MCU Module)(Table118.) (155)External Data Memory AC Characteristics(with the3V MCU Module)(Table119.) (156)A/D Analog Specification(Table120.) (156)Input to Output Disable/Enable(Figure78.) (157)CPLD Combinatorial Timing(5V Devices)(Table121.) (157)CPLD Combinatorial Timing(3V Devices)(Table122.) (157)Synchronous Clock Mode Timing–PLD(Figure79.) (158)CPLD Macrocell Synchronous Clock Mode Timing(5V Devices)(Table123.) (158)CPLD Macrocell Synchronous Clock Mode Timing(3V Devices)(Table124.) (159)Asynchronous RESET/Preset(Figure80.) (160)9/176元器件交易网µPSD323XAsynchronous Clock Mode Timing(product term clock)(Figure81.) (160)CPLD Macrocell Asynchronous Clock Mode Timing(5V Devices)(Table125.) (160)CPLD Macrocell Asynchronous Clock Mode Timing(3V Devices)(Table126.) (161)Input Macrocell Timing(product term clock)(Figure82.) (162)Input Macrocell Timing(5V Devices)(Table127.) (162)Input Macrocell Timing(3V Devices)(Table128.) (162)Program,WRITE and Erase Times(5V Devices)(Table129.) (163)Program,WRITE and Erase Times(3V Devices)(Table130.) (163)Peripheral I/O READ Timing(Figure83.) (164)Port A Peripheral Data Mode READ Timing(5V Devices)(Table131.) (164)Port A Peripheral Data Mode READ Timing(3V Devices)(Table132.) (164)Peripheral I/O WRITE Timing(Figure84.) (165)Port A Peripheral Data Mode WRITE Timing(5V Devices)(Table133.) (165)Port A Peripheral Data Mode WRITE Timing(3V Devices)(Table134.) (165)Reset(RESET)Timing(Figure85.) (166)Reset(RESET)Timing(5V Devices)(Table135.) (166)Reset(RESET)Timing(3V Devices)(Table136.) (166)V STBYON Definitions Timing(5V Devices)(Table137.) (166)V STBYON Timing(3V Devices)(Table138.) (166)ISC Timing(Figure86.) (167)ISC Timing(5V Devices)(Table139.) (167)ISC Timing(3V Devices)(Table140.) (168)MCU Module AC Measurement I/O Waveform(Figure87.) (168)PSD MODULE AC Float I/O Waveform(Figure88.) (168)External Clock Cycle(Figure89.) (169)Recommended Oscillator Circuits(Figure90.) (169)PSD MODULE AC Measurement I/O Waveform(Figure91.) (169)PSD MODULEAC Measurement Load Circuit(Figure92.) (169)Capacitance(Table141.) (169)PART NUMBERING (174)PACKAGE MECHANICAL INFORMATION (170)PART NUMBERING (174)10/176SUMMARY DESCRIPTIONs Dual bank Flash memories–Concurrent operation,read from memory while erasing and writing the other.In-Appli-cation Programming(IAP)for remote updates –Large128KByte or256KByte main Flash memory for application code,operating sys-tems,or bit maps for graphic user interfaces –Large32KByte secondary Flash memory di-vided in small sectors.Eliminate external EE-PROM with software EEPROM emulation –Secondary Flash memory is large enough for sophisticated communication protocol(USB) during IAP while continuing critical system taskss Large SRAM with battery back-up option –8KByte SRAM for RTOS,high-level languag-es,communication buffers,and stackss Programmable Decode PLD for flexible address mapping of all memories–Place individual Flash and SRAM sectors on any address boundary–Built-in page register breaks restrictive8032 limit of64KByte address space–Special register swaps Flash memory seg-ments between8032“program”space and “data”space for efficient In-Application Pro-grammings High-speed clock standard8032core(12-cycle)–40MHz operation at5V,24MHz at3.3V–2UARTs with independent baud rate,three 16-bit Timer/Counters and two External Inter-ruptss USB Interface(µPSD3234A-40only)–Supports USB1.1Slow Mode(1.5Mbit/s)–Control endpoint0and interrupt endpoints1 and2s I2C interface for peripheral connections –Capable of master or slave operations5Pulse Width Modulator(PWM)channels –Four8-bit PWM units–One8-bit PWM unit with programmable peri-od s4-channel,8-bit Analog-to-Digital Converter (ADC)with analog supply voltage(V REF)s Standalone Display Data Channel(DDC)–For use in monitor,projector,and TV applica-tions–Compliant with VESA standards DDC1and DDC2B–Eliminate external DDC PROMs Six I/O ports with up to50I/O pins–Multifunction I/O:GPIO,DDC,I2C,PWM, PLD I/O,supervisor,and JTAG–Eliminates need for external latches and logics3000gate PLD with16macrocells–Create glue logic,state machines,delays, etc.–Eliminate external PALs,PLDs,and74HCxx –Simple PSDsoft Express software...Frees Supervisor functions–Generates reset upon low voltage or watch-dog time-out.Eliminate external supervisor device–RESET Input pin;Reset output via PLDs In-System Programming(ISP)via JTAG –Program entire chip in10-25seconds with no involvement of8032–Allows efficient manufacturing,easy product testing,and Just-In-Time inventory–Eliminate sockets and pre-programmed parts –Program with FlashLINK TM cable and any PC s Content Security–Programmable Security Bit blocks access of device programmers and readerss Zero-Power Technology–Memories and PLD automatically reach standby current between input changess Packages–52-pin TQFP–80-pin TQFP:allows access to8032address/ data/control signals for connecting to external peripherals11/17612/176Table 1.µPSD323X Devices Product MatrixFigure 3.TQFP52ConnectionsNote: 1.Pull-up resistor required on pin 5(2k Ωfor 3V devices,7.5k Ωfor 5V devices)for all 52-pin devices,with or without USB function.Part No.Main Flash (bit)Sec.Flash(bit)SRAM (bit)Macro -Cells I/O Pins PWM Ch.Timer/CtrUART Ch.I 2C ADC Ch.DDCUSBV CCMHz PinsuPSD 3234A-402M256K64K1641or5053214yes yes 5V 4052or80uPSD 3234BV-242M 256K 64K 165053214yes 3V 2480uPSD 3233B-401M 256K 64K 1641or 5053214yes 5V 4052or 80uPSD 3233BV-241M 256K 64K 1641or 5053214yes 3V 2452or 8039P1.5/ADC1 38P1.4/ADC0 37P1.3/TXD1 36P1.2/RXD1 35P1.1/T2X 34P1.0/T2 33V CC 32XTAL2 31XTAL1 30P3.7/SCL1 29P3.6/SDA1 28P3.5/T1 27P3.4/T0PD1 PC7 PC6 PC5 USB– PC4 USB+ V CC GND PC3 PC2 PC1 PC0 1 2 3 4 5(1) 6 7 8 9 10 11 12 1352 51 50 49 48 47 46 45 44 43 42 41 40P B 0P B 1P B 2P B 3P B 4P B 5V R E FG N DR E S E TP B 6P B 7A D C 3A D C 214151617181920212223242526P 4.7/P W M 4 P 4.6/P W M 3 P 4.5/P W M 2 P 4.4/P W M 1 P 4.3/P W M 0 G N D P 4.2/D D C V S Y N C P 4.1/D D C S C L P 4.0/D D C S D A P 3.0/R X D P 3.1/T X D P 3.2/E X I N T 0 P 3.3/E X I N T 1AI05790C13/176Figure 4.TQFP80ConnectionsNote:NC =Not Connected1.Pull-up resistor required on pin 8(2k Ωfor 3V devices,7.5k Ωfor 5V devices)for all 82-pin devices,with or without USB function.60P1.5/ADC1 59P1.4/ADC0 58P1.3/TXD1 57P2.3,A11 56P1.2/RXD1 55P2.2,A10 54P1.1/T2X 53P2.1,A9 52P1.0/T2 51P2.0,A8 50V CC 49XTAL2 48XTAL1 47P0.7,AD7 46P3.7/SCL1 45P0.6,AD6 44P3.6/SDA1 43P0.5,AD5 42P3.5/T1 41P0.4,AD4PD2 P3.3/EXINT1 PD1 PD0,ALE PC7 PC6 PC5 USB- PC4 USB+ NC V CC GND PC3 PC2 PC1 NC P4.7/PWM4 P4.6/PWM3 PC0123 45 6 7 8(1) 9 10 11 12 13 14 15 16 1718 192080 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61P B 0P 3.2/E X I N T 0P B 1P 3.1/T X DP B 2P 3.0/R X DP B 3P B 4P B 5N CV R E FG N DR E S E TP B 6P B 7R D ,C N T L 1P 1.7/A D C 3P S E N ,C N T L 2W R ,C N T L 0P 1.6/A D C 22122232425262728293031323334353637383940P A 7 P A 6 P 4.5/P W M 2 P A 5 P 4.4/P W M 1 P A 4 P 4.3/P W M 0 P A 3 G N D P 4.2/D C C V S Y N C P 4.1/D D C S C L P A 2 P 4.0/D D C S D A P A 1 P A 0 A D 0,P 0.0 A D 1,P 0.1 A D 2,P 0.2 A D 3,P 0.3 P 3.4/T 0AI05791BTable2.80-Pin Package Pin DescriptionPort Pin SignalNamePin No.In/OutFunctionBasic AlternateP0.0AD036I/O External BusMultiplexed Address/Data bus A1/D1P0.1AD137I/O Multiplexed Address/Data bus A0/D0P0.2AD238I/O Multiplexed Address/Data bus A2/D2P0.3AD339I/O Multiplexed Address/Data bus A3/D3P0.4AD441I/O Multiplexed Address/Data bus A4/D4P0.5AD543I/O Multiplexed Address/Data bus A5/D5P0.6AD645I/O Multiplexed Address/Data bus A6/D6P0.7AD747I/O Multiplexed Address/Data bus A7/D7P1.0T252I/O General I/O port pin Timer2Count input P1.1T2EX54I/O General I/O port pin Timer2Trigger input P1.2RxD256I/O General I/O port pin2nd UART Receive P1.3TxD258I/O General I/O port pin2nd UART Transmit P1.4ADC059I/O General I/O port pin ADC Channel0input P1.5ADC160I/O General I/O port pin ADC Channel1input P1.6ADC261I/O General I/O port pin ADC Channel2input P1.7ADC364I/O General I/O port pin ADC Channel3input P2.0A851I/O External Bus,Address A8P2.1A953I/O External Bus,Address A9P2.2A1055I/O External Bus,Address A10P2.3A1157I/O External Bus,Address A11P3.0RxD175I/O General I/O port pin UART ReceiveP3.1TxD177I/O General I/O port pin UART TransmitP3.2INTO79I/O General I/O port pin Interrupt0input/timer0gate controlP3.3INT12I/O General I/O port pin Interrupt1input/timer1gate controlP3.4T040I/O General I/O port pin Counter0inputP3.5T142I/O General I/O port pin Counter1inputP3.6SDA144I/O General I/O port pin I2C Bus serial data I/O P3.7SCL146I/O General I/O port pin I2C Bus clock I/OP4.0SDA233I/O General I/O port pin I 2C serial data I/O for DDCinterface P4.1SCL231I/O General I/O port pin I2C clock I/O for DDC interface P4.2VSYNC30I/O General I/O port pin VSYNC input for DDC interface14/17615/176P4.3PWM027I/O General I/O port pin 8-bit Pulse Width Modulation output 0P4.4PWM125I/O General I/O port pin 8-bit Pulse Width Modulation output 1P4.5PWM223I/O General I/O port pin 8-bit Pulse Width Modulation output 2P4.6PWM319I/O General I/O port pin 8-bit Pulse Width Modulation output 3P4.7PWM418I/OGeneral I/O port pinProgrammable 8-bit Pulse Width modulation output 4USB-8I/OUSB Pin Pull-up resistor required (2k Ωfor 3V devices,7.5k Ωfor 5V devices)for all devices,with or without USB B+10I/O USB PinAVREF 70O Reference Voltage input for ADC RD_65O READ signal,external bus WR_62O WRITE signal,external bus PSEN_63O PSEN signal,external bus ALE 4O Address Latch signal,external bus RESET_68I Active low RESET inputXTAL148I Oscillator input pin for system clock XTAL249O Oscillator output pin for system clock PA035I/O General I/O port pin 1.PLD Macro-cell outputs 2.PLD inputstched Address Out (A0-A7)4.Peripheral I/O ModePA134I/O General I/O port pin PA232I/O General I/O port pin PA328I/O General I/O port pin PA426I/O General I/O port pin PA524I/O General I/O port pin PA622I/O General I/O port pin PA721I/OGeneral I/O port pinPort Pin Signal Name Pin No.In/Out FunctionBasicAlternate16/17652PIN PACKAGE I/O PORTThe 52-pin package members of the µPSD323X Devices have the same port pins as those of the 80-pin package except:s Port 0(P0.0-P0.7,external address/data bus AD0-AD7)sPort 2(P2.0-P2.3,external address bus A8-A11)s Port A (PA0-PA7)s Port D (PD2)sBus control signal (RD,WR,PSEN,ALE)Pin 5requires a pull-up resistor (2k Ωfor 3V de-vices,7.5k Ωfor 5V devices)for all devices,with or without USB function.PB080I/O General I/O port pin 1.PLD Macro-cell outputs 2.PLD inputstched Address Out (A0-A7)PB178I/O General I/O port pin PB276I/O General I/O port pin PB374I/O General I/O port pin PB473I/O General I/O port pin PB572I/O General I/O port pin PB667I/O General I/O port pin PB766I/O General I/O port pin PC0TMS 20I JTAG pin 1.PLD Macro-cell outputs 2.PLD inputs3.SRAM stand by voltage input (V STBY )4.SRAM battery-on indicator (PC4)5.JTAG pins are dedicated pins PC1TCK 16I JTAG pinPC2V STBY 15I/O General I/O port pin PC3TSTA T 14I/O General I/O port pin PC4TERR 9I/O General I/O port pin PC5TDI 7I JTAG pin PC6TDO6O JTAG pinPC75I/O General I/O port pin PD1CLKIN 3I/O General I/O port pin 1.PLD I/O2.Clock input to PLD and APD PD2CSI1I/OGeneral I/O port pin1.PLD I/O2.Chip select to PSD Module Vcc 12Vcc 50GND 13GND 29GND 69NC 11NC 17NC71Port Pin Signal NamePin No.In/Out FunctionBasicAlternate17/176ARCHITECTURE OVERVIEW Memory OrganizationThe µPSD323X Devices’s standard 8032Core has separate 64KB address spaces for Program memory and Data Memory.Program memory is where the 8032executes instructions from.Data memory is used to hold data variables.Flash memory can be mapped in either program or data space.The Flash memory consists of two flash memory blocks:the main Flash (1or 2Mbit)and the Secondary Flash (256Kbit).Except during flash memory programming or update,Flash memory can only be read,not written to.A Page Register is used to access memory beyond the 64K bytes address space.Refer to the PSD Mod-ule for details on mapping of the Flash memory.The 8032core has two types of data memory (in-ternal and external)that can be read and written.The internal SRAM consists of 256bytes,and in-cludes the stack area.The SFR (Special Function Registers)occupies the upper 128bytes of the internal SRAM,the reg-isters can be accessed by Direct addressing only.There are two separate blocks of external SRAM inside the µPSD323X Devices:one 256bytes block is assigned for DDC data storage.Another 8K bytes resides in the PSD Module that can be mapped to any address space defined by the user.Figure 5.Memory Map and Address SpaceRegistersThe 8032has several registers;these are the Pro-gram Counter (PC),Accumulator (A),B Register (B),the Stack Pointer (SP),the Program Status Word (PSW),General purpose registers (R0to R7),and DPTR (Data Pointer register).Figure 6.8032MCU RegistersAI06635SECONDARY FLASHFLASHMAIN 32KB128KB OR256KBFF7FFFFF(DDC)8KB256B INT.RAMEXT.RAM EXT.RAMAddressingIndirect IndirectDirect or AddressingAddressingDirect SFRInternal RAM Space (256Bytes)FF00External RAM Space (MOVX)Flash Memory SpaceAI06636Accumulator B Register Stack Pointer Program Counter Program Status Word General Purpose Register (Bank0-3)Data Pointer RegisterPCHDPTR(DPH)A B SPPCL PSW R0-R7DPTR(DPL)。