PCB SI SOP For DDR2_2
DDR2 DDR3 SDRAM的PCB布线规则指导
Signal Integrity and PCB layout considerations for DDR2-800 Mb/s and DDR3 MemoriesFidus Systems Inc.900, Morrison Drive, Ottawa, Ontario, K2H 8K7, CanadaChris Brennan, Cristian Tudor, Eric Schroeter, Heike Wunschmann, and Syed BokhariSession # 8.13AbstractThe paper addresses the challenge of meeting Signal Integrity (SI) and Power Integrity (PI) requirements of Printed Circuit Boards (PCBs) containing Double Data Rate 2 (DDR2) memories. The emphasis is on low layer count PCBs, typically 4-6 layers using conventional technology. Some design guidelines have been provided.1. IntroductionDDR2 usage is common today with a push towards higher speeds such as 800 Mbps [1] and more recently, 1066 Mbps. DDR3 [2] targets a data rate of 1600 Mbps. From a PCB implementation standpoint, a primary requirement is delay matching which is dictated by the timing requirement. This brings into it a number of related factors that affect waveform integrity and delay. These factors are interdependent, but where a distinction can be made, they can be termed PCB layer stackup and impedance, interconnect topologies, delay matching, cross talk, PI and timing. Cadence ALLEGRO™SI-230 and Ansoft’s HFSS™ are used in all computations.Table 1: Comparison of DDR2 and DDR3 requirementsSignals common to both technologies and a general comparison of DDR2 and DDR3 is shown in Table 1. It must be noted that “matching” includes cases where the clock net may be made longer (termed DELTA in ALLEGRO SigXP). We have assumed a configuration comprising a Controller and two SDRAMs in most illustrations that follow.2. PCB Layer stackup and impedanceIn a layer constrained implementation, a 4 layer PCB (Figure 1) is a minimum with all routing on TOP and BOTTOM layers. One of the internal layers will be a solid ground plane (GND). The other internal plane layer is dedicated to VDD. Vtt and Vref can be derived from VDD. Use of a 6-layer PCB makes the implementation of certain topologies easier. PI is also enhanced due to the reduced spacing between power and GND planes. The interconnect characteristic impedance for DDR2 implementation can be a constant. A single-ended trace characteristic impedance of 50 Ohms can be used for all single-ended signals. A differential impedance of 100 Ohms can be used for all differential signals, namely CLOCK and DQS. Further, the termination resistor pulled up to VTT can be kept at 50 Ohms and ODT settings can be kept at 50 Ohms.In the case of DDR3 however, single ended trace impedances of 40 and 60 Ohms used selectively on loaded sections of ADDR/CMD/CNTRL nets have been found to be advantageous. Further, the value of the termination resistor pulled up to Vtt needs to be optimized in combination with the trace impedance through SI simulations. Typically, it is in the range 30 – 70 Ohms. The differential trace impedance can remain at 100 Ohms.Figure 1 : Four and Six layer PCB stackup3. Interconnect TopologiesIn both cases of DDR2 and DDR3, DQ, DM and DQS signals are point-to-point and do not need any topological consideration. An exception is in the case of multi-rank Dual In Line Memory Modules (DIMMs). Waveform integrity is also easily addressed by a proper choice of drive strengths and On Die Termination (ODT). The ADDR/CMD/CNTRL signals, and sometimes the clock signal will involve a multipoint connection where a suitable topology is needed. Possible choices are indicated in Figure 2 for cases involving two SDRAMs. The Fly-By Topology is a special case of a daisy chain with a very short or no stub.For DDR3, any of these topologies will work, provided that the trace lengths are minimized. The Fly-by topology shows the best waveform integrity in terms of an increased noise margin. This can be difficult to implement on a4-layer PCB and the need for a 6-layer PCB arises. The daisy chain topology is easier to implement on a 4 layer PCB. The tree topology on the other hand requires the length of the branch AB to be very close to that of AC (Figure 2). Enforcing this requirement results in the need to increase the length of the branches which affects waveform integrity. Therefore, for DDR3 implementation, the daisy chain topology with minimized stubs proves to be best suited for 4-layer PCBs.For DDR2-800 Mbps any of these topologies are applicable with the distinction between each other being less dramatic. Again, the daisy chain proves to be superior in terms of both implementation as well as SI.Where more than two SDRAMs are present, often, the topology can be dictated by constraints on device placement. Figure 3 shows some examples where a topology could be chosen to suit a particular component placement. Of these, only A and D are best suited for 4-layer PCB implementation. Again, for DDR2-800 Mbps operations all topologies yield adequate waveform integrity. For a DDR3 implementation, in particular at 1600 Mbps, only D appears to be feasible.Vtt RtRtRtTree topology Fly-By topologyFigure 2: ADDR/CMD/CNTRL topologies with 2 SDRAMS(A)Figure 3: ADDR/CMD/CNTRL topologies with four SDRAMS4. Delay matchingImplementing matched delay is usually carried out by bending a trace in a trombone shape. Routing blockage may require layer jumping. Unfortunately, while physical interconnect lengths can be made identical in layout, electrically, the two configurations shown in Figure 4 will not be the same.The case of trombone delay has been well understood, and the case of a via is obvious. The delay of a trombone trace is smaller than the delay of a straight trace of the same center-line length. In the case of a via, the delay is more than that of a straight microstrip trace of length equal to the via length. The problem can be resolved in two different ways. In the first approach, these values can be pre-computed precisely and taken into account while delay matching. This would become a tedious exercise which could perhaps be eased with userRtRtRt(B)(C)(D)Rtdefined constraints in ALLEGRO 16.0. In the second approach, one would use means to reduce the disparity to an acceptable level.Trombone traceStraight traceL 3L 2 L 4 ≠L 1L 5Figure 4: Illustration of Trombone traces and ViasFigure 5: Circuit for estimation of trombone effect and resulting waveforms.≠Straight traceVia cross sectional viewConsider the case of a trombone trace. It is known that the disparity can be reduced by increasing the length of L3 (Figure 4). Details can be found in reference [3]. A simulation topology can be set up in SigXP to represent parallel arms of a trombone trace as coupled lines. A sweep simulation is carried out with L3 (S in Figure 5) as a variable and the largest reasonable value that reduces the delay difference with respect to a reference trace is selected. For microstrip traces, L3 > 7 times the distance of the trace to ground is needed.Delay values are affected in a trombone trace due to coupling between parallel trace segments. Another way to reduce coupling without increasing the spacing is to use a saw tooth profile. The saw tooth profile shows better performance as compared to a trombone although it eventually ends up requiring more space. In either case, it is possible to estimate the effect on delay precisely by using a modified equation for the computation of the effective trace length [3]. This would need to be implemented as a user defined constraint in ALLEGRO.Consider the case of a through hole via on the 6 layer stackup of Figure 2. Ground vias placed close to the signal vias play an important role in the delay. For the illustration, the microstrip traces on TOP and BOTTOM layers are 150 mils long, and 4 mils wide. The via barrel diameter = 8 mils, pad diameter is 18 mils and the anti-pad diameter is 26 mils.Three different cases are considered. In the first case, the interconnect with via does not have any ground vias in its immediate neighborhood. Return paths are provided at the edges of the PCB 250 mils away from the signal via. In the second case, a reference straight microstrip trace of length = 362 mils is considered. The third case is the same as case 1 with four ground vias in the neighborhood of the signal via. Computed s-parameters with 60 Ohm normalization are shown in Figure 6. It can be seen that the use of 4 ground vias surrounding the signal via makes its behavior more like a uniform impedance transmission line and improves the s21 characteristic. In the absence of a return path in the immediate neighborhood, the via impedance increases. For the present purpose, it is important to know the resulting impact on the delay.A test circuit is set up similar to Figure 5. The driver is a linear source of 60 Ohms output impedance and outputs a trapezoidal signal of rise time = fall time = 100 ps and amplitude = 1V. It is connected to each of the 3 interconnects shown in Figure 6 and the far end is terminated in a 60 Ohm load. The excitation is a periodic signal with a frequency of 800 MHz. The time difference between the driver waveform at V = 0.5 V and the waveform at the receiver gives the switched delay.Results are illustrated in Figure 7 where only the rising edge is shown. It can be seen that the delay with four neighboring ground vias differs from that of the straight trace by 3 ps. On the other hand, the difference is 8 ps for the interconnect with no ground vias in the immediate neighborhood.It is therefore clear that increasing the ground via density near signal vias will help. However, in the case of 4 layer PCBs, this will not be possible as the signal traces adjacent to the Power plane will be referenced to a Power plane. Consequently, the signal return path would depend on decoupling. Therefore, it is very important that the decoupling requirement on 4 layer PCBs addresses return paths in addition to meeting power integrity requirements.The clock net is differential in both DDR2 and DDR3. In DDR2, DQS can be either single ended or differential although it is usually implemented as differential at higher data rates. The switched delay of a differential trace is less than that of a single ended trace of identical length. Where timing computations indicate the need, the clock and DQS traces may need to be made longer than the corresponding ADDR/CMD/CNTRL nets and DATA nets.and DQ nets.Since DQ and DM nets run at the maximum speed, it is desirable that all of these nets in any byte lane be routed identically, preferably without vias. Differential nets are less sensitive to discontinuities and where layer jumping is needed, the DQS and CLOCK nets should be considered first.Figure 6: s-parameters of interconnects with vias (60 Ohm normalization)Figure 7: Driver and Receiver waveforms for the 3 cases of Figure 6. (Plot colors correspond)5. CrosstalkCross talk contributes to delay uncertainty being significant for microstrip traces. This is generally reduced by increasing the spacing between adjacent traces for long parallel runs. This has the drawback of increasing the total trace length and therefore a reasonable value must be chosen. Typically the spacing should be greater than twice the trace distance to ground. Again, ground vias play an important role. Near and far end coupling levels are illustrated in Figure 8. Use of multiple ground vias reduces coupling levels by 7 dB. To derive the interconnect budget, a simulation of a victim trace with two aggressors on both sides is adequate. Using a periodic excitation on all nets will yield the cross talk induced jitter. Using a pseudo random excitation on all nets will show the effect of both cross talk as well as data dependencies. Time domain results are not shown here, but it is easily done by setting up a 5 coupled line circuit in SigXP with the spacing between traces set up for sweeping. Reasonable spacing values that keep the jitter in the waveform due to both cross talk as well as pattern dependence at an acceptable level are chosen.Figure 8: s-parameters of coupled traces (60 Ohm normalization)6. Power IntegrityPower Integrity here refers to meeting the Power supply tolerance requirement under a maximum switching condition. Failure to address this requirement properly leads to a number of problems, such as increased clock jitter, increased data dependent jitter, and increased cross talk all of which eventually reduce timing margins.The theory for decoupling has been very well understood and usually starts with the definition of a “target impedance” as [4]CurrentTransient tolerance Voltage Z et t =arg (1)An important requirement here is knowledge of the transient current under worst case switching condition. A second important requirement is the frequency range. This is the range of frequencies over which the decoupling network must ensure that its impedance value is equal to or below the required target impedance. On a printed circuit board, capacitance created by the Power-Ground sandwich and the decoupling capacitors needs to handle a minimum frequency of ~100 kHz up to a maximum frequency of ~100-200 MHz. Frequencies below 100 kHz are easily addressed by the bulk capacitance of the voltage regulator module. Frequencies above 200 MHz should be addressed by the on-die and in some cases on-package decoupling capacitance. Due to the finite inductance of the package, there is no need to provide decoupling on the PCB to handle frequencies greater than 200 MHz. The actual computation of power integrity can be very complex involving IC package details, simultaneously switched signals and the PCB power distribution network. For PCB design, the use of the target impedance approach to decoupling design is simpler and provides a practical solution with very little computational effort.The three power rails of concern are the VDD, VTT and Vref. The tolerance requirements on the VDD rail is ~ 5% and the transient current is determined as the difference between Idd7 and Idd2 as specified by JEDEC [1,4]. This is accomplished by using plane layers for power distribution and a modest number of decoupling capacitors. It is preferable to use decoupling capacitors of 10 different values distributed in the range of 10 nF to 10 uF. Further, the capacitor pad mounting structure should be designed for reduced mounted inductance.The Vref rail has a tighter tolerance, but it draws very little current. Its target impedance is easily met using narrow traces and one or two decoupling capacitors. It is important however that the capacitors be located very close to the device pins.The VTT rail proves to be challenging because it not only has a tighter tolerance, but it also draws a transient current close to that of the VDD rail. The transient current is easily calculated as described in reference [5]. Again, the target impedance requirement can be met using an increased number of decoupling capacitors.On a 4 layer PCB, the planes are too far apart and consequently the advantage of inter-plane capacitance is lost. The number of decoupling capacitors needs to be increased and higher frequency capacitors with values less than 10 nF may be needed. These computations are easily done using ALLEGRO SI Power Integrity option.7. TimingTiming computation is carried out as described in reference [6]. A table needs to be setup for the following eight cases: 1. 2. 3. 4. 5. 6. 7. 8. Write Setup analysis DQ vs. DQS Write Hold analysis DQ vs. DQS Read Setup analysis DQ vs. DQS Read Hold analysis DQ vs. DQS Write Setup analysis DQS vs. CLK Write Hold analysis DQS vs. CLK Write Setup analysis ADDR/CMD/CNTRL vs. CLK Write Hold analysis ADDR/CMD/CNTRL vs. CLKAn example is shown for the case of Write setup analysis in Table 2. Actual numbers have been omitted as they are not precisely known yet for DDR3. These numbers are obtained from data sheets of Controller and memory manufacturers. The numbers in the interconnect section are determined by SI simulations. All the eight cases need to be analyzed for DDR2. For DDR3, 5 and 6 are not needed due to its write leveling feature. In the PCB implementation, length match tolerances must ensure that the total margin is positive. ElementControllerSkew Componenta.)DQ vs. DQS skew at transmitter output b.) Data / Strobe PLL jitter a+b Setup requirement (tDSb @ Vih/Vil level) DQ slew rate DQS slew rateSetupUnitsps ps ps psCommentsFrom controller design data Used if not included in transmitter skewTotal Controller SDRAM (or DIMM)V/ns V/ns psTotal SDRAM setup requirement InterconnecttDSb + slew rate adjustmentFrom SDRAM datasheet; this number is to be adjusted based on DQ and DQS slew rates Measured as per JEDEC specification from SI simulation results Measured as per JEDEC specification from SI simulation results Includes slew rate adjustmenta.) Data Xtalk b.) DQS Xtalk c.) Length matching tolerance d.) Characteristic impedance mismatch Total Interconnect Min. Total Setup Budget Setup margin Interconnect skew (a + b + c + d) 0.24*tckps ps ps ps2 aggressors (one each side of the victim); victim – repetitive; aggressor- PRBS 2 aggressors (one each side of the victim); victim – repetitive; aggressor- PRBS Extracted from SI simulation results longest data net, worst case PVT corner can be omitted if routing of DQ and corresponding DQS signals are done on same layerps ps From SDRAM datasheet (includes clock duty cycle variation) Must be positiveMin. Total Setup Budget – (Total Controller + Total SDRAM + Total Interconnect )psTable 2: Illustration of DDR3 Write Setup timing analysis summary for DQ vs. DQS8. PCB LayoutImplementation on a PCB involves a number of tradeoffs to meet SI requirements. Often, the question is how far does one need to go? PCB layout tasks are facilitated using the following approach: 1. Set up topology and constraints in ALLEGRO Constraint Manager. 2. Design Controller BGA breakout. A controller pin arrangement with ADDR/CMD/CNTRL pins in the middle and DQ/DQS/DM byte lanes on either side is best suited. Within these groups, individual pins may need to be swapped to ensure routing with minimum cross-over. 3. Attempt routing with reduced stub length and a minimum trace spacing as obtained from cross talk simulation. Often, most stubs can be eliminated but it will not be possible for all the pins. One may try two traces between BGA pads of the memory devices. This would require narrow PCB traces which can increase manufacturing cost. Yet, it will not be possible for all signals unless micro via and via-in-pad technology is used. Complete routing with coarse length matching tolerances. 4. Place Vref decoupling capacitors close to the Vref pins. Vtt decoupling can be placed at the far end of the last SDRAM and will not come in the way of routing. VDD decoupling can be placed close to devices where possible without blocking routing channels. The smaller valued capacitors should be placed closer to the devices. With a proper decoupling design, it will not be necessary to cram all capacitors close to the devices. All decoupling capacitors should use a fan out for the footprint designed for reduced inductance. This is typically two short wide traces perpendicular to the capacitor length. This can be automated by using a user defined capacitor footprint that can be attached to all the decoupling capacitors in the schematic. 5. Implement fine length matching and insert multiple ground vias where signal traces jump layers. It is better to use the delay matching option in ALLEGRO and one must include z-axis delay. Typically, P and N nets of differential pairs should be matched with a tolerance of +/- 2ps and the tolerance for all other matched nets can be +/- 10 ps or more based on the timing margin computation.9. DIMMConsiderations described above apply to the case of PCBs containing one or more DIMMs. The only exception is that the decoupling requirement for the memories can be relaxed as it is already accounted for on the DIMM PCB. SI analysis of registered DIMMs is also much simpler where the DIMM is treated as a single load. While the routing topology for ADDR/CMD/CNTRL nets is usually a daisy chain with reduced stubs, tree topologies can also be used for registered DIMMs. Analysis of un-buffered DIMMs can become tedious as the timing requirement at all the SDRAMs must be analyzed. DIMM routing on 4-layer PCBs is relatively simpler compared to the case of SDRAMs.10. ExamplesThe detail described above has been used in the implementation of a DDR2 PCB, a DDR3 PCB and a DDR3 – DIMM PCB. The controller is from MOSAID [7] which is designed to provide both DDR2 as well as DDR3 functionality. For the SI simulations, IBIS models have been used. Models for the memories are from MICRON Technology, Inc [8]. The IBIS models for the DDR3 SDRAMs were available at 1333 Mbps speed. These were used at 1600 Mbps. For the unbuffered DDR3 DIMM (MT_DDR3_0542cc) EBD models from Micron Technology were used. All waveforms are for the typical case and are computed at the SDRAM die. The 6 layer PCB stackup of Figure 2 is used with routing on TOP and BOTTOM layers only. The memory consists of 2 SDRAMsrouted as a daisy chain. In the case of the DIMM, a single unbufferred DIMM is used. TOP/BOTTOM layer routing and Signal Integrity waveforms are shown in Figures. 9-11.Snapshots ofFigure 9: Illustration of TOP and BOTTOM layers of a DDR3 PCB with computed waveforms at the farthest SDRAM. Waveform on left is an ADDRESS net compared to that of the CLOCK net. Waveform on the right is a DATA net compared to that of a DQS net. Clock frequency = 800 MHz and data rate is 1600 Mbps.Figure 10: Illustration of TOP and BOTTOM layers of a DDR2 PCB with computed waveforms at the farthest SDRAM. Waveform on left is an ADDRESS net compared to that of the CLOCK net. Waveform on the right is a DATA net compared to that of a DQS net. Clock frequency = 400 MHz and data rate is 800 Mbps.Figure 11: Illustration of TOP and BOTTOM layers of a DDR3 – DIMM PCB with computed waveforms at the 8th (last) SDRAM on DIMM. Waveform on left is an ADDRESS net compared to that of the CLOCK net. Waveform on the right is a DATA net compared to that of a DQS net.Lastly, Figure 12 shows a comparison of computed and measured DATA eye patterns of an 800 Mbps DDR2. In all cases waveform integrity can be seen to be excellent.Figure 12: Computed (Red) and Measured (blue) waveforms of a data net of an 800 Mbps DDR2 PCB.11. ConclusionIn this paper, all aspects related to SI, and PI of DDR2 and DDR3 implementation have been described. Use of Constraint Manager in ALLEGROTM makes implementation easy. While a four layer PCB implementation of 800 Mbps DDR2 and DDR3 appears to be feasible, DDR3-1600 Mbps will prove to be challenging. It will become clearer as the memory devices become available and one has a good handle on timing numbers.References[1] DDR2 SDRAM Specification, JEDEC JESD79-2B, January 2005. [2] DDR3 SDRAM Standard, JEDEC JESD79-3, June 2007. [3] Syed Bokhari, “Delay matching on Printed Circuit Boards”, Proceedings of the CDNLIVE 2006, San Jose. [4] Larry D Smith, and Jeffrey Lee, “Power Distribution System for JEDEC DDR2 memory DIMM, Proc. IEEE EPEP conference, Princeton, N.J., pp. 121-124, October 2003. [5] Hardware and layout design considerations for DDR2 SDRAM Memory Interfaces, Freescale semiconductor Application Note, Doc. No. AN2910, Rev. 2, 03/2007. [6] DDR2 design guide for 2 DIMM systems, Technical Note, Micron Technology Inc. TN-47-01, 2003. [7] /corporate/products-services/ip/SDRAM_Controller_whitepaper_Oct_2006.pdf [8] /products/dram/ddr2/partlist.aspx?speed=DDR2-800 [9] /products/dram/ddr3/partlist.aspx?speed=DDR3-1066。
DDR2布线约束参考
布线约束参考路径分成三段? 路径 1（#1）： 控制器到第一条 DIMM 的路径，包括 DQ/DQS 信号、地址信号和控制信号。
? 路径 2（#2）： 第一条 DIMM到第二条 DIMM之间的路径，包括 DQ/DQS信号、地址信号和和控制信号。
? 路径 3（#3）： 第二条 DIMM到VTT上拉电阻的路径，只有地址信号和控制信号。
数据信号有 ODT。
约束以下关键长度? #1典型长度在 1900mil至 4500mil 之间。
? #2 典型长度约为 425mil左右。
? #3典型长度在 200mil至 550mil 之间。
#3 丌需要时序约束。
? 同一个数据信号组（包括 DQ 及对应 DQS）需要精确的匹配长度，长度差异要求在+/‐50mil。
其中分配给#1度差异要求在+/‐30mil，分配给#2的长度差异要求在+/‐20mil。
? 所有数据信号组的组间长度差异要求在+/‐500mil。
? 地址信号间的长度差异要求在+/‐200mil。
DDR，DDR2的时序要求一般比较高，所以对于时钟、地址控制线、数据、DQS等的等长要求较高。
以下简单说一下DDR，DDR2的等长布线要求DDR 时钟（查分）:一般要求差分阻抗100欧。
线宽、间距需要根据叠层结构计算出来，与其他走线的间距要满足3w规则；必需精确匹配差分对走线误差，允许在＋30mil 以内。
DDR 地址、片选及其他控制线：单端阻抗50欧。
应走成菊花链状拓扑，可比ddrclk 线长1000－2500mil，绝对不能短。
DDR 数据线，ddrdqs，ddrdm 线：单端阻抗50欧。
最好在同一层布线。
数据线与时钟线的线长差控制在50mil 内。
其中要特别注意DQS的走线，要满足3W规则。
其中PCB走线阻抗都要根据实际的叠层结构计算。
2010年03月10日 星期三 22:57DDR SDRAM：严格的说DDR应该叫DDR SDRAM，人们习惯称为DDR，部分初学者也常看到DDR SDRAM，就认为是SDRAM。
DDR2设计指导
DDR2设计指导目录1DDR2基本功能描述 (4)1.1DDR2电平 (5)2DDR2 PCB设计 (6)2.1常用拓扑结构 (6)2.1.1DIMM拓扑分析 (6)2.1.2颗粒拓扑分析 (6)2.2走线规则及时序 (7)2.2.1时序 (8)3仿真分析拓扑模板 ..................................................................................... 错误！未定义书签。
图目录图1OCD功能示意 (4)图2ODT可变更参数（EMRS表示内部寄存器） (5)图3电压标准 (5)图4过冲示意图 (5)图52T（左）、1T（右）模式2DIMM各信号流向描述 (6)图6地址拓扑结构 (7)图71驱4地址拓扑 (7)图8DDR2时序关系示意图 (8)1 DDR2基本功能描述DDR2（Double Data Rate 2）SDRAM是由JEDEC进行开发的新生代内存技术标准，它与上一代DDR内存技术标准的区别在于，虽然同是采用了在时钟的上升/下降沿同时进行数据传输的基本方式，但DDR2内存拥有两倍于上一代DDR内存预读取能力（即：4bit数据读预取），DDR2内存每个时钟能够以4倍外部总线的速度读/写数据，并且能够以内部控制总线4倍的速度运行。
DDR2内存采用SSTL_1.8电压标准，相对于DDR标准的SSTL_2.5，降低了不少，因而提供了明显的更小的功耗与更小的发热量，这一点的变化意义重大。
在继承了DDR的优点之外，DDR II新增了OCD、ODT和Post CAS三项功能。
OCD（Off-Chip Driver）：也就是所谓的离线驱动调整，DDR II通过OCD可以提高信号的完整性。
DDR II通过调整上拉（pull-up）/下拉（pull-down）的电阻值使两者电压相等。
使用OCD 通过减少DQ-DQS的倾斜来提高信号的完整性；通过控制电压来提高信号品质。
DDR2内存时序调节方法
DDR2内存时序调节方法DDR2内存已经成为目前绝大部分用户的标配产品，而如何合理设置DDR2的参数就成为了不少用户（尤其是菜鸟用户）的最想了解的地方。
当你超频的时候，如何平衡内存频率和参数之间的关系；究竟如何合理选取内存频率，什么参数才是带来最高性能呢？相信这些问题是目前最多用户最想了解。
其实要了解这些东西，首先要明白DDR2内存在BIOS中的参数设置情况。
因为要提高系统整体性能，并不只是简单超频CPU外频，调高内存频率这么简单，将一大堆数字合理地分配和组合才是最为重要的。
目前市场上销售的DDR2内存主要按频率来划分，譬如DDR2 533、DDR2 667、DDR2 800就是消费者最常见的产品（注：部分厂商推出DDR2 1000高频DDR2内存，但这些DDR2内存在市场上并不多见，而价格昂贵，所以我们就暂时不讨论一些超频型DDR2内存）。
在这三款内存产品当中，就数DDR2 667内存最为多人购买，因为它同时具备了性能、价格、兼容性这些特点，而DDR2 533已经逐步被DDR2 667所取代。
如果您的内存为镁光D9颗粒，请直接参考本站《镁光小D9内存超频调教全攻略》，如果您是DDR内存，请参考本站《教你如何调整DDR内存参数》 至于目前频率较高DDR2 800也逐渐成为玩家购买的对象，因为Intel双核心平台对高频DDR2内存有着极大需求，要发挥酷睿2最大威力，一条高频率、可运行高参数的DDR2内存是非常重要的。
鉴于AMD AM2处理器内置了DDR2内存控制器，所以AM2平台的DDR2设置方法与Intel平台有着不同。
最稳当的DDR2内存设置方法，就是在主板BIOS当中将DDR2的设置参数设为By SPD，而这个选项也是最安全的DDR2内存设置方法。
不过这个设置最大缺点是，没有将内存的潜力发挥出来，只是用安全换来相对较低的性能。
如果你想超频手中的DDR2，那么By SPD选项将不是你的设置的地方，手动调整才是你的手段。
DDR2高速PCB设计和信号完整性分析
DDR2高速PCB设计和信号完整性分析邓思维;凌凯【摘要】随着现代高速电路设计的发展,DDR2因其内存强大的预读取能力成为许多嵌入式系统的选择.然而,DDR2的仿真工作不仅繁琐耗时量大,对EMI的仿真也比较困难,给PCB设计也带来了大量的工作难点.文中针对DDR2高速电路中存在的信号完整性问题进行了分析,提出了PCB设计要点.并以单个DDR2存储器与控制器间的PCB设计为例,对如何在减少仿真工作的情况下成功完成一个可用的设计进行了论述.【期刊名称】《电子科技》【年(卷),期】2015(028)004【总页数】4页(P132-134,138)【关键词】DDR2;PCB;信号完整性【作者】邓思维;凌凯【作者单位】许继电源有限公司研发部,河南许昌461000;许继电源有限公司研发部,河南许昌461000【正文语种】中文【中图分类】TN41DDR2内存强大的预读取能力使其成为许多嵌入式系统的选择,然而,由于其具有的高频与快速的上升、下降沿,给PCB设计带来了困难。
PCB设计者不仅需要严格遵循通用的高速PCB布线规则,更要对系统中的各种信号完整性问题进行一一分析与解决。
当然,对于电路中的问题逐个仿真是一种比较有效的方法,虽然仿真成功并不能保证设计完美,却可以排除大量的错误。
但是,DDR2的仿真工作不仅繁琐耗时量大,对EMI的仿真也比较困难,特别当一些单位并没有专门的仿真人员或者项目时间紧张,逐个仿真是不切实际的。
本文以单个DDR2存储器与控制器间的PCB设计为例,讲述了如何在减少仿真工作的情况下成功完成一个可用的设计。
DDR2电路的主要组成部分为控制器U1和DDR2存储器U3,此外还有一些小封装的串联电阻和旁路电容。
如图1所示,从U1到U3要形成一个电路隔离区,串联电阻在两者中间,而旁路电容在线路板的另一面。
DDR2电路与其它电路隔离距离越大越好,推荐20 mil(1mil=0.025 4 mm)以上。
在满足布线空间的情况下,控制器U1与DDR2存储器U3之间的距离越小越好。
ddr2原理
ddr2原理DDR2原理。
DDR2是一种双倍数据传输速率（Double Data Rate 2）的内存类型，它具有高速、高密度和低功耗的特点，被广泛应用于计算机和其他电子设备中。
DDR2内存的原理及其工作方式对于理解计算机内存的工作原理和性能优化具有重要意义。
本文将对DDR2内存的原理进行详细介绍，希望能帮助读者更好地理解和应用DDR2内存。
DDR2内存的原理主要包括以下几个方面，时序结构、数据传输、电压规范和频率调节。
首先，DDR2内存的时序结构是指内存模块在数据传输过程中的时序控制，它包括预充电、激活、读取和写入等时序信号。
这些时序信号的准确控制对于DDR2内存的稳定工作至关重要。
其次，DDR2内存的数据传输是指内存模块在读取和写入数据时的传输方式，它采用双倍数据传输速率，即在一个时钟周期内可以传输两次数据，从而提高了数据传输效率。
此外，DDR2内存的电压规范是指内存模块工作时所需的电压范围，它通常为1.8V，低于DDR内存的2.5V，从而降低了功耗和发热。
最后，DDR2内存的频率调节是指内存模块在不同工作频率下的性能表现，它通常以MHz为单位，频率越高表示内存工作速度越快。
在实际应用中，DDR2内存的原理对于优化系统性能和提高数据处理速度具有重要意义。
首先，通过合理调整时序结构和频率调节，可以提高DDR2内存的工作效率和稳定性，从而提高系统整体性能。
其次，通过采用低电压规范，可以降低系统功耗和发热，延长设备的使用寿命。
最后，通过合理设计数据传输方式，可以提高数据处理速度和响应时间，从而提升用户体验和系统的实时性。
总之，DDR2内存的原理是计算机内存技术的重要组成部分，它的高速、高密度和低功耗特点使其在各种电子设备中得到广泛应用。
通过深入理解DDR2内存的原理，可以更好地应用和优化DDR2内存，从而提高系统性能和用户体验。
希望本文对读者理解DDR2内存的原理有所帮助，谢谢！以上就是关于DDR2原理的介绍，希望对您有所帮助。
使用Cadence_PCB_SI应对DDR3的挑战
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库管理
关键器件预布局
布线前规则规划
•在高速设计流程的最初阶段，硬件工程师和SI工程师需要通力合作做好PCB设 计的基本要求和关键信号的规则规划
33
关键器件预布局
•对于很多系统设计，主要芯片和接插件的布局已经预先确定了。可以优先执行 这部分元件的布局。
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传统设计流程
项目创建和设置 原理图设计 规则获取和规划 打包原理图 PCB设计 生产文件输出
设计差异管理 库管理
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设计同步
高速PCB设计流程
布线前规则规划 项目创建和设置
原理图输入
前仿真分析 规则驱动布局 规则驱动布线 布线后DRC检查 后仿真验证 生产文件输出
Input
Vref
10
Fly-by拓扑
•Fly-by拓扑可提高DDR3的时钟/地址/命令信号的信号完整性
DDR/DDR2 DIMM
11
写入校准(Write Leveling)
•补偿因fly-by拓扑带来的数据选通对于时钟的时序偏移
12
• 建立和保持时间的要求从数值上不再是单一值，而是随着 地址/数据信号的变化沿斜率的变化而变化
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DDR3设计的主要挑战 - 信号质量
• 阈值电压
– 直流和交流 – 噪声裕量
• 过冲和下冲
– 幅值 – 面积
• tVAC
– 信号在阈值上停留的最小时间
• 眼图
– 计算了抖动后的有效数据窗口
• 拓扑结构
– 数据类信号：点对点拓扑 – 地址类信号：Fly-By拓扑
• 信号线阻抗
– 例如地址类信号，主干的阻抗要求是45ohm，分支的阻抗要求是60ohm – 允许的阻抗误差百分比
PCB SI介绍
PCB SI 介绍目前用户最需要是一个时序分析和SI 结合一体工具，而且界面要优化，设置要简单，同时需要包括DesignKIT。
ICXTau 如果能够象Quantum－SI 一样性能得到改进，那么将会受到用户欢迎。
由于Mentor 具有设计前端和后端，ICX＋Tau 优势是其它工具无法取代。
时序问题是关键问题，目前设计者基本上采用核心芯片厂家现成方案，因此设计中主要一部分工作是如何保证PCB 能够符合芯片工作要求时序。
，目前国内用户基本没有掌握时序问题。
少数SQ 用户会采用Excel 表来编制时序要求，后期把从SQ 中测量出参数手工填写到Excel 表中去计算是否最终设计符合时序要求。
无论是原理图设计者和PCB 布线设计者都很难从芯片数据单中读懂时序。
时序问题主要并行接口问题。
普通SI 问题。
即解决驱动问题、端接电阻或串接阻尼电阻数值计算、PCB 层压结构和特性阻抗计算，走线拓扑结构分析。
对于普通SI 问题，Hyperlynx、SQ 和ICX 都可以很好解决。
国内用户基本上已经掌握了如何处理和分析普通SI问题。
就工具而言，SQ、Hyperlynx 或ICX 都可以很好解决。
性能上，SQ 长处是它本身就是一个PCB 布局布线工具，因此其适合实际PCB 布局布线上性能上比较好，也即现场调试性能比较好。
但是SQ 没有时序分析能力，只有简单有限时序测量功能。
Hyperlynx 优点是容易使用，不过既没有时序分析功能，也无时序测量功能。
相当来说，Hyperlynx 在EMC 预测上比较方便，这是Hyperlynx 优点。
ICX 其GUI 上弱点和设置复杂性使得用户不大愿意采用该工具。
目前普通SI 问题，主要是PCB 布线设计者在进行。
原理图设计者则基本不做该方面工作。
主要原因是工具使用不熟悉和对SI 了解较少。
微波段传输问题。
即通常所称GHzSI。
设计需要解决传输链路上因为走线、过孔和材料等小尺寸形状引起各种通常只有在微波领域才会考虑问题。
DDRII接口SI仿真实例
上海佳研仿真工作室 ----- DDRII 接口SI 仿真实例某单板使用了一片FPGA，该FPGA 带了一片DDRII 颗粒，本报告将对这个DDRII 接口进行仿真分析，通过仿真分析验证现有布局、信号匹配措施及芯片内部接口配置是否满足信号质量要求，并为单板布线提供约束规则。
一、DDRII 接口布局该接口是最简单的点对点拓扑，布局方面需要考虑的并不多，预布局图如下：二、SI 仿真分析本文主要是用CADENCE 软件对该DDRII 接口进行SI 仿真分析，通过仿真分析确定VTT 上拉电阻的取舍，匹配电阻取舍及ODT 功能是否启用，保证单板信号质量及为单板降成本设计提供指导。
1、差分时钟CK 信号信号名称 F_CK_P, F_CK_N 数率 108M方向 FPGA ÆDDRII 仿真模式 Typical/SLOW/FASTXP2_s2d180f120aaaaaaaaou器件模型U27Y_CLKINj i a y a n j i a y a n j i a y a n j i a y a n j i a y a n j i a y a n j i a y a n j i a y a n j i a y a n j i a y a n j i a y a n j i a y a nj i a y a n结论信号质量OK, 建议R84这个100欧姆的终端匹配电阻布局布线的时候尽量靠近DDRII 放置，差分信号严格控制100欧姆的阻抗。
差分时钟CK 信号拓扑结构：仿真得到的接收端波形：j i a y a n j i a y a n j i a y a n j i a y a n j i a y a n j i a y a n j i a y a n j i a y a n j i a y a n j i a y a n j i a y a n j i a y a nj i a y a n对应于器件datasheet 资料中对该信号质量的要求：j i a y a n j i a y a n j i a y a n j i a y a n j i a y a n j i a y a n j i a y a n j i a y a n j i a y a n j i a y a n j i a y a n j i a y a nj i a y a n从器件资料中得到，对该波形主要的关注点是CROSS POINT,他要求的值是0.50 × V DD Q - 175 <CROSS POINT<0.50 × V DD Q + 175结论：DDRII 的差分信号是伪差分，只要关注共模COMM 信号就可以，目前的波形很理想,CROSS POINT 满足器件要求。
DDR2的设计经验经典流程.
DDR2的设计经验经典流程-1发布时间: 2012-11-23 21:28:34 来源: EDA中国DDR2的设计经验经典流程EDA中国撰写一、获取设计要求参数1、DDR信号：主要分为以下5类：<1>Data线(0-63)<2>Address线(0-13)<3>Command线<4>Control线<5>CLK线(0-3)<6>电源线2．获得电气参数要求（如：阻抗要求）DDR_DQS 100欧DDR_CLK 100欧DDR_command 60欧DDR_Control 60欧DDR -_Data 60欧二、确定叠构1．从PCB加工商了解板材以及相关参数，2. 通过设计经验结合仿真工具确定最佳叠构。
确定如下叠层结构:根据数据传输特性和DATASHEET要求将DDR线分成1) DDR_command (BUS):a) M_a_a0….. M_a_a13b) M_a_bs0….M_a_bs2c) M_a_Cas#d) M_a_Ras#e) M_a_We#2) DDR_Control (BUS):a) M_cke0,M_cke1,b) M_cs#0,M_cs#1,c) M_odt0,M_odt13) DDR_DATA (8 X BUS):①DDR_D0a) M_A_DQ0…M_A_DQ7b) M_A_Dm0c) M_A_DQs0, M_A_DQs#0②DDR_D1--------⑧ DDR_D7a) M_A_DQ56…M_A_DQ63b) M_A_Dm7c) M_A_DQs7, M_A_DQs#74) DDR_CLK (DVI):①DDR_CLK0a) M_CLK_Ddr#0b) M_CLK_Ddr0②DDR_CLK1a) M_CLK_Ddr#1b) M_CLK_Ddr1将BUS和差分对分类信息输入Constraint Manager,同时参考叠构结合仿真工具和设计经验将(线宽,间距,拓扑结构等)规则参数输入Constraint Manager三、布局Constraint Manager驱动布局。
DDRII测试规范 SOP
DDRII Test SOPRD/EE:Ada_ye2009-04-24一、DDRII 簡介DDR (Dual data Rate SDRAM)SDRAM : 同步动态随机存储器，一般可作以下分类： SDR: Single Data RateDDR: Double Data Rate,2-bit prefetchDDR2: Double Data Rate,4-bit prefetchDDR3: Triple Data Rate,8-bit prefetch在我们现在做的DDR EA test 中，我们一般测试的是DDR2和DDR3,其中主要是对笔记本内存条的Clock、Command、Data做信号验证性测试。
二、DDRII Test Signal 簡介CK .CK# (Clock): CK and CK# are differentiallock inputs. All address and control input signals are sampled on the crossing of the positive edge of CKand negative edge of CK#.CKE (Clock Enable): CKE HIGH activates, andCKE LOW deactivates. CKE must be maintainedHIGH throughout read and write accesses.CS# (Chip Select): All commands are maskedwhen CS is registered HIGH. CS provides forexternal. Rank selection on systems with multipleRanks. CS is considered part of the command code. RAS# : Row Address Strobe.CAS# : Column Address Strobe .WE# : Write Enable operate .BA0 - BA2(Bank Address Inputs):BA0 - BA2define to which bank an Active.A0 - A15 :Provide the address for Activecommands.DQS. DQS# (Data Strobe) :output with read data, input with write data. Edge-aligned with read data, centered in write data.DQ (Data Input/ Output) :Bi-directional data bus.三、DDR Test Plan1. Test conditonsRun 3D Marks：2. Test toolsM/B; DDR：型号、厂商、频率的选择均按照客户要求;Scope，Probe：带宽均在被测信号频率的5倍以上(DELL要求), 3.5倍以上(其他客户要求), 。
ddr2 3布线与SI约束
Signal Integrity and PCB layout considerations for DDR2-800 Mb/s and DDR3 MemoriesFidus Systems Inc.900, Morrison Drive, Ottawa, Ontario, K2H 8K7, CanadaChris Brennan, Cristian Tudor, Eric Schroeter, Heike Wunschmann, and Syed BokhariSession # 8.13AbstractThe paper addresses the challenge of meeting Signal Integrity (SI) and Power Integrity (PI) requirements of Printed Circuit Boards (PCBs) containing Double Data Rate 2 (DDR2) memories. The emphasis is on low layer count PCBs, typically 4-6 layers using conventional technology. Some design guidelines have been provided.1. IntroductionDDR2 usage is common today with a push towards higher speeds such as 800 Mbps [1] and more recently, 1066 Mbps. DDR3 [2] targets a data rate of 1600 Mbps. From a PCB implementation standpoint, a primary requirement is delay matching which is dictated by the timing requirement. This brings into it a number of related factors that affect waveform integrity and delay. These factors are interdependent, but where a distinction can be made, they can be termed PCB layer stackup and impedance, interconnect topologies, delay matching, cross talk, PI and timing. Cadence ALLEGRO™SI-230 and Ansoft’s HFSS™ are used in all computations.Table 1: Comparison of DDR2 and DDR3 requirementsSignals common to both technologies and a general comparison of DDR2 and DDR3 is shown in Table 1. It must be noted that “matching” includes cases where the clock net may be made longer (termed DELTA in ALLEGRO SigXP). We have assumed a configuration comprising a Controller and two SDRAMs in most illustrations that follow.2. PCB Layer stackup and impedanceIn a layer constrained implementation, a 4 layer PCB (Figure 1) is a minimum with all routing on TOP and BOTTOM layers. One of the internal layers will be a solid ground plane (GND). The other internal plane layer is dedicated to VDD. Vtt and Vref can be derived from VDD. Use of a 6-layer PCB makes the implementation of certain topologies easier. PI is also enhanced due to the reduced spacing between power and GND planes. The interconnect characteristic impedance for DDR2 implementation can be a constant. A single-ended trace characteristic impedance of 50 Ohms can be used for all single-ended signals. A differential impedance of 100 Ohms can be used for all differential signals, namely CLOCK and DQS. Further, the termination resistor pulled up to VTT can be kept at 50 Ohms and ODT settings can be kept at 50 Ohms.In the case of DDR3 however, single ended trace impedances of 40 and 60 Ohms used selectively on loaded sections of ADDR/CMD/CNTRL nets have been found to be advantageous. Further, the value of the termination resistor pulled up to Vtt needs to be optimized in combination with the trace impedance through SI simulations. Typically, it is in the range 30 – 70 Ohms. The differential trace impedance can remain at 100 Ohms.Figure 1 : Four and Six layer PCB stackup3. Interconnect TopologiesIn both cases of DDR2 and DDR3, DQ, DM and DQS signals are point-to-point and do not need any topological consideration. An exception is in the case of multi-rank Dual In Line Memory Modules (DIMMs). Waveform integrity is also easily addressed by a proper choice of drive strengths and On Die Termination (ODT). The ADDR/CMD/CNTRL signals, and sometimes the clock signal will involve a multipoint connection where a suitable topology is needed. Possible choices are indicated in Figure 2 for cases involving two SDRAMs. The Fly-By Topology is a special case of a daisy chain with a very short or no stub.For DDR3, any of these topologies will work, provided that the trace lengths are minimized. The Fly-by topology shows the best waveform integrity in terms of an increased noise margin. This can be difficult to implement on a4-layer PCB and the need for a 6-layer PCB arises. The daisy chain topology is easier to implement on a 4 layer PCB. The tree topology on the other hand requires the length of the branch AB to be very close to that of AC (Figure 2). Enforcing this requirement results in the need to increase the length of the branches which affects waveform integrity. Therefore, for DDR3 implementation, the daisy chain topology with minimized stubs proves to be best suited for 4-layer PCBs.For DDR2-800 Mbps any of these topologies are applicable with the distinction between each other being less dramatic. Again, the daisy chain proves to be superior in terms of both implementation as well as SI.Where more than two SDRAMs are present, often, the topology can be dictated by constraints on device placement. Figure 3 shows some examples where a topology could be chosen to suit a particular component placement. Of these, only A and D are best suited for 4-layer PCB implementation. Again, for DDR2-800 Mbps operations all topologies yield adequate waveform integrity. For a DDR3 implementation, in particular at 1600 Mbps, only D appears to be feasible.Vtt RtRtRtTree topology Fly-By topologyFigure 2: ADDR/CMD/CNTRL topologies with 2 SDRAMS(A)Figure 3: ADDR/CMD/CNTRL topologies with four SDRAMS4. Delay matchingImplementing matched delay is usually carried out by bending a trace in a trombone shape. Routing blockage may require layer jumping. Unfortunately, while physical interconnect lengths can be made identical in layout, electrically, the two configurations shown in Figure 4 will not be the same.The case of trombone delay has been well understood, and the case of a via is obvious. The delay of a trombone trace is smaller than the delay of a straight trace of the same center-line length. In the case of a via, the delay is more than that of a straight microstrip trace of length equal to the via length. The problem can be resolved in two different ways. In the first approach, these values can be pre-computed precisely and taken into account while delay matching. This would become a tedious exercise which could perhaps be eased with userRtRtRt(B)(C)(D)Rtdefined constraints in ALLEGRO 16.0. In the second approach, one would use means to reduce the disparity to an acceptable level.Trombone traceStraight traceL 3L 2 L 4 ≠L 1L 5Figure 4: Illustration of Trombone traces and ViasFigure 5: Circuit for estimation of trombone effect and resulting waveforms.≠Straight traceVia cross sectional viewConsider the case of a trombone trace. It is known that the disparity can be reduced by increasing the length of L3 (Figure 4). Details can be found in reference [3]. A simulation topology can be set up in SigXP to represent parallel arms of a trombone trace as coupled lines. A sweep simulation is carried out with L3 (S in Figure 5) as a variable and the largest reasonable value that reduces the delay difference with respect to a reference trace is selected. For microstrip traces, L3 > 7 times the distance of the trace to ground is needed.Delay values are affected in a trombone trace due to coupling between parallel trace segments. Another way to reduce coupling without increasing the spacing is to use a saw tooth profile. The saw tooth profile shows better performance as compared to a trombone although it eventually ends up requiring more space. In either case, it is possible to estimate the effect on delay precisely by using a modified equation for the computation of the effective trace length [3]. This would need to be implemented as a user defined constraint in ALLEGRO. Consider the case of a through hole via on the 6 layer stackup of Figure 2. Ground vias placed close to the signal vias play an important role in the delay. For the illustration, the microstrip traces on TOP and BOTTOM layers are 150 mils long, and 4 mils wide. The via barrel diameter = 8 mils, pad diameter is 18 mils and the anti-pad diameter is 26 mils.Three different cases are considered. In the first case, the interconnect with via does not have any ground vias in its immediate neighborhood. Return paths are provided at the edges of the PCB 250 mils away from the signal via. In the second case, a reference straight microstrip trace of length = 362 mils is considered. The third case is the same as case 1 with four ground vias in the neighborhood of the signal via. Computed s-parameters with 60 Ohm normalization are shown in Figure 6. It can be seen that the use of 4 ground vias surrounding the signal via makes its behavior more like a uniform impedance transmission line and improves the s21 characteristic. In the absence of a return path in the immediate neighborhood, the via impedance increases. For the present purpose, it is important to know the resulting impact on the delay.A test circuit is set up similar to Figure 5. The driver is a linear source of 60 Ohms output impedance and outputs a trapezoidal signal of rise time = fall time = 100 ps and amplitude = 1V. It is connected to each of the 3 interconnects shown in Figure 6 and the far end is terminated in a 60 Ohm load. The excitation is a periodic signal with a frequency of 800 MHz. The time difference between the driver waveform at V = 0.5 V and the waveform at the receiver gives the switched delay.Results are illustrated in Figure 7 where only the rising edge is shown. It can be seen that the delay with four neighboring ground vias differs from that of the straight trace by 3 ps. On the other hand, the difference is 8 ps for the interconnect with no ground vias in the immediate neighborhood.It is therefore clear that increasing the ground via density near signal vias will help. However, in the case of 4 layer PCBs, this will not be possible as the signal traces adjacent to the Power plane will be referenced to a Power plane. Consequently, the signal return path would depend on decoupling. Therefore, it is very important that the decoupling requirement on 4 layer PCBs addresses return paths in addition to meeting power integrity requirements.The clock net is differential in both DDR2 and DDR3. In DDR2, DQS can be either single ended or differential although it is usually implemented as differential at higher data rates. The switched delay of a differential trace is less than that of a single ended trace of identical length. Where timing computations indicate the need, the clock and DQS traces may need to be made longer than the corresponding ADDR/CMD/CNTRL nets and DATA nets. This would ensure that the clock and DQS transitions are centered on the associated ADDR/CMD/CNTRL nets and DQ nets.Since DQ and DM nets run at the maximum speed, it is desirable that all of these nets in any byte lane be routed identically, preferably without vias. Differential nets are less sensitive to discontinuities and where layer jumping is needed, the DQS and CLOCK nets should be considered first.Figure 6: s-parameters of interconnects with vias (60 Ohm normalization)Figure 7: Driver and Receiver waveforms for the 3 cases of Figure 6. (Plot colors correspond)5. CrosstalkCross talk contributes to delay uncertainty being significant for microstrip traces. This is generally reduced by increasing the spacing between adjacent traces for long parallel runs. This has the drawback of increasing the total trace length and therefore a reasonable value must be chosen. Typically the spacing should be greater than twice the trace distance to ground. Again, ground vias play an important role. Near and far end coupling levels are illustrated in Figure 8. Use of multiple ground vias reduces coupling levels by 7 dB. To derive the interconnect budget, a simulation of a victim trace with two aggressors on both sides is adequate. Using a periodic excitation on all nets will yield the cross talk induced jitter. Using a pseudo random excitation on all nets will show the effect of both cross talk as well as data dependencies. Time domain results are not shown here, but it is easily done by setting up a 5 coupled line circuit in SigXP with the spacing between traces set up for sweeping. Reasonable spacing values that keep the jitter in the waveform due to both cross talk as well as pattern dependence at an acceptable level are chosen.Figure 8: s-parameters of coupled traces (60 Ohm normalization)6. Power IntegrityPower Integrity here refers to meeting the Power supply tolerance requirement under a maximum switching condition. Failure to address this requirement properly leads to a number of problems, such as increased clock jitter, increased data dependent jitter, and increased cross talk all of which eventually reduce timing margins.The theory for decoupling has been very well understood and usually starts with the definition of a “target impedance” as [4]CurrentTransient tolerance Voltage Z et t =arg (1)An important requirement here is knowledge of the transient current under worst case switching condition. A second important requirement is the frequency range. This is the range of frequencies over which the decoupling network must ensure that its impedance value is equal to or below the required target impedance. On a printed circuit board, capacitance created by the Power-Ground sandwich and the decoupling capacitors needs to handle a minimum frequency of ~100 kHz up to a maximum frequency of ~100-200 MHz. Frequencies below 100 kHz are easily addressed by the bulk capacitance of the voltage regulator module. Frequencies above 200 MHz should be addressed by the on-die and in some cases on-package decoupling capacitance. Due to the finite inductance of the package, there is no need to provide decoupling on the PCB to handle frequencies greater than 200 MHz. The actual computation of power integrity can be very complex involving IC package details, simultaneously switched signals and the PCB power distribution network. For PCB design, the use of the target impedance approach to decoupling design is simpler and provides a practical solution with very little computational effort.The three power rails of concern are the VDD, VTT and Vref. The tolerance requirements on the VDD rail is ~ 5% and the transient current is determined as the difference between Idd7 and Idd2 as specified by JEDEC [1,4]. This is accomplished by using plane layers for power distribution and a modest number of decoupling capacitors. It is preferable to use decoupling capacitors of 10 different values distributed in the range of 10 nF to 10 uF. Further, the capacitor pad mounting structure should be designed for reduced mounted inductance.The Vref rail has a tighter tolerance, but it draws very little current. Its target impedance is easily met using narrow traces and one or two decoupling capacitors. It is important however that the capacitors be located very close to the device pins.The VTT rail proves to be challenging because it not only has a tighter tolerance, but it also draws a transient current close to that of the VDD rail. The transient current is easily calculated as described in reference [5]. Again, the target impedance requirement can be met using an increased number of decoupling capacitors.On a 4 layer PCB, the planes are too far apart and consequently the advantage of inter-plane capacitance is lost. The number of decoupling capacitors needs to be increased and higher frequency capacitors with values less than 10 nF may be needed. These computations are easily done using ALLEGRO SI Power Integrity option.7. TimingTiming computation is carried out as described in reference [6]. A table needs to be setup for the following eight cases: 1. 2. 3. 4. 5. 6. 7. 8. Write Setup analysis DQ vs. DQS Write Hold analysis DQ vs. DQS Read Setup analysis DQ vs. DQS Read Hold analysis DQ vs. DQS Write Setup analysis DQS vs. CLK Write Hold analysis DQS vs. CLK Write Setup analysis ADDR/CMD/CNTRL vs. CLK Write Hold analysis ADDR/CMD/CNTRL vs. CLKAn example is shown for the case of Write setup analysis in Table 2. Actual numbers have been omitted as they are not precisely known yet for DDR3. These numbers are obtained from data sheets of Controller and memory manufacturers. The numbers in the interconnect section are determined by SI simulations. All the eight cases need to be analyzed for DDR2. For DDR3, 5 and 6 are not needed due to its write leveling feature. In the PCB implementation, length match tolerances must ensure that the total margin is positive. ElementControllerSkew Componenta.)DQ vs. DQS skew at transmitter output b.) Data / Strobe PLL jitter a+b Setup requirement (tDSb @ Vih/Vil level) DQ slew rate DQS slew rateSetupUnitsps ps ps psCommentsFrom controller design data Used if not included in transmitter skewTotal Controller SDRAM (or DIMM)V/ns V/ns psTotal SDRAM setup requirement InterconnecttDSb + slew rate adjustmentFrom SDRAM datasheet; this number is to be adjusted based on DQ and DQS slew rates Measured as per JEDEC specification from SI simulation results Measured as per JEDEC specification from SI simulation results Includes slew rate adjustmenta.) Data Xtalk b.) DQS Xtalk c.) Length matching tolerance d.) Characteristic impedance mismatch Total Interconnect Min. Total Setup Budget Setup margin Interconnect skew (a + b + c + d) 0.24*tckps ps ps ps2 aggressors (one each side of the victim); victim – repetitive; aggressor- PRBS 2 aggressors (one each side of the victim); victim – repetitive; aggressor- PRBS Extracted from SI simulation results longest data net, worst case PVT corner can be omitted if routing of DQ and corresponding DQS signals are done on same layerps ps From SDRAM datasheet (includes clock duty cycle variation) Must be positiveMin. Total Setup Budget – (Total Controller + Total SDRAM + Total Interconnect )psTable 2: Illustration of DDR3 Write Setup timing analysis summary for DQ vs. DQS8. PCB LayoutImplementation on a PCB involves a number of tradeoffs to meet SI requirements. Often, the question is how far does one need to go? PCB layout tasks are facilitated using the following approach: 1. Set up topology and constraints in ALLEGRO Constraint Manager. 2. Design Controller BGA breakout. A controller pin arrangement with ADDR/CMD/CNTRL pins in the middle and DQ/DQS/DM byte lanes on either side is best suited. Within these groups, individual pins may need to be swapped to ensure routing with minimum cross-over. 3. Attempt routing with reduced stub length and a minimum trace spacing as obtained from cross talk simulation. Often, most stubs can be eliminated but it will not be possible for all the pins. One may try two traces between BGA pads of the memory devices. This would require narrow PCB traces which can increase manufacturing cost. Yet, it will not be possible for all signals unless micro via and via-in-pad technology is used. Complete routing with coarse length matching tolerances. 4. Place Vref decoupling capacitors close to the Vref pins. Vtt decoupling can be placed at the far end of the last SDRAM and will not come in the way of routing. VDD decoupling can be placed close to devices where possible without blocking routing channels. The smaller valued capacitors should be placed closer to the devices. With a proper decoupling design, it will not be necessary to cram all capacitors close to the devices. All decoupling capacitors should use a fan out for the footprint designed for reduced inductance. This is typically two short wide traces perpendicular to the capacitor length. This can be automated by using a user defined capacitor footprint that can be attached to all the decoupling capacitors in the schematic. 5. Implement fine length matching and insert multiple ground vias where signal traces jump layers. It is better to use the delay matching option in ALLEGRO and one must include z-axis delay. Typically, P and N nets of differential pairs should be matched with a tolerance of +/- 2ps and the tolerance for all other matched nets can be +/- 10 ps or more based on the timing margin computation.9. DIMMConsiderations described above apply to the case of PCBs containing one or more DIMMs. The only exception is that the decoupling requirement for the memories can be relaxed as it is already accounted for on the DIMM PCB. SI analysis of registered DIMMs is also much simpler where the DIMM is treated as a single load. While the routing topology for ADDR/CMD/CNTRL nets is usually a daisy chain with reduced stubs, tree topologies can also be used for registered DIMMs. Analysis of un-buffered DIMMs can become tedious as the timing requirement at all the SDRAMs must be analyzed. DIMM routing on 4-layer PCBs is relatively simpler compared to the case of SDRAMs.10. ExamplesThe detail described above has been used in the implementation of a DDR2 PCB, a DDR3 PCB and a DDR3 – DIMM PCB. The controller is from MOSAID [7] which is designed to provide both DDR2 as well as DDR3 functionality. For the SI simulations, IBIS models have been used. Models for the memories are from MICRON Technology, Inc [8]. The IBIS models for the DDR3 SDRAMs were available at 1333 Mbps speed. These were used at 1600 Mbps. For the unbuffered DDR3 DIMM (MT_DDR3_0542cc) EBD models from Micron Technology were used. All waveforms are for the typical case and are computed at the SDRAM die. The 6 layer PCB stackup of Figure 2 is used with routing on TOP and BOTTOM layers only. The memory consists of 2 SDRAMsrouted as a daisy chain. In the case of the DIMM, a single unbufferred DIMM is used. TOP/BOTTOM layer routing and Signal Integrity waveforms are shown in Figures. 9-11.Snapshots ofFigure 9: Illustration of TOP and BOTTOM layers of a DDR3 PCB with computed waveforms at the farthest SDRAM. Waveform on left is an ADDRESS net compared to that of the CLOCK net. Waveform on the right is a DATA net compared to that of a DQS net. Clock frequency = 800 MHz and data rate is 1600 Mbps.Figure 10: Illustration of TOP and BOTTOM layers of a DDR2 PCB with computed waveforms at the farthest SDRAM. Waveform on left is an ADDRESS net compared to that of the CLOCK net. Waveform on the right is a DATA net compared to that of a DQS net. Clock frequency = 400 MHz and data rate is 800 Mbps.Figure 11: Illustration of TOP and BOTTOM layers of a DDR3 – DIMM PCB with computed waveforms at the 8th (last) SDRAM on DIMM. Waveform on left is an ADDRESS net compared to that of the CLOCK net. Waveform on the right is a DATA net compared to that of a DQS net.Lastly, Figure 12 shows a comparison of computed and measured DATA eye patterns of an 800 Mbps DDR2. In all cases waveform integrity can be seen to be excellent.Figure 12: Computed (Red) and Measured (blue) waveforms of a data net of an 800 Mbps DDR2 PCB.11. ConclusionIn this paper, all aspects related to SI, and PI of DDR2 and DDR3 implementation have been described. Use of Constraint Manager in ALLEGROTM makes implementation easy. While a four layer PCB implementation of 800 Mbps DDR2 and DDR3 appears to be feasible, DDR3-1600 Mbps will prove to be challenging. It will become clearer as the memory devices become available and one has a good handle on timing numbers.References[1] DDR2 SDRAM Specification, JEDEC JESD79-2B, January 2005. [2] DDR3 SDRAM Standard, JEDEC JESD79-3, June 2007. [3] Syed Bokhari, “Delay matching on Printed Circuit Boards”, Proceedings of the CDNLIVE 2006, San Jose. [4] Larry D Smith, and Jeffrey Lee, “Power Distribution System for JEDEC DDR2 memory DIMM, Proc. IEEE EPEP conference, Princeton, N.J., pp. 121-124, October 2003. [5] Hardware and layout design considerations for DDR2 SDRAM Memory Interfaces, Freescale semiconductor Application Note, Doc. No. AN2910, Rev. 2, 03/2007. [6] DDR2 design guide for 2 DIMM systems, Technical Note, Micron Technology Inc. TN-47-01, 2003. [7] /corporate/products-services/ip/SDRAM_Controller_whitepaper_Oct_2006.pdf [8] /products/dram/ddr2/partlist.aspx?speed=DDR2-800 [9] /products/dram/ddr3/partlist.aspx?speed=DDR3-1066。
使用AllegroPCBSI应对DDR的挑战
5
预取(Pre-fetch)架构
?预取架构可以在不增加内核频率的情况下提高外部数据传输率 ?是DDR3和其他DDR/SDR内存的关键区别
Core 133MHz DDR3
Memory Array
Core 133MHz DDR2
Memory Array
Core 133MHz DDR
Memory Array
?补偿因fly-by拓扑带来的数据选通对于时钟的时序偏移
12
议题
? DDR3的简介 ? DDR3设计的主要挑战 ? Cadence PCB SI设计流程 ? 前仿真和规则设置 ? 规则驱动设计 ? 后仿真验证 ? Cadence PCB SI 16.5版本的新功能
? 答疑
13
DDR3设计的主要挑战
Core 133MHz SDR
Memory Array
Ex Clock 533MHz I/O
Buffer
Ex Clock 266MHz I/O
Buffer
Ex Clock133MHz I/O
Buffer
Ex Clock133MHz I/O
Buffer
Data Rate 1066Mbps
Data Rate 533Mbps
7
ODT和动态ODT
?ODT (On-Die Termination) 将匹配内置到芯片中，以提高数据总线的信号质量 ?动态ODT能够进一步提高DDR3数据总线的信号质量，特别是在多个负载例如 双内存条系统中
8
DDR3的动态ODT
? 什么是动态ODT
– 在读写切换时，DDR3内存会在原始ODT和动态ODT做对应的切换。也 就是说，当读取或空闲时，ODT的值会是 20, 30, 40, 60, 120 ohm 之 一（由EMR配置）；而写入时会切换至60或120ohm（由EMR配置）
DDR2设计原则(Altera&Freescale)
徐聪翻译整理的Altera手册本应用笔记提供了在连接Altera FPGA器件和DDR2 SDRAM器件时需要使用的Altera推荐的终结电路图。
然而，你还是应该通过对自己的设计进行仿真来得到针对你的设计最适合终结电路图，这是非常重要的。
本应用笔记也提供了仿真结果与实验测得的结果之间的比较，以便你能够自己总结出对于实现最佳信号质量的最佳设计方法。
对于终结电路的设计，Altera推荐使用接收器端的并联终结电阻来达到最佳的信号质量。
因此，对于双向信号，例如数据线DQ或数据选通脉冲DQS，推荐使用的终结电路形式是Class II方式。
你可以采用在FPGA一边和内存一边外接并联电阻或者启用内存的ODT功能和FPGA的OCT功能，或者组合使用DDR2 SDRAM的ODT功能和在FPGA一侧放置终结电阻，对于一个单向的信号，例如命令线或地址线，推荐的终结方式是Class I方式，在这种方式下终结电阻放置在内存一边。
选择何种FPGA的输出能力选项取决于采用何种终结方式——Class I或Class II——但是根据仿真结果显示，你应当将输出能力设置为与输出驱动器“看到”的负载相匹配的值。
对于Class II终结方式，Altera 推荐使用的输出能力设置为25ΩOCT。
这种设置能实现最好的结果，因为输出驱动器的输出阻抗与输出驱动器看到的阻抗相匹配。
而当采用Class I终结方式时，Altera推荐使用50ΩOCT 输出能力设定。
此外，本应用指南描述了不同的内存负载形式对于信号质量的影响。
从前文“单/双内存条对比”中可知，高负载值会降低信号的上升速度，延长信号的上升时间，因此会缩小接收端可以看到的信号读取窗口（“眼”）的宽度。
你可以通过提高输出能力设定来提高信号的上升速度，但是这回降低输出驱动器的阻抗造成阻抗不匹配。
最后，本应用指南给出了DDR2布局布线指导。
虽然本应用指南中的推荐方法是由仿真结果和在Stratix III 主机开发板与Stratix II内存电路板2上的实验结果基础上给出的，但对于任何其他的电路板，你可以应用同样的基本原理来确定最佳的终结方式、驱动能力设置和负载形式。
DDR2知识
h t t p://www.me mo ry te st.c om.cnDDR2内存技术当前的处理器主频和I/O带宽都很高，需要内存提供很高的数据传输率来配合。
要知道内存带宽至少要和前端总线带宽同步，这样才不至于影响处理器性能的发挥。
而且处理器的速度提升还在不断的进行中，内存需要每秒钟提供更多的数据来满足处理器的要求。
目前的内存速度提升已经相当困难，这时候转变到DDR2不失为合理的时机，它提供了一条提高内存带宽的康庄之道，可以缓解当前遇到的很多问题。
提高内存性能的两个途径内存的性能通过下面的公式来计算：速度=位宽×频率速度用来表示内存的性能(MB/s)，位宽是指内存总线的宽度(bit)，频率当然就是指数据传输的频率，注意，这里说的是数据传输的频率，而不是内存的工作频率，在DDR时代，数据传输频率是内存工作频率的二倍。
因此，提高性能有两种方式，增加内存总线的位宽或者是提高内存工作的频率。
好的，让我们来看看内存如今的状态是怎么样。
虽然内存发展出很多的类型，但是它们都是基于原始的DRAM单元，实际上，它是一个晶体管和一个电容的结合体，很简单但也很高效。
有很多尝试希望丢弃这种阵旧的以晶体管为基础的存储方式，出现了一些新的存储技术，如MRAM(Magnetoresistive RAM)，FRAM (Ferroelectric RAM)等，但是它们都没有获得足够的成功。
没有其它内存类型能够提供一个和DRAM相似的，结合了容量，价格和速度的解决方案。
当然还有很多快速的基本单元结构，象静态内存(SRAM)，它不象动态内存那样需要刷新(预充电)，但是它的每个存储单元耗用了大量的晶体管，它太贵太大了，因此内存芯片不能够达到足够大的容量，还有一些廉价的解决方案，但是它们的性能无法用于PC的主内存系统。
换句话说，基本的DRAM架构仍然是现代内存类型的基础，因此，所有的现代内存类型都继承了DRAM的优点和缺点：它需要刷新(预充电，不然随着漏电，DRAM中的数据会消失)，以及有操作频率的上限(这也是用电容充电来存储数据的弊病)。
DDR2设备的布局布线准则
DSP的DDR2布局布线准则文：曹永涛目次1. PCB叠层设计 (1)2. 阻抗匹配 (2)3. 布局 (2)4. DDR2的禁止布线区域设置及要点 (2)5. 低频分离旁路电容的布置 (3)6. 高频分离旁路电容的布置 (3)7. 时钟线和信号线 (4)8. VREF的布线 (4)9. CK时钟和ADDR_CTRL的走线拓扑与规则 (5)10. DQS和DQ的布线拓扑与规则 (6)11. DQGATE的走线拓扑与规则 (7)DSP的DDR2布局布线准则相比其它器件，DDR2设备在布局布线方面有其特殊性。
TI公司通过仿真设计及对EVM板的EMI测试，明确了其DSP产品与DDR2设备接口布局布线的准则。
我们可以直接照搬EVM板在DDR2处的布局布线，也可以按下面的准则灵活设计。
此文也可作其它控制器的DDR2设备接口部分布局布线的参考。
1. PCB叠层设计在DDR2的布局布线中，叠层最少设计为6层，为节省空间或其它电路有需要的话，可增加叠层。
叠层设计要求如下表：2. 阻抗匹配阻抗匹配分为源端匹配和终端匹配。
地址线和控制线为源端匹配（控制器端），数据线为终端匹配（存储器端）。
nDSDDQM0，nDSDDQM1，nDSDDQM2，nDSDDQM3采用源端匹配。
具体如下表：3. 布局DDR2控制器与DDR2设备的布局关系表示如图：图中：X最大值为1660MILS；Y最大值为1280MILS；Y偏移最大值为650MILS。
（注：所有数据均以器件中心为测量基点。
）4. DDR2的禁止布线区域设置及要点在DDR2的布局布线区域有其特殊性，先将这个区域称为DDR2的禁止布线区域，其位置设置大致如下图：布线要点：A．所有与DDR2相关的电路均必须布局布线在此区域；B．非DDR2电路、信号线不能在此区域内与DDR2信号线同层布线；C．非DDR2信号线在此区域布线时，必须与DDR2信号线布线层以完整地平面隔开；D．此区域的地平面与电源平面无分割，电源平面必须覆盖全区域。
DDR2,SO-DIMM,笔记本内存管脚定义
DDR2,SO-DIMM,笔记本内存管脚定义Pin Type SigNoise Model Net--- ---- -------------- ---1 UNSPEC VREF2 UNSPEC VREF3 UNSPEC GND4 UNSPEC GND5 UNSPEC DQ06 UNSPEC DQ47 UNSPEC DQ18 UNSPEC DQ59 UNSPEC VCC10 UNSPEC VCC11 UNSPEC DQS012 UNSPEC DM013 UNSPEC DQ214 UNSPEC DQ615 UNSPEC GND16 UNSPEC GND17 UNSPEC DQ318 UNSPEC DQ719 UNSPEC DQ820 UNSPEC DQ1221 UNSPEC VCC22 UNSPEC VCC23 UNSPEC DQ924 UNSPEC DQ1325 UNSPEC DQS126 UNSPEC DM127 UNSPEC GND28 UNSPEC GND29 UNSPEC DQ1030 UNSPEC DQ1431 UNSPEC DQ1132 UNSPEC DQ1533 UNSPEC VCC34 UNSPEC VCC35 UNSPEC CK0T36 UNSPEC VCC37 UNSPEC CK0B38 UNSPEC GND39 UNSPEC GND40 UNSPEC GND41 UNSPEC DQ1642 UNSPEC DQ2043 UNSPEC DQ1744 UNSPEC DQ2145 UNSPEC VCC46 UNSPEC VCC47 UNSPEC DQS248 UNSPEC DM249 UNSPEC DQ1850 UNSPEC DQ2251 UNSPEC GND52 UNSPEC GND53 UNSPEC DQ1954 UNSPEC DQ2355 UNSPEC DQ2456 UNSPEC DQ28VCC58 UNSPEC VCC59 UNSPEC DQ2560 UNSPEC DQ2961 UNSPEC DQS362 UNSPEC DM363 UNSPEC GND64 UNSPEC GND65 UNSPEC DQ2666 UNSPEC DQ3067 UNSPEC DQ2768 UNSPEC DQ3169 UNSPEC VCC70 UNSPEC VCC71 UNSPEC CB072 UNSPEC CB473 UNSPEC CB174 UNSPEC CB575 UNSPEC GND76 UNSPEC GND77 UNSPEC DQS878 UNSPEC DM879 UNSPEC CB280 UNSPEC CB681 UNSPEC VCC82 UNSPEC VCC83 UNSPEC CB384 UNSPEC CB785 UNSPEC87 UNSPEC GND88 UNSPEC GND89 UNSPEC CK2T90 UNSPEC GND91 UNSPEC CK2B92 UNSPEC VCC93 UNSPEC VCC94 UNSPEC VCC95 UNSPEC CKE196 UNSPEC CKE097 UNSPEC A1398 UNSPEC BA299 UNSPEC A12 100 UNSPEC A11 101 UNSPEC A9 102 UNSPEC A8 103 UNSPEC GND 104 UNSPEC GND 105 UNSPEC A7 106 UNSPEC A6 107 UNSPEC A5 108 UNSPEC A4 109 UNSPEC A3 110 UNSPEC A2 111 UNSPEC A1 112 UNSPEC A0 113 UNSPEC VCC 114 UNSPEC VCC 115 UNSPEC A10116 UNSPEC BA1117 UNSPEC BA0 118 UNSPEC RAS 119 UNSPEC WE 120 UNSPEC CAS 121 UNSPEC S0 122 UNSPEC S1 123 UNSPEC124 UNSPEC125 UNSPEC GND 126 UNSPEC GND 127 UNSPEC DQ32 128 UNSPEC DQ36 129 UNSPEC DQ33 130 UNSPEC DQ37 131 UNSPEC VCC 132 UNSPEC VCC 133 UNSPEC DQS4 134 UNSPEC DM4 135 UNSPEC DQ34 136 UNSPEC DQ38 137 UNSPEC GND 138 UNSPEC GND 139 UNSPEC DQ35 140 UNSPEC DQ39 141 UNSPEC DQ40 142 UNSPEC DQ44 143 UNSPEC VCC 144 UNSPEC VCC145 UNSPEC DQ41 146 UNSPEC DQ45 147 UNSPEC DQS5 148 UNSPEC DM5 149 UNSPEC GND 150 UNSPEC GND 151 UNSPEC DQ42 152 UNSPEC DQ46 153 UNSPEC DQ43 154 UNSPEC DQ47 155 UNSPEC VCC 156 UNSPEC VCC 157 UNSPEC VCC 158 UNSPEC CK1B 159 UNSPEC GND 160 UNSPEC CK1T 161 UNSPEC GND 162 UNSPEC GND 163 UNSPEC DQ48 164 UNSPEC DQ52 165 UNSPEC DQ49 166 UNSPEC DQ53 167 UNSPEC VCC 168 UNSPEC VCC 169 UNSPEC DQS6 170 UNSPEC DM6 171 UNSPEC DQ50 172 UNSPEC DQ54 173 UNSPEC GND 174 UNSPECGND175 UNSPEC DQ51 176 UNSPEC DQ55 177 UNSPEC DQ56 178 UNSPEC DQ60 179 UNSPEC VCC 180 UNSPEC VCC 181 UNSPEC DQ57 182 UNSPEC DQ61 183 UNSPEC DQS7 184 UNSPEC DM7 185 UNSPEC GND 186 UNSPEC GND 187 UNSPEC DQ58 188 UNSPEC DQ62 189 UNSPEC DQ59 190 UNSPEC DQ63 191 UNSPEC VCC 192 UNSPEC VCC 193 UNSPEC SDA 194 UNSPEC SA0 195 UNSPEC SCL 196 UNSPEC SA1 197 UNSPEC VCCSPD 198 UNSPEC SA2 199 UNSPEC200 UNSPEC。
DDR2程序设计方案
DDR2程序设计方案程序设计目标实现DDR2的读写功能，并且读写正常。
程序设计思路考虑到直接写DDR2读写时序有困难，所以使用DDR2 IP核。
调用DDR2 IP核，并且为DDR2 IP核生成相应的时钟，根据模块化思想，将读写操作进行封装成模块，在顶层模块为读写模块提供地址与数据。
程序具体设计根据以上思路需要做到以下几点：1)生成DDR2 IP核2)基于DDR核的读写模块3)顶层模块设计4)使用PLL生成时钟DDR2 IP核的生成过程打开核生成器创建一个新的工程根据工程需要指定工程路径，并且给工程取名。
点击Part选择芯片型号，点击Generation选择语言，点击ok。
找到mig核，并双击，进入DDR2核生成过程。
进入DDR2 IP核的配置界面，核对建立工程时的信息，点击下一步重新定义”Component Part”，点击下一步点击下一步选择DDR2_SDRAM，点击下一步设置时钟为200M，数据位宽为16点击此页的”Creat Custom Part”，设置器件名称为k4t1g164qf，此名称可以自由定义并作为DDR2芯片名，在最下方根据芯片手册选择相应的列地址，行地址以与BANK地址，点击保存，回到之前的页面，点击下一步选择”Burst Length”为4，点击下一步“System Clock”选择”Single-Ended”，单端时钟比较好操作，点击下一步。
接下来是DDR2引脚的配置，此时的配置需要明确DDR2在FPGA上的引脚，同时这一步也是检验DDR2引脚在FPGA上分配是否正确的方法。
选择”Fixed Pin Out:...”这一选项，点击下一步将FPGA的引脚标识添加到对应DDR2信号名称的引脚上。
多余引脚，先找一些无用的引脚填上，之后再修改ucf文件即可。
如果ucf已经存在，也可以使用”ReadUCF”来进行加载，如果引脚有不正确的分配，进行”Valide”时会提示错误。
如果无错误，点击下一步点击下一步选择”Accept”，点击下一步，之后一直点击下一步，直到最后点击”Generate”，生成DDR2 IP核。
AltiumDDRII_SDRAM_的等长布线整理
Altium Designer 中DDRII SDRAM 的等长布线/icview-217610-1-1.html如图所示，以ARM，DSP等SOC为核心的电子系统中，经常存在两片或者以上的DDR/DDRII SDRAM。
考虑到DDR/DDRII SDRAM的运行频率一般都比较高，在做PCB layout的时候需要等长布线来保证DDR/DDRII SDRAM的读写时序。
对于包含两片及以上DDR/DDRII SDRAM的系统，这里要求的等长布线有两层含义。
拿ADDRESS信号来讲，第一层含义要求从SOC的某一个ADDRESS的pad到每一块儿DDR/DDRII SDRAM对应的pad之间的长度要相等（A+B = A+C），第二层含义要求SOC的所有ADDRESS的pad到对应DDR/DDRII SDRAM的pad之间的长度要相等（所有的A+B = 所有的A+C）。
但在Altium Designer中，SOC的某一ADDRESS pad与对应DDR/DDRII SDRAM的pad之间的网络定义是唯一的（也就是A，B，C拥有同样的网络名称），网络的长度定义为（A+B+C），无法准确知道A，B和C的长度。
那如何在Altium Designer中实现DDR/DDRII SDRAM的等长布线呢？下面以一个项目中DRAM_A0 ~ A3四根信号线的等长设计为例，介绍在Altium Designer中实现DDRII SDRAM的等长布线。
U23为CPU，U7和U8为两片DDRII SDRAM。
DRAM_A0 ~ A3为低四位地址信号。
下面以一个项目中DRAM_A0 ~ A3四根信号线的等长设计为例，介绍在Altium Designer中实现DDRII SDRAM的等长布线。
U23为CPU，U7和U8为两片DDRII SDRAM。
DRAM_A0 ~ A3为低四位地址信号。
一，在From-To Editor中定义DRAM_A0 ~ A3的From To。
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Allegro PCB SI SOP For DDR2_VLP_RDIMM
開始>程式集>PCB SI
1.進入PCB SI 後, 在其工作列選擇Tools> setup advisor, 會出現database setup advisor的畫面,
如圖所示。
Fig 1. Setup advisor編輯畫面
2.點選Next選項,之後會出現Edit cross-section文字框的畫面(如圖二所示),點選Edit
cross-section字框後,即可進入PCB板結構的編輯畫面(如圖三所示),我們再依照板廠所提供的stackup 將PCB板各層的厚度及材料參數(介電係數, Loss Tangent, 阻抗值等)一一鍵入即可完成PCB板編輯,完成後點選ok,則回到圖二畫面。
Fig 2.Edit cross-section 畫面
3. 在圖二畫面中點選Next 選項, 進入DCNet 的編輯框(如圖四所示)
點選Identify DCNets, 進入DCNets 後, 將所有DC 值列出(如圖5所示)，若須修改則在圖5中左邊對話框中，點選欲修改的選項，之後在右邊的(Net selected)框中，將欲修改之DC 值填入，之後按DC Net 的設定，之後按Device Setup 。
Fig 3.PCB cross-section 編輯
Fig 4. DCNets
進入Device setup 畫面(Fig. 6)後，按下(Fig. 7)，在此case 中，我們將Resistor Pack 的名稱由RN*改成Fig. 6畫面，，進入SI Model 設定。
Fig. 5 DC Net setup
Fig. 6 Device setup
進入SI Model 設定後(如Fig. 8
SI Model 設定的畫面(如Fig. 9)後，我們開始將各個元件所屬的Model 掛上
Fig. 8 SI Model Assignment
Fig. 9 SI Model Setup
首先將Register IBIS, DRAM IBIS, PLL IBIS分別掛上(在此我們以DRAM為例,加以說明)
Step 1: 將.ibs之IBIS模型轉成Candence可判讀的.dml格式
首先在功能列中，找到Analyze，點選Analyze後找到SI/EMI Sim選項，再點選該選項找到Library選項(如圖10所示)(Analyze→SI/EMI Sim→Library)
Fig. 10
然後點選Library進入Signal Analyze Library 畫面(如圖11所示)
Fig. 11
點選translate 後選擇ibis2 signoise進入圖12之畫面選擇IBIS來源檔案，點選wright1.ibs後，按開啟則會進入圖13畫面此為將ibs轉換為dml的translation command 接著按OK即得到wright.dml，之後再將DRAM 的IBIS model掛上，即可定義DRAM的元件特性。
Step 2.將model 掛上所屬的元件(我們採用Register 為例作說明)，首先在元件庫中找到Register(U11)後(如圖14所示)，點選Find Model 後則會出現Model Browser
Fig. 12 Select IBIS source files Fig. 14 model assignment
(如圖15)，之後在Model type Filter欄位中選擇IbisDevice且將Model Name Pattern改為＊.,則在下方文字框中會出現所有IbisDevice Model點選Register的Model後，點選close將視窗關閉，則Register IBIS Model 會掛上，之後按OK離開Signal Model Assignment 對話框，之後按Finish即可完成Step advisor
Fig. 15 model browser
被動元件model之建立
Step 1. 進入Allegro後，在工作列上選取Analyze後，選取SI/EMI Sim後，進入Library之後會出現Device Library Files的對話框，點選device.dml (點二下)，如圖16所示。
Fig. 16 signal analysis library
進入model browser點選任一個元件模型後，在點選Add Model(如圖17所示)
Fig. 17 model browser
點選Add Model後再點選Clone Selection(如圖18所示)之後會出現鍵入新元件名稱的對話框
Fig. 18
然後Key in新的元件名稱(example: Resistor)之後click OK，則出現new device model name (在此為Resistor)，如圖19所示。
Fig. 19 new device model
點選新建立的元件model(在此為Resistor)如圖20所示，則會出現device model 的內容，將其阻值修改後，按下save，即可完成建立新元件的model。
修改阻值
Fig. 20元件model內容
若欲建立新的電容或電感等被動元件之model則重覆上述方法即可。
完成Model Setup後，須再check PLL & Register & Connector pin type 避免在load model 時發生Pin 腳的訊號產生錯誤，首先回到Signal Model Assignment畫面(Fig. 14)，之後在點選RefDesPins即可進入每一個IC的定義，我們分別點選U4及U11兩顆IC進入其Pin腳的定義(如圖21所示)check Pin腳的signal是否正確，若不正確須做修改，修改步驟如下：
1.回到SI 主畫面(如圖22所示)，點選Logic後點選
Pin type 修改畫面(如圖
23所示)。
2.
將欲修改之Pin 腳signal 修改後按
Fig. 21 IC Pin type Fig. 22 SI主畫面
Fig. 23 Pin type修改
接下來開始PCB 板的模擬，首先設定分析的條件
1. 點選Analyze>SI/EMI Sim>Preference 進入DeviecModels ，勾選Use Default for Missing Components
Models(如圖24所示)
2. 接下來點選Interconnect Models 進入Via Modeling Setup (如圖25所示)選擇
接下來開始模擬訊號，首先點選Analyze>SI/EMI Sim>Probe
Fig. 24 Device Models
Fig. 25Interconnect Models
若須Simulation setup time and hold time 須設定BUS
Setup time/Hold time
Source Synchronous Bus Analysis
1.Go to Analyze>SI/EMI Sim>Bus Setup.
2.Click “Create Simulation Bus” button to verify
3. Select Clocks or Strobes
4. Assign Bus Xnexts to Clocks or Strobes
5. Assign Bus Stimulus
6. Go to Analyze > SI/EMI Sim > Bus Simulate
Function generator will be put on golden finger.。