上菲红：Cursor 9胜在性能良好
猎鹰9号火箭用户指南falcon9 usersguide rev 2.0
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Falcon User’s Guide 5.2 Electrical Interfaces 5.2.1 Connectivity during Payload Processing and on Launch Pad 5.2.2 Falcon-to-Payload Command Interface 5.2.3 Timing Services Interface Compatibility Verification Requirements 37 37 39 40 40 41 41 41 43 44 46 47 47 48 48 48 49 50 51 53 53 53 54 57 58 58 59 59 60 60 60 61 61 61 61 61 61 62 6TABLE OF CONTENTS
1. Introduction 1.1 User’s Guide Purpose 1.2 Company Description 1.3 Falcon Program Overview 1.4 Falcon Launch Vehicle Safety 1.5 Falcon Reliability 1.6 Pricing Vehicles 2.1 2.2 2.3 2.4 2.5 Falcon 9 Vehicle Overview Structure and Propulsion Retention, Release and Separation Systems Avionics, and Guidance, Navigation and Control Coordinate Frame 5 5 5 6 6 7 9 10 10 10 12 12 12 14 14 14 15 16 16 16 16 17 17 18 18 18 19 19 21 23 26 27 30 31 32 32 34 34 34 36
IEEE 1394 火线接口的设计
``FWDG 1.0TA03/02/2010 FireWire Design GuideAbstract: Guidelines for implementing FireWire (IEEE 1394) ports on both high level complex devices such as personal computers and simple devices such as inexpensive consumer electronics products. Includes references to normative specifi-cations as well as full reference designs that can be used as is or, with the careful consideration of the trade-offs, as a starting point for a more optimized design.FireWire Design Guide FWDG 1.0TA03/02/2010 1394 Trade Association Specifications are developed within Working Groups of the 1394 TradeAssociation, a non-profit industry association devoted to the promotion of and growth of the market forIEEE 1394-compliant products. Participants in Working Groups serve voluntarily and withoutcompensation from the Trade Association. Most participants represent member organizations of the 1394Trade Association. The specifications developed within the working groups represent a consensus of theexpertise represented by the participants.Use of a 1394 Trade Association Specification is wholly voluntary. The existence of a 1394 TradeAssociation Specification is not meant to imply that there are not other ways to produce, test, measure,purchase, market or provide other goods and services related to the scope of the 1394 Trade AssociationSpecification. Furthermore, the viewpoint expressed at the time a specification is accepted and issued issubject to change brought about through developments in the state of the art and comments received fromusers of the specification. Users are cautioned to check to determine that they have the latest revision of any1394 Trade Association Specification.Comments for revision of 1394 Trade Association Specifications are welcome from any interested party,regardless of membership affiliation with the 1394 Trade Association. Suggestions for changes indocuments should be in the form of a proposed change of text, together with appropriate supportingcomments.Interpretations: Occasionally, questions may arise about the meaning of specifications in relationship tospecific applications. When the need for interpretations is brought to the attention of the 1394 TradeAssociation, the Association will initiate action to prepare appropriate responses.Comments on specifications and requests for interpretations should be addressed to:Editor, 1394 Trade Association315 Lincoln, Suite EMukilteo, W A 98275USA1394 Trade Association Specifications are adopted by the 1394 Trade Association withoutregard to patents which may exist on articles, materials or processes or to otherproprietary intellectual property which may exist within a specification. Adoption of aspecification by the 1394 Trade Association does not assume any liability to any patentowner or any obligation whatsoever to those parties who rely on the specificationdocuments. Readers of this document are advised to make an independent determinationregarding the existence of intellectual property rights, which may be infringed byconformance to this specification.Published by1394 Trade Association315 Lincoln, Suite EMukilteo, WA 98275 USACopyright © 2010 by 1394 Trade AssociationAll rights reserved.Printed in the United States of AmericaFWDG 1.0TA FireWire Design Guide 03/02/2010IEEE CopyrightPortions of this specification are copied from published IEEE standards, by permission.The source documents are:IEEE Std 1394-1995, Standard for a High Performance Serial BusIEEE Std 1394a-2000, Standard for a High Performance Serial Bus – Amendment 1The IEEE copyright policy at /IPR/copyrightpolicy.html states, in part:Royalty Free PermissionIEEE-SA policy holds that anyone may excerpt and publish up to, but not more than, ten percent (10%) ofthe entirety of an IEEE-SA Document (excluding IEEE SIN books) on a royalty-free basis, so long as:1)proper acknowledgment is provided;2)the ‘heart’ of the standard is not entirely contained within the portion being excerpted.This included the use of tables, graphs, abstracts and scope statements from IEEE DocumentsFireWire Design Guide FWDG 1.0TA03/02/2010 ChecklistAll designers of devices with FireWire ports should look for the following:#2.1: Connectors (both plugs and sockets) shall meet the requirements laid out in the IEEE standards. (7)#2.2: Plugs shall have an overmold that includes strong tactile cues for orientation. (8)#2.3: Sockets should be oriented so that “thumb” part of plug is on top or on the left (9)#2.4: Sockets attached to a single PHY should be close together. (10)#2.5: FireWire 800 9-to-9 (1394b type 1) cable assemblies shields and ground shall not be shorted together. (10)#3.1: The wiring between the connector and the PHY (TP1 to TP2 and TP3 to TP4) shall be as short as possible. (14)#3.2: Ensure correct value for TPBIAS decoupling capacitor. (15)#3.3: Limit FW400 common mode choke to the minimum necessary to pass EMC (15)#3.4: Implement a transient protection circuit in a power provider to protect the PHY from late VG events. (15)#3.5: FireWire power should be current limited and filtered. (16)#3.6: VG must be capacitively connected to chassis ground and directly connected to PHY signal ground with minimal (pref-erably no) filtering. (16)#3.7: The socket shield shall be directly connected to chassis ground for all unisolated ports. (16)#3.8: The socket shield(s) shall be directly connected to VG at one place in the system. (17)#3.9: Systems that require isolated interfaces shall use a beta-only 1394b connection. (17)#3.10: FW800 ports should avoid common mode chokes. (18)#3.11: FW800 connector socket should internally bond the inner and outer shells. (18)#3.12: FW800 TPA and TPB shields have different termination requirements than each other and for FW400 shields. (18)#3.13: Ensure signal integrity of long traces to support front panel connectors. (18)#3.14: If a system has multiple PHYs and at least one of the PHYs has S800 or faster ports, then all the PHYs should be S800 or faster. (19)#4.1: Ensure that Power_class is set correctly. (21)#4.2: Ensure CONTENDER is deasserted (21)#4.3: Connect PCIe CLKREQ* (21)#4.4: TI PHY core voltage is 1.95V (22)#4.5: TI PHY core voltage filtering uses 1uF caps (22)#4.6: TI PHY oscillator voltage can be 1.95V (22)#4.7: Ensure correct PHY/LINK pin termination when using TI PHYs in repeater mode (22)#4.8: Ensure configuration and termination of unused port(s) on TI PHYs (22)#4.9: Ensure LKON/DS2 is correctly biased high or low (23)#4.10: Caution when TI 1394b PHY port 2 is unused or set to DS-only mode (23)#4.11: Note TI PHY max port speed is reported incorrectly for DS-mode only ports (23)#4.12: Use peaking inductors on bi-lingual ports on TI PHYs (23)#4.13: Tie PLLVDD_33 to the AVDD_3_3 power rail on TI PHYs. (23)#4.14: Ensure that TI PHY recommendations are met (23)#4.15: Connect Chex OHCI_PME# to a GPIO for optimal power management (23)#4.16: Ensure that Chex GRST# asserts only on link layer power cycle. (23)#4.17: Leave Chex GPIO’s as no-connects (24)#4.18: Bring Chex CYCLEOUT to a test point (24)#4.19: Connect VDD_33_AUX to 3.3V (24)#4.20: Ensure TI Link devices implementation requirements are met (24)#4.21: Ensure power is provided during sleep mode for TI Link devices. (24)#4.22: Ensure that G_RST* timing requirement is met (24)#4.23: G_RST* is asynchronous (24)#4.24: Ensure VAUX_DETECT is pulled high on FW643 (25)#4.25: Ensure FW643 power reset is stuffed consistently with regulation of 1.0V supply (25)#4.26: Ensure LSI integrated PHY/Link devices implementation requirements are met (25)#4.27: Ensure power is provided during sleep mode for LSI integrated PHY/Link devices. (25)#4.28: Ensure PME is uniquely identifiable to software for LSI FW323 v129. (25)#4.29: Internal or external pull-downs required on PHY/Link interface (27)#4.30: Special termination may be needed if PHY/Link propogation delay is > 1 ns (27)FWDG 1.0TA FireWire Design Guide 03/02/2010#5.1: All components and traces between the protection diode and the connector need to support 33V or higher. (29)#5.2: PHY operation should not be affected by power provider current limiter trips (29)#5.3: System operation of power providers should not be affected by power consumer inrush or shorts. (29)#5.4: Power Class 4 power providers should implement appropriate CSRs. (30)#5.5: Bus powered portable devices and peripherals should declare the appropriate power class. (30)#5.6: Power consumers should implement the power management CSRs. (30)#5.7: Ensure that CPS is correctly connected (32)#6.1: OHCI link must reliably meet real-time requirements under anticipated load. (40)FireWire Design Guide FWDG 1.0TA03/02/2010 Contents2. Mechanical (7)2.1 Connectors (7)2.2 End-to-end connections (10)3. Port design (14)3.1 Interfaces (14)3.2 Connector/PHY wiring (14)3.2.1 Termination (17)3.2.2 Front panel (“remote”) connector wiring guide (18)3.3 Testing Advice (19)4. System design (21)4.1 PHY selection (21)4.2 PHY configuration recommendations (21)4.2.1 General (21)4.3 Link layer recommendations (21)4.3.1 PCIe recommendations (21)4.4 Specific device recommendations (22)4.4.1 TI TSB81BA3 (22)4.4.2 TI XIO2213 (Cheetah Express, aka Chex) (23)4.4.3 Texas Instruments TSB82AA2 1394b link device (24)4.4.4 LSI FW643 (25)4.4.5 LSI FW323 (25)4.5 PHY/Link interface (27)4.5.1 Additional requirements (27)4.5.2 Layout guide (28)5. Cable power (29)5.1 Introduction (29)5.2 FireWire power checklistrecommendations (29)5.3 FireWire device guidelines (30)5.4 Example Circuits (31)5.4.1 Desktop alternate power provider (33)5.4.2 Desktop primary power provider with backup power pass-through (34)5.4.3 Portable computer (35)5.4.4 Peripherals or mobile devices (36)5.5 Notes (37)5.5.1 Power Classes (for reference) (37)5.5.2 Note on diode protection (37)5.5.3 Use of Power Down and Cable Not Active (38)5.5.4 Trade Association Cable Power Distribution Specification - proposed variations (39)6. Link selection (40)6.1 OHCI requirements (40)6.2 Target devices (40)6.2.1 Asynch peripherals (40)6.2.2 Media/consumer electronics (40)FWDG 1.0TA FireWire Design Guide 03/02/20107. Firmware/higher layers (41)7.1 Basic node operation (41)7.1.1 Bus initialization (41)7.1.2 Configuration ROM (41)7.1.3 Isochronous Resource Manager (41)7.1.4 Bus Manager (42)7.1.5 Required performance (42)7.1.6 Interoperability issues (42)7.2 Mass storage devices (42)7.2.1 SBP profile (42)7.2.2 A V profile (42)7.3 Imaging devices (42)7.3.1 Printers (42)7.3.2 Scanners (42)7.3.3 Still image cameras (42)7.3.4 Machine vision cameras (42)7.4 Consumer electronics (43)7.4.1 Tape recorders (43)7.4.2 Televisions (43)7.4.3 Set top boxes (43)7.4.4 Disks (43)7.4.5 Audio equipment (43)7.5 Professional (43)7.5.1 Audio (44)7.5.2 Video (44)7.6 Automobile (44)7.7 Industrial/Instrumentation (44)8.1 Layout recommendations for S800 1394b TSB81BA3 Physical Layer: (51)9. Firewire Design Guide – Robust Port Design (57)12.1 Conformance terminology (75)12.2 Technical glossary (75)FiguresFigure2-1— Plug overmold (8)Figure2-2— Socket orientation (as viewed from outside of bulkhead) (9)Figure2-3— Legacy socket orientation (as viewed from front of product) (9)Figure2-4— 1394b type 1 cable assembly and schematic (Beta plug to Beta plug) (11)Figure2-5— 1394b type 2 cable assembly and schematic (Legacy 6 circuit plug to Bilingual plug) (12)Figure2-6— 1934b type 3 cable assembly and schematic (Legacy 4-circuit plug to Bilingual plug) (13)Figure3-1— Measurement points (half connection is shown) (14)Figure5-1— A multiport Power Provider class 1/2/3 node (32)Figure5-2— A multiport Power Provider class 4 node (33)Figure5-3— A multiport Power Provider class 1/2/3 node, operating as Class 4 when power is not available (34)Figure5-4— A multiport Alternate Power Provider class 4 node (35)Figure5-5— A single port bus-powered (class 4) node (36)Figure5-6— A multiport bus-powered (class 4) node (36)Figure5-7— Diodes to provide power management domains (38)Figure8-1— Example FW800 OHCI Controller (46)Figure10-1— Example extendible two port power management IC (72)Figure10-2— Using multiple two port power management ICs (73)TablesTable2-1— Insertion and removal force (tentative) (7)Table2-2— 1394b type 1 (Beta to beta) end-to-end connections (11)Table2-3— Legacy 6 circuit to 1394b Bilingual end-to-end connections (12)Table2-4— Legacy 4 circuit to 1394b Bilingual end-to-end connections (13)Table3-1— 1394b receiver characteristics (14)Table4-1— Phantom cycles caused by MI cycle reflection (27)Table5-1— Power class (37)2.2.1ConnectorsItem #2.1:Connectors (both plugs and sockets) shall meet the requirements laid out in the IEEE stan-dards.Sockets must strongly resist “backwards” insertionThis means that the “narrow” part of the socket shall not have a split unless there is a mechanical reinforcement that pre-vents the narrow end from spreading when a plug is inserted backwards. It further means that the mechanical tolerences specified in [2], [3], and [4] must be met. In particular, the socket should meet the following insertion force requirements:Table2-1—Insertion and removal force(tentative)Condition Insertion/removalforceComment6-pin plug correctly aligned inserted into 6-pin socket9-pin plug correctly aligned inserted into 9-pin socket < 1 N measured using a plug that is at the maximum dimensions allowed by 1394, andmaximum value before any of the VG, VP, or TPx contactsmate, andmust have a noticeable “click” or “snap” when fully inserted6-pin plug correctly aligned removed from 6-pin socket9-pin plug correctly aligned removed into 9-pin socket > 1 N measured using a plug that is at the minimum dimensions allowed by 1394, andminimum value before any of the VG, VP, or TPx contactsseparate, andmust have a noticeable “click” or “snap” when removed6-pin plug reverse aligned inserted into 6-pinsocket9-pin plug reverse aligned inserted into 9-pinsocket > 10 N measured using a plug that is at the minimum dimensions allowed by 1394, andminimum force before any of the VG, VP, or TPx contactsmate, andsocket must be noticeably damaged by reverse insertion(allows diagnosis of improper use)Item #2.2:Plugs shall have an overmold that includes strong tactile cues for orientation.Overmold cues are to provide hints for where the user should put the thumb.a)Flat surface corresponds with “flat” surface on narrow axis b)Round surface corresponds with “angled” surface on narrow axisThis will assist in preventing attempted backwards connection (particularly if the connector placement rules described below are followed).Figure 2-1—Plug overmoldLegacy 6-pinBeta/bilingual 9-pinFWDG 1.0TA FireWire Design Guide 03/02/2010Item #2.3:Sockets should be oriented so that “thumb” part of plug is on top or on the leftSockets should have a standard orentation to aid the “blind” insertion of the plug. Since the plug overmold has features to encourage the placement of the thumb in a particular spot, and most people prefer to put their thumb on top of a plug as they insert it, the socket itself should be oriented so that the “thumb” feature is on top as viewed looking at the bulkhead from the outside. And since most people are right handed,. the alternate positioning should have the “thumb” feature on the left. Figures 2-2 and 2-3 illustrate the concept.Figure2-2—Socket orientation (as viewed from outside of bulkhead)... or as viewed from the front of a hypothetical product:Figure2-3—Legacy socket orientation (as viewed from front of product)FireWire Design Guide FWDG 1.0TA03/02/2010 Item #2.4:Sockets attached to a single PHY should be close together.Connectors, PHY, protection and termination components for a single port are best seen as a lumped circuit. The min. rise time for 1394a is 0.5 ns which implies 1 GHz waveforms, while the min. rise time for 1394b is 0.080 ns, over 6 GHz! If both front and back panel sockets are desired, then there are two choices:a)separate PHYs for front and back (two PHYs and one Link), orb) a very carefully designed “remote” socket where the entire path from the PHY termination network (seeclause3.2.2) to the socket is within 1394 requirements (110 ± 6 Ω differential mode and 33 ± 6 Ω common mode, more details in [2]). Note that this is quite unlikely to be successful for a S800 or faster port.2.2End-to-end connectionsItem #2.5:FireWire 800 9-to-9 (1394b type 1) cable assemblies shields and ground shall not be shorted together.Since the new 1394b connections are unfamiliar with designers, the end-to-end connections for the various 1394b cables are described in figure2-4, table2-2, figure2-5, table2-3, figure2-6 and table2-4.FWDG 1.0TA FireWire Design Guide03/02/2010NOTE—The legacy interface cables (type 2 9-to-6 and type 1 9-to-4) do short some of the shields and ground together. It is important that this be done correctly for each cable type.NOTE—Cable as defined in 1394b. Connectors are viewed as looking at the front plug face.Figure 2-4—1394b type 1 cable assembly and schematic (Beta plug to Beta plug)Table 2-2—1394b type 1 (Beta to beta) end-to-end connectionsSignal PCB pad Socket/plug name Socket/plug connection Cable Socket/plug connection Socket/plug name PCB pad SignalChassis Ground 13Chassis GroundOuter shell(no connect)Outer shell Chassis Ground12Chassis Ground Chassis Ground, HF to Logic Ground 11Cable Shield Ground Inner shell Outer shieldInner shellCable Shield Ground 10Chassis Ground, HF to Logic Ground TPA4TPA 4Signal pair #1 red2TPB 2TPB High frequency to Logic Ground 5TPA(R)5Signal pair #1 shield 9TPB(R)9Logic Ground TPA*3TPA*3Signal pair #1 green 1TPB*1TPB*Logic Ground 6VG 6Power pair #1 white 6VG 6Logic Ground (no connect)7SC 7(no connect)7SC 7(no connect)FW PWR 8VP 8Power pair #1 black 8VP 8FW PWR TPB 2TPB 2Signal pair #2 blue4TPA 4TPALogic Ground 9TPB(R)9Signal pair #2 shield 5TPA(R)5High frequency to Logic Ground TPB*1TPB*1Signal pair #2 orange 3TPA*3TPA*Chassis Ground, HF to Logic Ground 10Cable Shield Ground Inner shell Outer shieldInner shellCable Shield Ground 11Chassis Ground, HF to Logic Ground Chassis Ground12Chassis GroundOuter shell(no connect)Outer shellChassis Ground13Chassis Ground743215689743215689plug 1plug 2FireWire Design GuideFWDG 1.0TA 03/02/2010NOTE—Cable (reference) IEEE Std 1394-1995. Connectors are viewed as looking at the front plug face.Figure 2-5—1394b type 2 cable assembly and schematic (Legacy 6 circuit plug to Bilingual plug)Table 2-3—Legacy 6 circuit to 1394b Bilingual end-to-end connectionsSignalPCB padSocket/plug nameSocket/plug connectionCable Socket/plug connection Socket/plug name PCB pad Signal (no connect)Outer shell Chassis Ground12Chassis Ground Chassis Ground, HF to Logic Ground Cable Shield Ground Plug shell Outer shieldInner shellCable Shield Ground 10Chassis Ground, HF to Logic Ground TPA 6TPA 6Signal pair #1 red 2TPB 2TPB Logic Ground 2VG 2Signal pair #1 shield 9TPB(R)9Logic Ground TPA*5TPA*5Signal pair #1 green 1TPB*1TPB*Logic Ground2VG2Power pair #1 white 6VG 6Logic Ground (no connect)7SC 7(no connect)FW PWR 1VP 1Power pair #1 black 8VP 8FW PWR TPB 4TPB 4Signal pair #2 blue 4TPA 4TPALogic Ground 2VG 2Signal pair #2 shield 5TPA(R)5High frequency toLogic Ground TPB*3TPB*3Signal pair #2 orange 3TPA*3TPA*Chassis Ground, HF to Logic GroundCable Shield Ground Plug shell Outer shieldInner shellCable Shield Ground 11Chassis Ground, HF to Logic Ground (no connect)Outer shellChassis Ground13Chassis Ground432156743215689plug 1plug 2NOTE—Cable (reference) IEEE Std 1394a-2000. Connectors are viewed as looking at the front plug face.Figure 2-6—1934b type 3 cable assembly and schematic (Legacy 4-circuit plug to Bilingual plug)Table 2-4—Legacy 4 circuit to 1394b Bilingual end-to-end connectionsSignalPCB padSocket/plug nameSocket/plug connectionCable Socket/plug connection Socket/plug name PCB pad Signal (no connect)Outer shell Chassis Ground12Chassis Ground (no connect)Outer shieldInner shellCable Shield Ground 10Chassis Ground, HF to logic Ground TPA 4TPA 4Signal pair #1 red 2TPB 2TPB Logic Ground ShellPlug shell Signal pair #1 shield 9TPB(R)9Logic Ground TPA*3TPA*3Signal pair #1 green 1TPB*1TPB*(no connect)6VG 6Logic Ground (no connect)7SC 7(no connect)(no connect)8VP 8FW PWR TPB 2TPB 2Signal pair #2 blue 4TPA 4TPALogic Ground ShellPlug shell Signal pair #2 shield 5TPA(R)5High frequency to Logic Ground TPB*1TPB*1Signal pair #2 orange 3TPA*3TPA*(no connect)Outer shieldInner shellCable Shield Ground 11Chassis Ground, HF to logic Ground (no connect)Outer shellChassis Ground13Chassis Ground4321plug 1743215689plug 23.There are a number of good 1394 port design application notes. The TI notes on EMI [11] and layout [12] as well as the LSI design guide for the FW323 [13] are particularly good. Every designer of FireWire systems should be familiar with these documents. Much of the following is derived from those application notes.3.1InterfacesAll interface specifications apply at the points of entry and exit from the equipment. The interface specifications may be “valid” at other places. These points are identified as points TP2 and TP3 as shown in Figure 3-1. The specifications assume that all measurements are made after a mated connector pair, relative to the source or destination. TP1 and TP4are reference points for use by implementors to specify vendor components. In particular, PHY IC specs apply at TP1 for transmit and TP4 for receive.The reference points for all connections are those points TP2 and TP3 at the transitions between the cabinet and the cable shield. If sections of transmission line exist within the cabinet shield, they are considered to be part of the associated transmit or receive network, and not part of the cable plant.NOTE—Do not confuse “TPn” where “n” is the number one through four with the “TPx” where “x” is “A” or “B”. TPn refers to a test point and TPx refers to a twisted pair signal.3.2Connector/PHY wiringItem #3.1:The wiring between the connector and the PHY (TP1 to TP2 and TP3 to TP4) shall be as short as possible.The TPA and TPB pairs carry very high speed signals, and so must be imlemented using good design practices for high speed circuits and interfaces to external devices. The impedance requirements for the connector/PHY wiring shall meet 1394b requirements (included below for reference).Figure 3-1—Measurement points (half connection is shown)Table 3-1—1394b receiver characteristicsParameterS400βS800βS1600βUnitsInput impedance test conditions:TDR rise time 10010050ps Exception window a 700700700psInput impedance @ TP3:Through connection b 110 ± 20110 ± 20110 ± 20ΩAt termination c110 ± 10110 ± 10110 ± 10ΩTRANSMIT NETWORKRECEIVE NETWORKT+T-R+R-TP1TP2TP3TP4PHYPHYNOTE—1394 bilingual and FW400 ports have transmitter and receiver on both the TPA and TPB signals, so the receiver input impedance spec applies for both pairs.3.2.0.1TerminationThe TPA pair has the required 110 ¾ differential termination as close as possible to the PHY, with the center point of the termination attached to the PHY’s bias output for that port and capacitively to signal ground (each port on the PHY shall have an independent bias output – this is required to prevent a short on one port from causing all the other ports to not operate).Item #3.2:Ensure correct value for TPBIAS decoupling capacitor.The PHY’s tpbias output should be decoupled with a 0.33 μF capacitor to ground, unless the PHY is a TI PHY. TI PHYs need a 1.0 μF to ground, so as to guarantee a minimum ripple on the tpbias voltage under a worst-case speed-signaling scenario, which is necessary in the TI design to maintain stability of the tpbias driver. The lower value is needed when using non-TI PHYs in order to meet the 1394a timing specification for tpbias assertion and deassertion.3.2.0.2TP EMC/EMI protectionItem #3.3:Limit FW400 common mode choke to the minimum necessary to pass EMCFW400 ports may need a high speed common mode choke, particularly if the PHY-to-connector layout is long or runs near possible signal sources. Individual components must be used for each signal pair to limit crosstalk between TPA and TPB. The choke must allow the lower fequency common mode speed signals to get through (while removing high fre-quency common mode signals). In general, this means that the common mode impendence must be less than 165 Ohms at 100 MHz, and the differential impedence less than 15 ohm at 100 MHz.Products should use the minimum choke necessary to pass EMC. The design should anticipate evaluation of EMC com-pliance with several values (for example, the Murata DLP11SN range starts at 67 Ohms, with variants at 90 Ohms, 120Ohms and 160 Ohms), and with not using a common mode choke at all. This can be achieved by designing the layout to allow a common mode choke or a 0 Ohm resistor.3.2.0.3Transient protectionItem #3.4:Implement a transient protection circuit in a power provider to protect the PHY from late VG events.Power providers should have a diode clamping network between the PHY and the socket to provide two functions:a)ESD protection so that the high voltage is drained to the chassis, andDifferential skew5%5%5%UI Common mode input impedance> 550Ωa.Within the Exception-window no single impedance excursion shall exceed the Through-connection impedance tolerance for a period of twice the TDR rise time specification.b.Through connection impedance describes the impedance tolerance through a mated connector. This tolerance is greater than the termination or cable impedance due to limits in the technology of the connectors.c. The input impedance at TP3, for the termination, shall be recorded 4.0ns following the electrical reference plane determined by the receptacle on the receiver bulkheadTable 3-1—1394b receiver characteristicsParameterS400βS800βS1600βUnitsFireWire Design Guide FWDG 1.0TA03/02/2010 b)“Late VG” protection (so called because the power provided on VP can appear on the TPx signals if the VGconnection takes place after the VP and at least one of the TPx connections is completed). Note that this last function requires that chassis ground and signal ground have a low resistance connection somewhere (see Item #3.8:below).The high side clamp diodes use a 3.6V nominal zener diode prebiased with a 3.3V source via a 330 Ohm current liminting resistor (other sources may be used with an appropriate resistor value). This provides a nominal 2.4V, worst case 2.1V ESD and late-VG rail to the BAV99 diodes. In turn, allowing for a 0.6V drop through the diodes, this will permit FireWire signaling at up to 2.7V without compromising signal integrity. A late-VG event on the signal pairs will be drained back to ground via the Zener diode. Late VG events can be of a long duration, and they represent a return path for the VP supply, so the current must be directed back to VG. Despite its rating, the recommended Zener has been mea-sured as being capable of sustaining a current of 300mA, up to 2W, keeping the voltage level on the signal pins to less than 5.5V, which the PHY is also able to tolerate. Under more stress, either the PHY fails or the Zener. The Zener tends to fail short, which results in the TPA/TPB pairs being held to GND and preventing FireWire operation. Lower voltage Zeners, which have been used in some designs, tend to fail before the PHY, increasing the system return rate unnecessar-ily.ESD events are of a short duration and will be drained from digital ground to chassis ground and from there to earth ground. It is acceptable to use signal ground instead of chassis ground for the transient protection network since signal ground is capacitively connected to chassis ground at the connector. This can only be done if there is no ferrite on the VG path (see Item #3.6:below). The galvanic connection between chassis ground and signal ground must be low impedance at the frequencies not handled by the capacitive connection at the connector.If a common mode choke is used, then the transient supression network should be placed on the PHY side of the choke. The advantage of having the diodes on the PHY side is that the common mode choke can be placed closer to the connec-tor for better EMI performance.Late-VG does not occur on self powered devices.Transient protection iodes must have a very low capacitance (less than 0.5 pF).3.2.0.4Power and ground interface (VG/VP)Item #3.5:FireWire power should be current limited and filtered.VP should be current limited 1.5 A and EMI filtered to minimize system noise getting out to peripherals. Current limit can be done using a polyfuse, although their slow trip speed requires careful thought put towards the effect of momentary excess current draw. A choke between 50 ohm and 1000 ohm (at 100 MHz) is acceptable in the path for EMI filtering and should be located close to the sockets. A 0.010µf capacitor should connect to chassis ground immediately next to the socket.Item #3.6:VG must be capacitively connected to chassis ground and directly connected to PHY signal ground with minimal (preferably no) filtering.VG should AC connect to chassis ground immediately next to the socket using a 0.010µf capacitor. There must not be a significant impedance in the path between VG and the PHY signal ground since VG is the return path for the common mode speed signalling sent out on TPB and received on TPA. If a filter is implemented, it should be designed to pass the speed signal (100-120ns pulse of about 20ma on VG). Usually this means any ferrite in the VG path must be 50 ohm or less at 100 MHz.3.2.0.5Shield interfaceItem #3.7:The socket shield shall be directly connected to chassis ground for all unisolated ports.There should be a chassis ground plane underneath the socket for this purpose. The galvanic isolation options defined in 1394a and 1394-1995 should no longer be used.。
5114351_上菲红稳步迈向全系列动力供应商
0418□邮箱：***************专 题■ 本报记者 李晓菲 文/图4月20日，第十三届北京国际汽车展览会如期举行，上汽集团以集团形式参展。
作为上汽集团商用车板块关键零部件总成，上汽菲亚特红岩动力总成有限公司（以下简称“上菲红”）携旗下CURSOR、NEF、F1三大系列产品亮相，收获众多关注。
销量快速增长作为行业新兵，上菲红自2008年首台发动机下线以来，每年都以令人惊喜的速度快速增长，技术领先、品质可靠的产品是其销量快速增长的首要原因。
通过引进菲亚特动力科技的先进技术，上菲红发动机产品在动力性、燃油经济性、舒适性、环保等方面都能更好地满足用户需求。
为保证产品质量，上菲红还采用了WCM （世界级制造）生产管理系统，该系统是通过全员参与的方式，降低由于生产系统可靠性及运营低下导致的时间和资源浪费，改善生产效率，减少故障和提升质量的全面管理系统，专注于全体质量控制（TQC）、全体生产维护（TPM）、全体工业设计（TIE）、 及时交付（JIT），最终目标是将世界级制造延伸到所有工艺工程乃至所有供应商，从而实现生产过程零事故、生产设备零故障、生产材料零报废和产品质量零缺陷、物流过程零库存。
据介绍，上菲红目前的产品结构仍以CURSOR 系列为主，CURSOR 9是销售主力产品，在卡车、客车、工程机械、发电机组等领域均有所应用。
同时，轻型发动机F1系列的适配范围也逐步扩大，目前已经在轻客、皮卡、小型船舶等领域配装应用。
“2013年，上菲红完成了年初销售目标，销量达到23000台，这一销量的实现主要得益于上菲红在重卡市场产品认可度的提高以及出口市场的扩大。
”上菲红总经理Olivier Michard 表示。
目前，除了上汽依维柯红岩、南京依维柯等企业，上菲红动力产品还已经成功匹配宇通、华菱、武汉枭龙、山西中大、江苏巨超等众多国内品牌。
在国外市场，CURSOR 9已经配装美国CNH（凯斯纽荷兰）的农业设备；另外，CURSOR 9欧Ⅵ标准发动机已经开始在意大利IVECO 整车（卡车、客车）上批量配装。
宇通客车开辟车内自由呼吸新天地
04 □邮箱：***************宇通客车开辟车内自由呼吸新天地本报讯 客车业巨头宇通推出了能有效降低车内PM2.5的车载空气净化装置，由此，雾霾天气中乘车外出的人们在移动的公交车内终于可以解开口罩放松呼吸。
宇通早在2008年就开始关注车内空气质量问题并于去年1月成功研发出空气净化装置，在国内大范围雾霾天气出现后，又在最短时间内对装置进行更新升级，强化了PM2.5的净化功能，装置已于今年2月获得国家知识产权局专利。
该装置主要针对人员复杂及有机性污染物多的客车巴士开发，可实现对PM2.5的去除功能，也具备对甲醛、甲苯等本报讯 华菱星马一季度累计销售重卡5385辆、专用车1299辆，同比分别增长20.85%和25.75%，实现了自2011年以来的首次增长。
今年以来，公司加大了市场开拓力度和提升营销体系内部效能：所有销售人员重新配备，精英充实到市场；内部各岗位职能重新整合；完善营销体系内部沟通机制；利用现代化通信提高各项工作效率。
一系列举措有效推动了销售的高效率运转，一季度的大幅增长既有市场回暖的因素，更是华菱厚积薄发、提前准备的结果。
赵 勇华菱星马一季度劲增超20%本报讯 四川省芦山“4·20”7.0级强烈地震发生后，上汽依维柯红岩商用车有限公司快速响应，位于雅安范围内的红岩汉源服务站服务小分队当晚即赶往灾区，为抗震救灾军用车辆全力做好服务保障，同时义务为灾区民用车辆展开维修检测。
4月21日，第二批服务人员在天全县始阳镇集合，随时待命进入灾区。
雅安周边的8家红岩服务站已做好准备，实行24小时值班制度，利用专业的流动服务车辆对参加抗震救灾的军车、民用重卡实施现场救援，免收一切服务费用。
商 车灾后第一晚红岩汽车小分队进入芦山本报讯 近日，东风柳汽在业内首推体验式营销，针对新上市不久的霸龙康明斯M7C 在全国范围内开展免费试用活动，最长试用时间可达1个月，试用里程最长可达2万公里，将柳汽的价值营销上升到了新高度。
TSPL中文文档
目录文件字体规则 (1)系统设定指令 (2)SIZE (2)GAP (3)BLINE (4)OFFSET (5)SPEED (6)DENSITY (7)DIRECTION (8)REFERENCE (9)COUNTRY (10)CODEPAGE (11)CLS (12)FEED (13)FORMFEED (14)HOME (15)PRINT (16)SOUND (17)CUT (18)LIMITFEED (19)卷标内容设计指令 (20)BAR (20)BARCODE (21)BITMAP (25)BOX (26)ERASE (27)DMATRIX (28)MAXICODE (29)PDF417 (32)PUTPCX (34)REVERSE (35)TEXT (36)询问打印机状态指令 (38)<ESC>!? (38)~!A (40)~!T (41)~!C (42)~!I (43)~!F (44)~!@ (45)信息传递协议 (46)<ESC>! (46)<ESC>& (46)~# (47)WINDOWS DRIVER驱动程序指令 (48)!B (48)!J (49)!N (50)档案管理指令 (51)DOWNLOAD (51)REDRAW (59)EOP (60)FILES (61)KILL (62)MOVE (63)UPDATBIOS (64)BASIC 指令及函式 (65)ABS( ) (65)ASC( ) (66)CHR$( ) (67)END (68)EOF( ) (69)OPEN (71)READ (73)SEEK (75)LOF( ) (77)FREAD$( ) (77)FOR...NEXT.. (79)IF...THEN...ELSE (81)GOSUB...RETURN. (83)GOTO (85)INPUT (88)REM (90)OUT (91)GETKEY( ) (92)INT( ) (93)LEFT$( ) (94)LEN( ) (95)MID$( ) (96)RIGHT$( ) (97)STR$( ) (98)VAL( ) (99)BEEP (100)打印机外围功能设定指令 (101)SET COUNTER (101)SET CUTTER (103)SET KEY1 (105)SET KEY2 (105)SET LED1, LED2, LED3 (107)SET PEEL (108)SET DEBUG (109)SET GAP (110)SET RIBBON (111)SET COM1 (112)@LABEL (114)PEEL (115)LED1, LED2, LED3 (116)KEY1, KEY2 (117)YEAR (118)MONTH (119)DATE (120)WEEK (121)HOUR (122)MINUTE (123)SECOND (125)文件字体规则本文件使用以下字体规则文件规则描述[表示内容] 在`中括号内表示该参数为选项<ESC> <ESC>代表ASCII 27 字符，当打印机收到以该控制字符为启始之指令将立即响应(即使打印机在错误状态时也将实时回应)~ (ASCII 126), 该字符启始的指令用于询问打印机的状态注: 200 DPI: 1 mm = 8 dots 粗斜体Arial,字型，用于表300 DPI: 1 mm = 12 dots 示批注DOWNLOAD “TEST.BAS”当所列出的内容为程序SET COUNTER @1 1 时以Curier 字型表示@1=”0001”TEXT 10,10,”3”,0,1,1,@1PRINT 3,2EOP系统设定指令SIZE说明该指令用于设定卷标纸的宽度及长度指令语法(1) 英制系统(英寸)SIZE m, n(2) 公制系统(公厘)SIZE m mm, n mm参数说明m 标签纸的宽度 (不含背纸)n 标签纸的长度 (不含背纸)Note: 200 DPI: 1 mm = 8 dots*300 DPI: 1 mm = 12 dots范例(1) 英制系统 (英寸)SIZE 3.5, 3.00(2) 公制系统 (公厘)SIZE 100 mm, 100 mmGAP说明该指令定义两张卷标纸间的垂直间距距离指令语法(1) 英制系统 (英寸)GAP m, n(2) 公制系统 (公厘)GAP m mm, n mm参数说明m 两标签纸中间的垂直距离0 ≤ m ≤ 1 (英寸), 0 ≤ m ≤ 25.4 (公厘)n 垂直间距的偏移[-]n ≤标签纸张长度 (英寸或公厘)Note: 200 DPI : 1 mm = 8 dots300 DPI : 1 mm = 12 dots范例一般垂直间距设定(1) 英制系统 (英寸)GAP 0.12,0(2) 公制系统 (公厘)GAP 3 mm,0特殊垂直间距设定(1) 英制系统 (英寸)GAP 0.30,-0.10(2) 公制系统 (公厘)GAP 7.62 mm, -2.54 mmBLINE说明该指令用于设定黑标的高度及偏移位置指令语法(1) 英制系统 (英寸)BLINE m, n(2) 公制系统 (公厘)BLINE m mm, n mm参数说明m 黑标的高度，以英寸或公厘表示0.1 ≤m ≤1 (英寸), 2.54 ≤m ≤ 25.4 (公厘)n 黑标偏移量 0 ≤n ≤标签纸张高度范例(1) 英制系统 (英寸)BLINE 0.20,0.50(2) 公制系统 (公厘)BLINE 5.08 mm,12.7 mmOFFSET说明该指令用于控制在剥离模式时(pee-off mode)每张卷标停止的位置，该指令仅适用于剥离模式。
PIC16LF1508-ISS;PIC16F1508-ISS;PIC16LF1509-ISS;PIC16F1509-ISS;中文规格书,Datasheet资料
Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, , dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, , PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2011, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-61341-726-3
CANalyzer.J1939_Manual_EN
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User Manual
CANalyzer Option .J1939
Version 7.0 English
Imprint
Vector Informatik GmbH Ingersheimer Straße 24 D-70499 Stuttgart
The information and data given in this user manual can be changed without prior notice. No part of this manual may be reproduced in any form or by any means without the written permission of the publisher, regardless of which method or which instruments, electronic or mechanical, are used. All technical information, drafts, etc. are liable to law of copyright protection. © Copyright 2007, Vector Informatik GmbH All rights reserved.
国际电子（National Instruments）USB-7845R OEM 多功能数字实时接口设
SPECIFICATIONSNI USB-7845R OEMR Series for USB Multifunction RIO with Kintex-7 70T FPGA Français Deutsch日本語한국어简体中文/manualsThis document contains the specifications for the National InstrumentsUSB-7845R OEM device. Specifications are typical at 25 °C unless otherwise noted.Caution Using the NI USB-7845R OEM device in a manner not described in thisdocument may impair the protection the NI USB-7845R OEM device provides. Analog InputNumber of channels8 ............................................................................Input modes DIFF, NRSE, RSE (software-selectable; ............................................................................selection applies to all channels)Type of ADC Successive approximation register (SAR) ............................................................................Resolution16 bits ............................................................................Conversion time 2 µs ............................................................................Maximum sampling rate500 kS/s (per channel) ............................................................................Input impedancePowered on 1.25 GΩ ║ 2 pF....................................................................Powered off/overload 4.0 kΩ min....................................................................Input signal range±1 V, ±2 V, ±5 V, ±10 V (software-selectable) ............................................................................Input bias current±5 nA ............................................................................ ............................................................................Input offset current±5 nAInput coupling DC ............................................................................Overvoltage protection....................................................................Powered on±42 V maxPowered off±35 V max....................................................................Table 1. AI Operating Voltage Ranges Over TemperatureAI Absolute AccuracyAbsolute accuracy at full scale numbers is valid immediately following internal calibration and assumes the device is operating within 10 °C of the last external calibration. Accuracies listed are valid for up to one year from the device external calibration.Absolute accuracy at full scale on the analog input channels is determined using the following assumptions:•TempChangeFromLastExternalCal = 10 °C •TempChangeFromLastInternalCal = 1 °C•number_of_readings = 10,000•CoverageFactor = 3 σ1The minimum measurement voltage range is the largest voltage the NI USB-7845R OEM device is guaranteed to accurately measure.2| | NI USB-7845R OEM SpecificationsTable 2. AI Absolute Accuracy (Calibrated) (Continued)Table 3. AI Absolute Accuracy (Uncalibrated)Calculating Absolute AccuracyAbsoluteAccuracy=Reading⋅(GainError)+Range*(OffsetError)+NoiseUncertaintyGainError=ResidualGainError+GainTempco*(TempChangeFromLastInternalCal)+ReferenceTempco*(TempChangeFromLastExternalCal)OffsetError=ResidualOffsetError+OffsetTempco*(TempChangeFromLastInternalCal)+INL_ErrorNoiseUncertainty=Refer to the following equation for an example of calculating absolute accuracy.NI USB-7845R OEM Specifications| © National Instruments| 3Absolute accuracy at full scale on the analog input channels is determined using the following assumptions:•TempChangeFromLastExternalCal = 10 °C •TempChangeFromLastInternalCal = 1 °C•number_of_readings = 10,000•CoverageFactor = 3 σGainError=104.4ppm+20ppm*1+4ppm*10GainError=164.4ppmOffsetError=16.4ppm+4.18ppm*1+42.52ppmOffsetError=63.1ppmNoiseUncetainty=NoiseUncertainty=7.89µVAbsoluteAccuracy=10V*(GainError)+10V*(OffsetError)+NoiseUncertaintyAbsoluteAccuracy=2,283µVDC Transfer Characteristics ............................................................................INL Refer to the AI Accuracy TableDNL±0.4 LSB typ, ±0.9 LSB max ............................................................................No missing codes16 bits guaranteed ............................................................................CMRR, DC to 60 Hz-100 dB ............................................................................Dynamic CharacteristicsBandwidthSmall signal 1 MHz........................................................................................................................................Large signal500 kHz4| | NI USB-7845R OEM Specifications............................................................................Crosstalk-80 dB, DC to 100 kHzAnalog Output ............................................................................Output type Single-ended, voltage output ............................................................................Number of channels8 ............................................................................Resolution16 bits ............................................................................Update time 1.0 µs ............................................................................Maximum update rate 1 MS/sType of DAC Enhanced R-2R ............................................................................ ............................................................................Range±10 V ............................................................................Output coupling DCOutput impedance0.5 Ω............................................................................NI USB-7845R OEM Specifications| © National Instruments| 5............................................................................Minimum current drive±2.5 mAProtection Short circuit to ground ............................................................................Overvoltage protectionPowered on±15 V max....................................................................Powered off±10 V max....................................................................Power-on state User-configurable ............................................................................Power-on glitch-1 V for 1 µs ............................................................................Table 4. AO Operating Voltage Ranges for Over TemperatureAO Absolute AccuracyAbsolute accuracy at full scale numbers is valid immediately following internal calibration and assumes the device is operating within 10 °C of the last external calibration. Accuracies listed are valid for up to one year from the device external calibration.Absolute accuracy at full scale on the analog output channels is determined using the following assumptions:•TempChangeFromLastExternalCal = 10 °C •TempChangeFromLastInternalCal = 1 °C2The minimum measurement voltage range is the largest voltage the NI USB-7845R OEM device is guaranteed to accurately measure.6| | NI USB-7845R OEM SpecificationsTable 5. AO Absolute Accuracy (Calibrated) (Continued)Calculating Absolute AccuracyAbsoluteAccuracy=OutputValue*(GainError)+Range*(OffsetError)GainError=ResidualGainError+GainTempco*(TempChangeFromLastInternalCal)+ReferenceTempco*(TempChangeFromLastExternalCal)OffsetError=ResidualOffsetError+AOOffsetTempco*(TempChangeFromLastInternalCal)+INL_Error Refer to the following equation for an example of calculating absolute accuracy.Absolute accuracy at full scale on the analog output channels is determined using thefollowing assumptions:•TempChangeFromLastExternalCal = 10 °C•TempChangeFromLastInternalCal = 1 °CGainError=87.3ppm+12.6ppm*1+4ppm*10GainError=139.9ppmNI USB-7845R OEM Specifications| © National Instruments| 7OffsetError=41.1ppm+7.8ppm*1+61ppmOffsetError=109.9ppmAbsoluteAccuracy=10V*(GainError)+10V*(OffsetError)AbsoluteAccuracy=2,498µVDC Transfer CharacteristicsINL Refer to the AO Accuracy Table ............................................................................DNL±0.5 LSB typ, ±1 LSB max ............................................................................Monotonicity16 bits, guaranteed ............................................................................Dynamic CharacteristicsSlew rate-10 V/µs ............................................................................Noise250 µV rms, DC to 1 MHz ............................................................................Glitch energy at midscale transition±10 mV for 3 µs ............................................................................5V OutputOutput voltage 4.75 V to 5.1 V ............................................................................Output current0.5 A max ............................................................................Overvoltage protection±30 V ............................................................................ ............................................................................Overcurrent protection650 mA8| | NI USB-7845R OEM SpecificationsDigital I/OCompatibility LVTTL ............................................................................Logic family User-selectable ............................................................................Default software setting 3.3 V ............................................................................Maximum input 3.6 V ............................................................................NI USB-7845R OEM Specifications| © National Instruments| 9Table 10. Digital Output Logic Levels (Continued)Output currentSource 4.0 mA....................................................................Sink 4.0 mA....................................................................Input leakage current±15 µA max ............................................................................Input impedance50 kΩ typ, pull-down ............................................................................Power-on state Programmable, by line ............................................................................Protection±20 V, single line ............................................................................Digital I/O voltage switching time 2 ms max ............................................................................Note Refer to NI RIO Software Help for more information about switching times.Reconfigurable FPGAFPGA type Kintex-7 70T ............................................................................Number of flip-flops82,000 ............................................................................Number of LUTs41,000 ............................................................................Embedded block RAM4,860 kbits ............................................................................Number of DSP48 slices240 ............................................................................Timebase40, 80, 120, 160, or 200 MHz ............................................................................Timebase accuracy, onboard clock±100 ppm ............................................................................Calibration ............................................................................Recommended warm-up time15 minutesCalibration interval 1 year ............................................................................10| | NI USB-7845R OEM SpecificationsOnboard calibration referenceDC level3 5.000 V (±2 mV)....................................................................Temperature coefficient±4 ppm/°C max....................................................................Long-term stability±25 ppm/1,000 h....................................................................Note Refer to Calibration Certifications at /calibration to generate acalibration certificate for the NI USB-7845R OEM deviceBus Interface ............................................................................USB compatibility USB 2.0 Hi-Speed or Full-Speed4Data transfers DMA, interrupts, programmed I/O ............................................................................Number of DMA channels3 ............................................................................Power RequirementInput voltage9 V to 30 V ............................................................................Max power20 W ............................................................................ ............................................................................Overvoltage protection40 VNote You must use a UL Listed ITE power supply marked LPS with theNI USB-7845R OEM device.PhysicalNote If you need to clean the device, wipe it with a dry, clean towel.Dimensions (PCB)17.5 cm × 16.3 cm (6.9 in. × 6.4 in.) ............................................................................Weight183 g (6.45 oz) ............................................................................I/O connectors Analog- 1 × 50 pin box header, ............................................................................Digital- 3 × 34 pin box header3Actual value stored in Flash memory4Operating on a full-speed bus will result in lower performance and you might not be able to achieve maximum sampling/update rates.NI USB-7845R OEM Specifications| © National Instruments| 11Maximum Working VoltageMaximum working voltage refers to the signal voltage plus the common-mode voltage. Channel-to-earth±12 V, Measurement Category I ............................................................................Channel-to-channel±24 V, Measurement Category I ............................................................................Measurement Category I is for measurements performed on circuits not directly connected to the electrical distribution system referred to as MAINS voltage. MAINS is a hazardous live electrical supply system that powers equipment. This category is for measurements of voltages from specially protected secondary circuits. Such voltage measurements include signal levels, special equipment, limited-energy parts of equipment, circuits powered by regulated low-voltage sources, and electronics.Caution Do not use the NI USB-7845R OEM device for connection to signals inMeasurement Categories II, III, or IV.Note Measurement Categories CAT I and CAT O (Other) are equivalent. Thesetest and measurement circuits are not intended for direct connection to the MAINSbuilding installations of Measurement Categories CAT II, CAT III, or CAT IV. Environmental-40 °C to 70 °COperating temperature ............................................................................(IEC 60068-2-1, IEC 60068-2-2)Storage temperature-40 °C to 85 °C ............................................................................(IEC 60068-2-1, IEC 60068-2-2)10% to 90% RH, noncondensingOperating humidity ............................................................................(IEC 60068-2-56)Storage humidity (IEC 60068-2-56)5% to 95% RH, noncondensing ............................................................................ ............................................................................Pollution Degree2Maximum altitude2,000 m ............................................................................Indoor use only.Online Product CertificationTo obtain product certifications and the DoC for this product, visit /certification, search by model number or product line, and click the appropriate link in the Certification column.12| | NI USB-7845R OEM SpecificationsEnvironmental ManagementNI is committed to designing and manufacturing products in an environmentally responsible manner. NI recognizes that eliminating certain hazardous substances from our products is beneficial to the environment and to NI customers.For additional environmental information, refer to the Minimize Our Environmental Impact web page at /environment. This page contains the environmental regulations and directives with which NI complies, as well as other environmental information not included in this document.Waste Electrical and Electronic Equipment (WEEE)EU Customers At the end of the product life cycle, all products must be sent to aWEEE recycling center. For more information about WEEE recycling centers,National Instruments WEEE initiatives, and compliance withWEEE Directive 2002/96/EC on Waste Electrical and Electronic Equipment, visit/environment/weee.电子信息产品污染控制管理办法（中国RoHS）中国客户National Instruments符合中国电子信息产品中限制使用某些有害物质指令(RoHS)。
MX25L25635E, 3V, 256Mb, v1.3
MX25L25635EHIGH PERFORMANCE SERIAL FLASH SPECIFICA TIONContentsFEATURES (5)GENERAL DESCRIPTION (7)Table 1. Additional Features (7)PIN CONFIGURATION (8)PIN DESCRIPTION (8)BLOCK DIAGRAM (9)DATA PROTECTION (10)Table 2. Protected Area Sizes (11)Table 3. 4K-bit Secured OTP Definition (11)Memory Organization (12)Table 4. Memory Organization (12)DEVICE OPERATION (13)Figure 1. Serial Modes Supported (for Normal Serial mode) (13)HOLD FEATURES (14)Figure 2. Hold Condition Operation (14)COMMAND DESCRIPTION (15)Table 5. Command Sets (15)(1) Write Enable (WREN) (17)(2) Write Disable (WRDI) (17)(3) Read Identification (RDID) (17)(4) Read Status Register (RDSR) (18)(5) Write Status Register (WRSR) (19)Protection Modes (19)(6) Enter 4-byte mode (EN4B) (20)(7) Exit 4-byte mode (EX4B) (20)(8) Read Data Bytes (READ) (20)(9) Read Data Bytes at Higher Speed (FAST_READ) (20)(10) 2 x I/O Read Mode (2READ) (21)(11) Dual Read Mode (DREAD) (21)(12) 4 x I/O Read Mode (4READ) (21)(13) Quad Read Mode (QREAD) (22)(14) Sector Erase (SE) (22)(15) Block Erase (BE) (23)(16) Block Erase (BE32K) (23)(17) Chip Erase (CE) (24)(18) Page Program (PP) (24)(19) 4 x I/O Page Program (4PP) (24)Program/Erase Flow(1) - verify by reading array data (26)Program/Erase Flow(2) - verify by reading program/erase fail flag bit (27)(20) Continuously program mode (CP mode) (28)(21) Deep Power-down (DP) (29)(22) Release from Deep Power-down (RDP), Read Electronic Signature (RES) (29)(23) Read Electronic Manufacturer ID & Device ID (REMS), (REMS2), (REMS4) (29)Table 6. ID Definitions (30)(24) Enter Secured OTP (ENSO) (30)(25) Exit Secured OTP (EXSO) (30)(26) Read Security Register (RDSCUR) (30)Security Register Definition (31)(27) Write Security Register (WRSCUR) (31)(28) Write Protection Selection (WPSEL) (32)BP and SRWD if WPSEL=0 (32)The individual block lock mode is effective after setting WPSEL=1 (33)WPSEL Flow (34)(29) Single Block Lock/Unlock Protection (SBLK/SBULK) (35)Block Lock Flow (35)Block Unlock Flow (36)(30) Read Block Lock Status (RDBLOCK) (37)(31) Gang Block Lock/Unlock (GBLK/GBULK) (37)(32) Clear SR Fail Flags (CLSR) (37)(33) Enable SO to Output RY/BY# (ESRY) (37)(34) Disable SO to Output RY/BY# (DSRY) (37)(35) Read SFDP Mode (RDSFDP) (38)Read Serial Flash Discoverable Parameter (RDSFDP) Sequence (38)Table a. Signature and Parameter Identification Data Values (39)Table b. Parameter Table (0): JEDEC Flash Parameter Tables (40)Table c. Parameter Table (1): Macronix Flash Parameter Tables (42)POWER-ON STATE (44)ELECTRICAL SPECIFICATIONS (45)ABSOLUTE MAXIMUM RATINGS (45)Figure 3. Maximum Negative Overshoot Waveform (45)CAPACITANCE TA = 25°C, f = 1.0 MHz (45)Figure 4. Maximum Positive Overshoot Waveform (45)Figure 5. OUTPUT LOADING (46)Table 7. DC CHARACTERISTICS (Temperature = -40°C to 85°C for Industrial grade, VCC = 2.7V ~ 3.6V) .47 Table 8. AC CHARACTERISTICS (Temperature = -40°C to 85°C for Industrial grade, VCC = 2.7V ~ 3.6V) 48 Timing Analysis (50)Figure 6. Serial Input Timing (50)Figure 7. Output Timing (50)Figure 8. Hold Timing (51)Figure 9. WP# Setup Timing and Hold Timing during WRSR when SRWD=1 (51)Figure 10. Write Enable (WREN) Sequence (Command 06) (52)Figure 11. Write Disable (WRDI) Sequence (Command 04) (52)Figure 12. Read Identification (RDID) Sequence (Command 9F) (53)Figure 13. Read Status Register (RDSR) Sequence (Command 05) (53)Figure 14. Write Status Register (WRSR) Sequence (Command 01) (53)Figure 15. Read Data Bytes (READ) Sequence (Command 03) (54)Figure 16. Read at Higher Speed (FAST_READ) Sequence (Command 0B) (54)Figure 17. 2 x I/O Read Mode Sequence (Command BB) (55)Figure 18. Dual Read Mode Sequence (Command 3B) (55)Figure 19. 4 x I/O Read Mode Sequence (Command EB) (56)Figure 20. Quad Read Mode Sequence (Command 6B) (56)Figure 21. 4 x I/O Read Enhance Performance Mode Sequence (Command EB) (57)Figure 22. Sector Erase (SE) Sequence (Command 20) (58)Figure 23. Block Erase (BE/EB32K) Sequence (Command D8/52) (58)Figure 24. Chip Erase (CE) Sequence (Command 60 or C7) (58)Figure 25. Page Program (PP) Sequence (Command 02) (59)Figure 26. 4 x I/O Page Program (4PP) Sequence (Command 38) (59)Figure 27. Continuously Program (CP) Mode Sequence with Hardware Detection (Command AD) (60)Figure 28. Deep Power-down (DP) Sequence (Command B9) (61)Figure 29. Read Electronic Signature (RES) Sequence (Command AB) (61)Figure 30. Release from Deep Power-down (RDP) Sequence (Command AB) (61)Figure 31. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90 or EF or DF) (62)Figure 32. Write Protection Selection (WPSEL) Sequence (Command 68) (62)Figure 33. Single Block Lock/Unlock Protection (SBLK/SBULK) Sequence (Command 36/39) (63)Figure 34. Read Block Protection Lock Status (RDBLOCK) Sequence (Command 3C) (63)Figure 35. Gang Block Lock/Unlock (GBLK/GBULK) Sequence (Command 7E/98) (63)RESET (64)Figure 36. RESET Timing (64)Table 9. Reset Timing (64)Figure 37. Power-up Timing (65)Table 10. Power-Up Timing (65)INITIAL DELIVERY STATE (65)OPERATING CONDITIONS (66)Figure 38. AC Timing at Device Power-Up (66)Figure 39. Power-Down Sequence (67)ERASE AND PROGRAMMING PERFORMANCE (68)DATA RETENTION (68)LATCH-UP CHARACTERISTICS (68)ORDERING INFORMATION (69)PART NAME DESCRIPTION (70)PACKAGE INFORMATION (71)REVISION HISTORY (73)256M-BIT [x 1/x 2/x 4] CMOS MXSMIO TM (SERIAL MULTI I/O) FLASH MEMORY FEATURESGENERAL• Serial Peripheral Interface compatible -- Mode 0 and Mode 3• 268,435,456 x 1 bit structure or 134,217,728 x 2 bits (two I/O mode) structure or 67,108,864 x 4 bits (four I/O mode) structure• 8192 Equal Sectors with 4K bytes each- Any Sector can be erased individually• 1024 Equal Blocks with 32K bytes each- Any Block can be erased individually• 512 Equal Blocks with 64K bytes each- Any Block can be erased individually• Power Supply Operation- 2.7 to 3.6 volt for read, erase, and program operations• Latch-up protected to 100mA from -1V to Vcc +1VPERFORMANCE• High PerformanceVCC = 2.7~3.6V- Normal read- 50MHz- Fast read- 1 I/O: 80MHz with 8 dummy cycles- 2 I/O: 70MHz with 4 dummy cycles- 4 I/O: 70MHz with 6 dummy cycles- Fast program time: 1.4ms(typ.) and 5ms(max.)/page (256-byte per page)- Byte program time: 9us (typical)- Continuously Program mode (automatically increase address under word program mode)- Fast erase time: 60ms (typ.)/sector (4K-byte per sector) ; 0.5s(typ.) /block (32K-byte per block); 0.7s(typ.) /block (64K-byte per block); 160s(typ.) /chip• Low Power Consumption- Low active read current: 45mA(max.) at 80MHz, 40mA(max.) at 70MHz and 30mA(max.) at 50MHz- Low active programming current: 25mA (max.)- Low active erase current: 25mA (max.)- Standby current: 200uA (max.)- Deep power down current: 80uA (max.)• Typical 100,000 erase/program cyclesSOFTWARE FEATURES• Input Data Format- 1-byte Command code• Advanced Security Features- BP0-BP3 block group protect- Flexible individual block protect when OTP WPSEL=1- Additional 4K bits secured OTP for unique identifier• Auto Erase and Auto Program Algorithms- Automatically erases and verifies data at selected sector- Automatically programs and verifies data at selected page by an internal algorithm that automatically times the program pulse width (Any page to be programed should have page in the erased state first.)• Status Register Feature• Electronic Identification- JEDEC 1-byte Manufacturer ID and 2-byte Device ID- RES command for 1-byte Device ID- Both REMS,REMS2, REMS4 commands for 1-byte Manufacturer ID and 1-byte Device ID• Support Serial Flash Discoverable Parameters (SFDP) modeHARDWARE FEATURES• SCLK Input- Serial clock input• SI/SIO0- Serial Data Input or Serial Data Input/Output for 2 x I/O mode and 4 x I/O mode• SO/SIO1- Serial Data Output or Serial Data Input/Output for 2 x I/O mode and 4 x I/O mode• WP#/SIO2- Hardware write protection or serial data Input/Output for 4 x I/O mode• HOLD#/SIO3- HOLD# pin or serial data Input/Output for 4 x I/O mode, an internal weak pull up on the pin- The weak pull up on the HOLD# pin will be disabled after QE bit is enabled, until next power-on cycle starts.- HOLD# function is only available on 16 SOP package• RESET#- Hardware reset pin• PACKAGE- 16-pin SOP (300mil)- 8 WSON (8x6mm)- All devices are RoHS CompliantTable 1. Additional FeaturesGENERAL DESCRIPTIONMX25L25635E is 268,435,456 bits serial Flash memory, which is configured as 33,554,432 x 8 internally. When it is in two or four I/O mode, the structure becomes 134,217,728 bits x 2 or 67,108,864 bits x 4. The MX25L25635E features a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial access to the device is enabled by CS# input.MX25L25635E, MXSMIO TM (Serial Multi I/O) flash memory, provides sequential read operation on whole chip and multi-I/O features.When it is in dual I/O mode, the SI pin and SO pin become SIO0 pin and SIO1 pin for address/dummy bits input and data output. When it is in quad I/O mode, the SI pin, SO pin, WP# pin and HOLD# pin become SIO0 pin, SIO1 pin, SIO2 pin and SIO3 pin for address/dummy bits input and data Input/Output.After program/erase command is issued, auto program/ erase algorithms which program/ erase and verify the specified page or sector/block locations will be executed. Program command is executed on byte basis, or page (256 bytes) basis, or word basis for Continuously Program mode, and erase command is executes on sector (4K-byte), block (32K-byte/64K-byte), or whole chip basis.To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read command can be issued to detect completion status of a program or erase operation via WIP bit.When the device is not in operation and CS# is high, it is put in standby mode and draws less than 200uA DC cur-rent.The MX25L25635E utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after 100,000 program and erase cycles.Additional FeaturesPart NameProtection and SecurityRead PerformanceFlexible or Individual block (or sector) protection4K-bit secured OTP1 I/O Read (80 MHz)2 I/O Read (70 MHz)4 I/O Read (70 MHz)MX25L25635EVVV VVAdditional FeaturesPart NameIdentifierRES (command: AB hex)REMS (command: 90 hex)REMS2(command: EF hex)REMS4(command: DF hex)RDID(command: 9F hex)MX25L25635E18 (hex)C2 18 (hex)C2 18 (hex)C2 18 (hex)C2 20 19 (hex)PIN CONFIGURATION16-PIN SOP (300mil)12345678HOLD#/SIO3VCC RESET#NC NC NC CS#SO/SIO1161514131211109SCLK SI/SIO0NC NC NC NC GNDWP#/SIO2PIN DESCRIPTIONSYMBOL DESCRIPTION CS#Chip SelectSI/SIO0Serial Data Input (for 1xI/O)/ Serial DataInput & Output (for 2xI/O or 4xI/O mode)SO/SIO1Serial Data Output (for 1xI/O)/SerialData Input & Output (for 2xI/O or 4xI/Omode)SCLK Clock InputWP#/SIO2Write protection: connect to GND orSerial Data Input & Output (for 4xI/Omode)HOLD#(1,2)/SIO3HOLD# pin or Serial Data Input & Output (for 4xI/O mode)VCC + 3.3V Power Supply GND GroundRESET#(3)Hardware Reset Pin, Active lowNC No Connection Note:(1). HOLD# function is only available on 16-SOPpackage.(2). The weak pull up on the HOLD# pin will be dis- abled after QE bit is enabled, until next power-oncycle starts.(3). RESET# pin has internal pull up.8-WSON (8x6mm) *CS#SO/SIO1WP#/SIO2GNDVCCRESET#/SIO3SCLK SI/SIO0BLOCK DIAGRAMDATA PROTECTIONMX25L25635E is designed to offer protection against accidental erasure or programming caused by spurious sys-tem level signals that may exist during power transition. During power up the device automatically resets the state machine in the standby mode. In addition, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific command sequences. The device also incorporates several fea-tures to prevent inadvertent write cycles resulting from VCC power-up and power-down transition or system noise.• Valid command length checking: The command length will be checked whether it is at byte base and completed on byte boundary.• Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before other command to change data. The WEL bit will return to reset stage under following situation:- Power-up- Reset# Pin driven low- Write Disable (WRDI) command completion- Write Status Register (WRSR) command completion- Page Program (PP, 4PP) command completion- Continuously Program mode (CP) instruction completion- Sector Erase (SE) command completion- Block Erase (BE, BE32K) command completion- Chip Erase (CE) command completion- Single Block Lock/Unlock (SBLK/SBULK) instruction completion- Gang Block Lock/Unlock (GBLK/GBULK) instruction completion- Write Security Register (WRSCUR) instruction completion- Write Protection Selection (WPSEL) instruction completion• Deep Power Down Mode: By entering deep power down mode, the flash device also is under protected from writing all commands except Release from Deep Power Down mode command (RDP) and Read Electronic Sig-nature command (RES).I. Block lock protection- The Software Protected Mode (SPM) uses (BP3, BP2, BP1, BP0) bits to allow part of memory to be protected as read only. The protected area definition is shown as table of "Protected Area Sizes", the protected areas are more flexible which may protect various area by setting value of BP0-BP3 bits. Please refer to table of "Protect-ed Area Sizes".- The Hardware Protected Mode (HPM) use WP#/SIO2 to protect the (BP3, BP2, BP1, BP0) bits and SRWD bit.If the system goes into four I/O mode, the feature of HPM will be disabled.- MX25L25635E provide individual block (or sector) write protect & unprotect. User may enter the mode with WPSEL command and conduct individual block (or sector) write protect with SBLK instruction, or SBULK for individual block (or sector) unprotect. Under the mode, user may conduct whole chip (all blocks) protect with GBLK instruction and unlock the whole chip with GBULK instruction.II. Additional 4K-bit secured OTP for unique identifier: to provide 4K-bit One-Time Program area for setting de -vice unique serial number - Which may be set by factory or system maker. Please refer to Table 3. 4K-bit Se-cured OTP Definition. - Security register bit 0 indicates whether the chip is locked by factory or not.- To program the 4K-bit secured OTP by entering 4K-bit secured OTP mode (with ENSO command), and going through normal program procedure, and then exiting 4K-bit secured OTP mode by writing EXSO command.- Customer may lock-down the customer lockable secured OTP by writing WRSCUR(write security register) command to set customer lock-down bit1 as "1". Please refer to table of "Security Register Definition" for secu -rity register bit definition and table of "4K-bit Secured OTP Definition" for address range definition.- Note: Once lock-down whatever by factory or customer, it cannot be changed any more. While in 4K-bit Se-cured OTP mode, array access is not allowed.Table 3. 4K-bit Secured OTP DefinitionTable 2. Protected Area SizesNote: The device is ready to accept a Chip Erase instruction if, and only if, all Block Protect (BP3, BP2, BP1, BP0) are 0.Address range Size Standard Factory Lock Customer Lock xxx000~xxx00F 128-bit ESN (electrical serial number)Determined by customerxxx010~xxx1FF3968-bitN/AStatus bitProtection Area BP3BP2BP1BP0256Mb00000 (none)0001 1 (2 blocks, block 510th-511th)0010 2 (4 blocks, block 508th-511th)0011 3 (8 blocks, block 504th-511th)0100 4 (16 blocks, block 496th-511th)0101 5 (32 blocks, block 480th-511th)0110 6 (64 blocks, block 448nd-511th)01117 (128 blocks, block 384th-511th)10008 (256 blocks, block 256th-511th)10019 (512 blocks, all)101010 (512 blocks, all)101111 (512 blocks, all)110012 (512 blocks, all)110113 (512 blocks, all)111014 (512 blocks, all)111115 (512 blocks, all)Memory OrganizationTable 4. Memory Organizationindividual blocklock/unlock unit:64K-byteDEVICE OPERATION1. Before a command is issued, status register should be checked to ensure device is ready for the intended op-eration.2. When incorrect command is inputted to this LSI, this LSI becomes standby mode and keeps the standby mode until next CS# falling edge. In standby mode, SO pin of this LSI should be High-Z.3. When correct command is inputted to this LSI, this LSI becomes active mode and keeps the active mode until next CS# rising edge.4. For standard single data rate serial mode, input data is latched on the rising edge of Serial Clock(SCLK) and data shifts out on the falling edge of SCLK. The difference of Serial mode 0 and mode 3 is shown as Figure 1.5. For the following instructions: RDID, RDSR, RDSCUR, READ, FAST_READ, RDSFDP , 2READ, DREAD, 4READ, QREAD, RDBLOCK, RES, REMS, REMS2, and REMS4 the shifted-in instruction sequence is followed by a data-out sequence. After any bit of data being shifted out, the CS# can be high. For the following instruc-tions: WREN, WRDI, WRSR, SE, BE, BE32K, HPM, CE, PP , CP , 4PP , RDP , DP , WPSEL, SBLK, SBULK, GBLK, GBULK, ENSO, EXSO, WRSCUR, EN4B, EX4B, ENPLM, EXPLM, ESRY , DSRY and CLSR the CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.6. During the progress of Write Status Register, Program, Erase operation, to access the memory array is neglect-ed and not affect the current operation of Write Status Register, Program, Erase.Figure 1. Serial Modes Supported (for Normal Serial mode)Note:CPOL indicates clock polarity of Serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which Serial mode is supported.SCLKMSBCPHA shift inshift outSI 01CPOL(Serial mode 0)(Serial mode 3)1SO SCLKMSBHOLD FEATURESHOLD# pin signal goes low to hold any serial communications with the device. The HOLD feature will not stop the operation of write status register, programming, or erasing in progress.The operation of HOLD requires Chip Select(CS#) keeping low and starts on falling edge of HOLD# pin signal while Serial Clock (SCLK) signal is being low (if Serial Clock signal is not being low, HOLD operation will not start until Serial Clock signal being low). The HOLD condition ends on the rising edge of HOLD# pin signal while Se-rial Clock(SCLK) signal is being low (if Serial Clock signal is not being low, HOLD operation will not end until Serial Clock being low), see Figure 2.The Serial Data Output (SO) is high impedance, both Serial Data Input (SI) and Serial Clock (SCLK) are don't care during the HOLD operation. If Chip Select (CS#) drives high during HOLD operation, it will reset the internal logic of the device. To re-start communication with chip, the HOLD# must be at high and CS# must be at low.Note 1: The HOLD feature is disabled during Quad I/O mode in 16-SOP package.COMMAND DESCRIPTION Table 5. Command SetsCOMMAND (byte)WREN (writeenable)WRDI (writedisable)RDID (readidentification)RDSR(read statusregister)WRSR(write statusregister)EN4B (enter4-byte mode)EX4B (exit4-byte mode)READ (readdata)Command(hex)06 04 9F 05 01 B7 E9 03InputCyclesData(8)ADD(24) DummyCyclesActionsets the(WEL) writeenable latchbitresets the(WEL) writeenable latchbitoutputsJEDECID: 1-byteManufacturerID & 2-byteDevice IDto read outthe valuesof the statusregisterto write newvalues tothe statusregisterto enter4-byte modeand set4BYTE bit as"1"to exit 4-bytemode andclear 4BYTEbit to be "0"n bytes readout until CS#goes highCOMMAND (byte)FAST READ(fast readdata)RDSFDP(Read SFDP)2READ (2x I/O readcommand)Note1DREAD(1I 2O read)4READ (4x I/O readcommand)QREAD(1I 4O read)4PP (quadpageprogram)SE (sectorerase)Command(hex)0B 5A BB 3B EB 6B38 20Input Cycles ADD(24)ADD(24)ADD(12)ADD(24)ADD(6)+indicator(2)ADD(24)ADD(6)+Data(512)ADD(24)DummyCycles884848Action n bytes readout until CS#goes highRead SFDPmoden bytes readout by 2 x I/O until CS#goes highn bytes readout by Dualoutput untilCS# goeshighn bytes readout by 4 x I/O until CS#goes highn bytes readout by Quadoutput untilCS# goeshighquad inputto programthe selectedpageto erase theselectedsectorCOMMAND (byte)BE (blockerase 64KB)BE 32K (blockerase 32KB)CE (chiperase)PP (Pageprogram)CP(Continuouslyprogrammode)DP (Deeppower down)RDP(Releasefrom deeppower down)RES (readelectronic ID)Command(hex)D8 52 60 or C7 02 AD B9 AB ABInput Cycles ADD(24)ADD(24)ADD(24)+Data(2048)ADD(24)+Data(16)DummyCycles24Action to erase theselected64KB blockto erase theselected32KB blockto erasewhole chipto programthe selectedpagecontinouslyprogramwholechip, theaddress isautomaticallyincreaseenters deeppower downmoderelease fromdeep powerdown modeto read out1-byte DeviceIDNote 1: It is not recommended to adopt any other code not in the command definition table, which will potentiallyenter the hidden mode.Note 2: In individual block write protection mode, all blocks/sectors is locked as defualt.Note 3: The number in parentheses afer "ADD" or "Data" stands for how many clock cycles it has. For example, "Data(8)" represents there are 8 clock cycles for the data in. Please note the number after"ADD" are based on 3-byte address mode, for 4-byte address mode, which will be increased.COMMAND (byte)REMS (readelectronic manufacturer & device ID)REMS2 (read ID for 2x I/O mode)REMS4 (read ID for 4x I/O mode)ENSO (enter secured OTP)EXSO (exitsecured OTP)RDSCUR (read security register)WRSCUR(write securityregister)Command(hex)90EF DF B1C12B 2FInputCycles ADD(8)ADD(8)ADD(8)DummyCycles16 16 16Actionoutput the Manufacturer ID & Device ID output the Manufacturer ID & Device ID output the Manufact-urer ID & device ID to enter the 4K-bit Secured OTP mode to exit the 4K-bit Secured OTP mode to read value of security register to set the lock-down bit as "1" (once lock-down, cannotbe updated)COMMAND (byte)ESRY (enable SO to output RY/BY#)DSRY (disable SO to output RY/BY#)CLSR (Clear SR Fail Flags)HPM (High Perform-ance Enable Mode)WPSEL (write protection selection)SBLK (singleblock lock)*Note 2SBULK (singleblock unlock)Command (hex)708030A36836 39 Input Cycles ADD(24)ADD(24)Dummy Cycles Actionto enable SO to output RY/BY# during CP mode to disable SO to output RY/BY# during CP mode clear security register bit 6 and bit 5Quad I/O high Perform-ance mode to enter and enable individal block protect mode individual block (64K-byte) or sector (4K-byte) write protect individual block (64K-byte) or sector (4K-byte)unprotectCOMMAND (byte)RDBLOCK(block protectread)GBLK (gang block lock)GBULK (gangblock unlock)Command(hex)3C 7E 98InputCycles ADD(24)Dummy Cycles Action read individual block or sector write protect statuswhole chip write protect wholechip unprotect(1) Write Enable (WREN)The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like PP, 4PP, CP, SE, BE, BE32K, CE, WRSR, WRSCUR, WPSEL, SBLK, SBULK, GBLK and GBULK, which are intended to change the device content, should be set every time after the WREN instruction setting the WEL bit.The sequence of issuing WREN instruction is: CS# goes low→ sending WREN instruction code→ CS# goes high. (Please refer to Figure 10)(2) Write Disable (WRDI)The Write Disable (WRDI) instruction is for resetting Write Enable Latch (WEL) bit.The sequence of issuing WRDI instruction is: CS# goes low→ sending WRDI instruction code→ CS# goes high. (Please refer to Figure 11)The WEL bit is reset by following situations:- Power-up- Reset# pin driven low- Write Disable (WRDI) instruction completion- Write Status Register (WRSR) instruction completion- Page Program (PP, 4PP) instruction completion- Sector Erase (SE) instruction completion- Block Erase (BE, BE32K) instruction completion- Chip Erase (CE) instruction completion- Continuously Program mode (CP) instruction completion- Single Block Lock/Unlock (SBLK/SBULK) instruction completion- Gang Block Lock/Unlock (GBLK/GBULK) instruction completion- Write Security Register (WRSCUR) instruction completion- Write Protection Selection (WPSEL) instruction completion(3) Read Identification (RDID)The RDID instruction is for reading the Manufacturer ID of 1-byte and followed by Device ID of 2-byte. The MXIC Manufacturer ID is C2(hex), the memory type ID is 20(hex) as the first-byte Device ID, and the individual Device ID of second-byte ID are listed as table of "ID Definitions". (Please refer to Table 6)The sequence of issuing RDID instruction is: CS# goes low→ sending RDID instruction code → 24-bits ID data out on SO→ to end RDID operation can use CS# to high at any time during data out. (Please refer to Figure 12)While Program/Erase operation is in progress, it will not decode the RDID instruction, so there's no effect on the cy-cle of program/erase operation which is currently in progress. When CS# goes high, the device is at standby stage.(4) Read Status Register (RDSR)The RDSR instruction is for reading Status Register. The Read Status Register can be read at any time (even in program/erase/write status register condition) and continuously. It is recommended to check the Write in Progress (WIP) bit before sending a new instruction when a program, erase, or write status register operation is in progress. The sequence of issuing RDSR instruction is: CS# goes low→ sending RDSR instruction code→ Status Register data out on SO (Please refer to Figure 13).The definition of the status register bits is as below:WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase/write status register progress. When WIP bit sets to 1, which means the device is busy in program/erase/write status register progress. When WIP bit sets to 0, which means the device is not in progress of program/erase/write status register cycle.WEL bit. The Write Enable Latch (WEL) bit, a volatile bit, indicates whether the device is set to internal write enable latch. When WEL bit sets to "1", which means the internal write enable latch is set, the device can accept program/erase/write status register instruction. When WEL bit sets to 0, which means no internal write enable latch; the de-vice will not accept program/erase/write status register instruction. The program/erase command will be ignored and will reset WEL bit if it is applied to a protected memory area.BP3, BP2, BP1, BP0 bits. The Block Protect (BP3, BP2, BP1, BP0) bits, non-volatile bits, indicate the protected area (as defined in Table 2) of the device to against the program/erase instruction without hardware protection mode being set. To write the Block Protect (BP3, BP2, BP1, BP0) bits requires the Write Status Register (WRSR) instruction to be executed. Those bits define the protected area of the memory to against Page Program (PP), Sector Erase (SE), Block Erase (BE) and Chip Erase (CE) instructions (only if all Block Protect bits set to 0, the CE instruction can be executed).QE bit. The Quad Enable (QE) bit, non-volatile bit, while it is "0" (factory default), it performs non-Quad and WP#, HOLD#, RESET# are enable. While QE is "1", it performs Quad I/O mode and WP#, HOLD#, RESET# are disabled. In the other word, if the system goes into four I/O mode (QE=1), the feature of HPM and HOLD (16SOP package) or RESET (8 WSON package) will be disabled.SRWD bit. The Status Register Write Disable (SRWD) bit, non-volatile bit, default value is "0". SRWD bit is operat -ed together with Write Protection (WP#/SIO2) pin for providing hardware protection mode. The hardware protection mode requires SRWD sets to 1 and WP#/SIO2 pin signal is low stage. In the hardware protection mode, the Write Status Register (WRSR) instruction is no longer accepted for execution and the SRWD bit and Block Protect bits (BP3, BP2, BP1, BP0) are read only. Status RegisterNote 1: see the Table 2 "Protected Area Size" in page 11.bit7bit6bit5bit4bit3bit2bit1bit0SRWD (status register write protect)QE (Quad Enable)BP3 (level of protected block)BP2 (level of protected block)BP1 (level of protected block)BP0 (level of protected block)WEL (write enable latch)WIP (write inprogress bit)1=statusregister write disable1= QuadEnable0=not QuadEnable(note 1)(note 1)(note 1)(note 1)1=write enable 0=not write enable 1=write operation 0=not in write operation Non-volatile bit Non-volatile bit Non-volatile bit Non-volatile bit Non-volatile bit Non-volatilebit volatile bitvolatile bit。
内外兼修Cursor_13赢信赖、得市场
03 □邮箱：****************黄 博专 题在我国的商用车配套动力制造体系中，上海柴油机股份有限公司（以下简称上柴）有着骄人的辉煌。
经历了21世纪改革大潮的冲击，伴随着体制的转变，上柴的新产品以低油耗、低排放和良好的环境适应性等优势，在我国的卡、客车市场上取得了令人瞩目的销售业绩。
“希望在未来更广阔的商用车市场上能继续看到上柴的身影，享受它带给我们的优质动力。
”在2012年12月28日举办的第二届“润迪杯”我信赖的商用车动力评选颁奖典礼上，一位物流从业者谈道。
评选的专家评审委员会也给予了上柴产品很高的评价：“可以骄傲地拥有，放心地使用。
”■ 本报记者 余梦洁 通讯员 韩华海/文 黄 博/图D 系列获广泛认可自从2008年进入上汽集团后，上柴在发扬光大优秀历史传统的同时，又学习和追寻了先进的上汽文化，依靠“科技兴企”，着力开发“新技术、高质量、低能耗”的产品，努力打造上汽商用车动力基地。
历史造就了上柴，也造就了上柴的产品。
上柴D 系列发动机以其成熟、稳定、可靠、高效、省油、低噪的特性赢得了市场，并得到了不同地区、不同用户的广泛认可。
据了解，D 系列发动机是上柴与AVL 公司联合设计的结晶，针对中国油品和用户使用习惯开发，是当前国内成熟发动机中设计年代较近、技术指标较先进的发动机，广泛运用于卡车、客车、工程机械、农业机械、电站、船舶等设备的动力配套。
依托D 系列柴油机成熟技术升级开发的电控柴油机，无论是机体还是燃油系统，都是发动机成熟、可靠、稳定的保证。
此外，如增压器、活塞、起动电机等电控柴油机的其他零部件也都采用国际知名品牌，为柴油机的可靠性提供了有利保障。
目前，D 系列柴油机的市场保有量已达到近50万台，低速大扭矩、动力性强劲、加速性能好，这是许多用过上柴发动机客户的共同呼声。
D 系列产品在执着与坚持中不断升级。
上柴公司充分依托公司多年积累的柴油机研发经验和技术实力，与美国西南研究院联合，对柴油机进行全面的性能试验开发，按照北美重型柴油机流程研发、试验，制造出新一代四气门重型柴油机，最大设计功率达400马力。
上菲红发动机产品介绍[1]
![上菲红发动机产品介绍[1]](https://img.taocdn.com/s3/m/96dea858be23482fb4da4c0d.png)
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Cursor9 Engine Main Performance 2 Cursor9 发动机主要特点 2
采用BOSCH最先进的高压共轨燃油系统，最高喷射压力可达到2200bar, 保 证最佳和精准喷射，充分燃烧。
8.7
210→297 kW - 1232→1600 Nm
CONSTRUCTION
MARINE
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L6 12/24V
NEF
AUTOMOTIVE INDUSTRIAL AGRICULTURE
5.9-6.7 3.9-4.5
73→202 kW - 440→930 Nm L4 8/16V 53→125 kW - 280→560 Nm
道路用车 道路用车 On-road vehicles (vans, trucks & busses)
F1C, NEF, CURSOR
NEF, CURSOR
移动、固定工业设备 固定工业设备 Mobile and Stationary industrial, Material Handling 农用 Agricultural 施工设备 施工设备 Construction Equipment 船泊用 Marine 发电机 发电机组 Power Generation
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Cursor 9发动机特性（汽车和工业用）
Cursor 9 Engine (Automotive & Industrial)
400 HP Number of cylinders Bore x stroke Swept volume Combustion type / injection Turbocharger Rated power Variable geometry (VGT) 294 kW @ 2100 rpm Rated torque Emission 1600 Nm @ 1200 rpm 280 kW @ 2100 rpm 1500 Nm @ 1500 rpm 380 HP 6 117 mm x 135 mm 8,7 l0 cc 4 valves, common rail Wastegate (WG) 250 kW @ 2100 rpm 1200 Nm @ 1500 rpm 215 kW @ 2100 rpm 1100 Nm @ 1500 rpm 340 HP 290 HP
外设天下血手幽灵光微动A91极速游戏鼠标体验评测
从体验血手幽灵V5游戏鼠标开始，就让我对血手的鼠标有了认识和好感，血手的鼠标在一百多元的价格里做出了自己足够多的特色，除了配置有血手宝典专业强大的软件驱动程序以外，在鼠标重要的手感、硬件性能方面也很有诚意，像V5还附送了备用脚贴等服务，很多细节让人感觉产品贴心有诚意。
这次新一代产品血手幽灵A91技术游戏鼠标相比V系统其它鼠标并没有简单的换壳复制，而是有了更加大胆、创新、新颖的设计，光微动，除此之外在其他一些细节也有很多特点，下面就来开箱一起体验一下这款新产品血手幽灵A91又能带给我们什么惊喜呢？！首先是开箱，产品的包装盒风格还是延续了血手V系统产品，包装颜色风格以红黑色为主，大大的一个血手印无处不在，不过这次增加了光微动字眼，这也是A91这次最大与众不同的卖点。
包装上有关于A91鼠标特点的介绍，可以看到主要有5点，光微动按键、光手轮、AVAGO A3050光学引擎的高刷新率、灵敏金靴、免驱七彩七模，关于这5大特色后面会一一实战体验，看看究竟如何。
血手幽灵A91鼠标采用了AVAGO A3050光学引擎，所以产品硬件性能也比较出色，分辨率100-4000 CPI5段调节，图像处理241万像素/秒，帧速率6666fps，加速度20g，循踪速度60fps，报告率125-1000Hz/秒，按键反应极限一毫秒以下，其中CPI和报告率都是大家平时提的比较多的参数部分，4000的CPI完全可以应付主流大屏幕显示器的分辨率。
关于光微动的耐用性厂家也有明确自信的说明，光微动开关是高达5000万次以上，光手轮开关高达1000万圈以上，鼠标脚垫行走300公里以上，这几个承诺指标在一百元多价位的产品里都是算比较高的。
产品的包装方式跟前面的V系列也是相同的礼盒式，大红色的内衬配色精美吉利，对产品有较好的保护，拆取收纳也方便，可以反复使用。
鼠标的附件主要有血手幽灵A91鼠标、一套两个血手不干胶贴、血手宝典5介绍、产品三包凭证卡。
S1D13305中文资料
元器件交易网
The information of the product number change
Starting April 1, 2001, the product number will be changed as listed below. To order from April 1, 2001 please use the new product number. For further information, please contact Epson sales representative.
SDU1374#0C SDU1375#0C SDU1376#0C SDU1376BVR SDU1378#0C
• S1D1380x Series New No. Previous No.
SDU1386#0C
New No.
S5U13806P00C
S5U13503P00C S5U13504P00C S5U13505P00C S5U13506P00C
S1D13305 Series S1D13305D00A S1D13305F00A S1D13305F00B
S1D1370x Series S1D13704F00A S1D13705F00A S1D13706B00A S1D13706F00A S1D13708 Series
• S1D1350x Series Previous No.
S5U13704P00C S5U13705P00C S5U13706P00C S5U13706B32R S5U13708P00C
• S1D13A0x Series Previous No.
SDU13A3#0C SDU13A4#0C
New No.
SN160系列变频器 使用说明书
目录1.安全注意事项 (1)1.1.安全信息定义 (1)1.2.警告标识 (1)1.3.安全指导 (2)2.产品简介 (4)2.1. 快速启动 (4)2.2.产品规格 (6)2.3.产品额定值 (8)2.4.结构示意图 (9)3.安装指导 (13)3.1. 机械安装 (13)3.2.标准接线 (16)3.3.配线保护 (21)4.键盘操作流程 (22)4.1.键盘简介 (22)4.2键盘显示 (23)4.3键盘操作 (24)5.功能参数一览表 (26)5.1F0组基本功能组 (27)5.2F1组启停控制 (29)5.3F2组V/F控制参数 (30)5.4F3组第一电机矢量控制参数 (31)5.5F4组矢量控制参数 (32)5.6F5组转矩控制参数 (33)5.7F6组输入端子 (34)5.8F7组输出端子 (36)5.9F8组故障与保护、加速过电流 (38)5.10F9组辅助功能 (42)5.12FB组控制优化参数 (46)5.13FC组PID功能 (47)5.14FD组摆频、定长和计数 (48)5.15FE组多段指令、简易PLC (48)5.16FF组功能码管理 (51)5.17P0组通讯参数 (51)5.18P2组AIAO校正 (52)5.19P3组AI曲线设定 (52)5.20P4组用户定制功能码 (53)5.21U0组监视参数组 (54)6.详细功能说明 (56)6.1F0组基本功能组 (56)6.2F1组启停控制 (63)6.3F2组VF控制参数 (71)6.4F3组第一电机矢量控制参数 (78)6.5F4组矢量控制参数 (79)6.6F5组转矩控制参数 (81)6.7F6组输入端子 (82)6.8F7组输出端子 (91)6.9F8组故障与保护、加速过电流 (95)6.10F9组辅助功能 (102)6.11FA组键盘与显示 (110)6.12FB组控制优化参数 (113)6.13FC组PID功能 (114)6.14FD组摆频、定长和计数 (118)6.15FE组多段指令、简易PLC (120)6.16FF组功能码管理 (123)6.17P0组通讯参数 (124)6.19P3组AI曲线设定 (126)6.20P3组用户定制功能码 (127)6.21U0组监视参数组 (128)7.故障预防 (129)7.1故障处理 (133)附录A.通讯协议 (137)A.1. MODBUS协议简介 (137)A.2. 本变频器应用方式 (137)A.3. 命令码及通讯数据描述 (142)A.4. 数据地址的定义 (143)A.5. 读写操作举例 (146)A.6. 常见通讯故障 (148)附录B. 技术数据 (149)B.1. 降额使用变频器 (149)B.2. CE 150B.3. EMC规范 (151)附录C.外围选配件 (152)C.1. 外围接线图 (152)C.2. 电源 (153)C.3. 电缆 (154)C.4. 断路器和电磁接触器 (155)C.5. 电抗器 (155)C.6. 制动电阻 (156)C.7. 尺寸图 (158)1.安全注意事项请用户在进行搬运、安装、运行、维护之前，仔细阅读本手册，并遵循本手册中所有安全注意事项。
用于 HP ProLiant Gen9 服务器的 HP UEFI Shell 用户指南
2 UEFI Shell 命令参考....................................................................................8
performancetiming参数解析 -回复
performancetiming参数解析-回复Performancetiming参数解析：以中括号内的内容为主题，写一篇1500-2000字文章，一步一步回答一、介绍现如今，在网络应用程序开发中，性能优化是至关重要的一环。
为了帮助开发者更好地分析和测量网页的性能，W3C提供了一个名为Performancetiming的API。
Performancetiming API提供了详细的浏览器性能数据，可用于衡量网页的加载速度和用户体验。
本文将深入研究Performancetiming参数，以帮助读者更好地使用和理解该API。
二、Performancetiming API概述Performancetiming API是W3C标准的一部分，旨在提供网页性能测量的标准方法。
Performancetiming API通过各种参数来记录和测量浏览器加载网页所需的时间。
这些参数被包装在一个PerformanceTiming对象中，该对象提供了详细的性能数据。
三、PerformanceTiming对象PerformanceTiming对象是Performancetiming API的核心。
它提供了一个包含各种性能计时参数的接口，可以通过JavaScript代码访问这些参数。
下面是一些常用的PerformanceTiming参数：1. navigationStart：这是浏览器处理当前网页的起始时间点，通常与用户在浏览器地址栏中输入URL的时间相吻合。
2. loadEventEnd：这是浏览器完成加载网页的时间，包括所有资源的下载和处理。
3. domInteractive：这是浏览器完成解析网页的时间，开始构建DOM树并将其与CSSOM进行合并。
4. domContentLoadedEventStart：这是浏览器开始解析网页中的异步脚本之前的时间点。
5. responseStart：这是浏览器接收到第一个字节的时间点，标志着服务器开始发送响应。
高手、高手与高高手！操控高手利器指导
数字族e文章作者：非风雾语责任编辑：一棵树操控高手利器指导高手、高手与高高手！键盘、鼠标是我们目前玩游戏彻底离不开的两件法宝。
也许你用惯了手里的那只“耗子”，体会不到操作感之间的差异，也许你已经习惯了那块“破盘子“，已经许久不曾沾染新的敲击感受，树希望这篇内容能唤起一位游戏高手的内心狂热，唤起一份只属于操作高手的享受。
曾经我们对于游戏键鼠的要求，主要是针对FPS、RTS等竞技游戏，要求的只是更高的性能参数，也就是拥有更高的DPI、CPI等等。
可随着越来越多外设厂商加大对游戏外设的投入，以及越来越多的竞技网游的出现或是网游中加入的竞技性，如今的游戏键鼠已经不仅仅着眼于硬件参数，同时也要求更多的快捷按键、更加出色的驱动软件，和更爽的手感！今天，我们就为大家介绍高中低端六款游戏键鼠产品，帮助大家找到适合自己的游戏键鼠。
双飞燕的鼠标，作为国产品牌中的一面旗帜，一向都以性价比出色受到许多用户的推崇。
当初CS刚刚在国内流行的时候，双飞燕滚轮鼠标便拥有了众多的追捧者。
甚至可以说，双飞燕滚轮鼠标开启了国内游戏专用外设的启蒙时代。
如今，在众多知名外设品牌充斥市场的年代，双飞燕凭借旗下X7系列游戏鼠标，依然拥有不错的市场份额，而这款XL-760H，正是双飞燕X7系列中的一款精品。
从性能参数上来看，这款鼠标在低端游戏鼠标中绝对不落下风。
这款鼠标采用了3600DPI的激光引擎，并支持从100DPI-3600DPI 的六档调速，刷新率达到7080帧/秒，忠实的记录玩家的每一次鼠标操作。
而且，在这款鼠标上，双飞燕还具有创新快按键回应速度，将按键响应时间由传统的16毫秒提升到了3毫秒，不仅能够延长按键使用寿命，也能够将用户的高手速更加迅速的体现出来。
此外，这款鼠标中的“神定块”设计，也是双飞燕的一个独有技术。
有了“神定块”，只要我们将鼠标提离桌面，光标就会定住不动，让我们的操作更加精确。
需要注意的是，双飞燕东方手拥有两个不同的型号，区别在于其编号为X-760H和XL-760H。
黄金比例达尔优em905游戏利器鼠标
黄金比例达尔优em905游戏利器鼠标黄金比例达尔优em905游戏利器鼠标目前市场上的游戏鼠标比较多，但其中多数都很同质化，乏善可陈。
达尔优是玩家熟悉的国内外设品牌，近期达尔优出品的游戏鼠标——EM905，定位入门级，但却有很多个性。
EM905采用了人体工学对称式设计，体型方面更适合国内主流玩家的手感，类肤质材质让鼠标拥有极佳的握感。
另外，EM905支持4000DPI，60ips移动速度以及20G加速度的内核配置满足游戏玩家的需求，滚轮，Logo灯，以及底部灯带具备1680万色RGB设定，通过驱动可以获得更多的调节。
最主要的是，EM905的黄金分割设计，让用户握住鼠标时更加畅快，鼠标的黄金分割点和人手关节的分割点几近重叠，给玩家带来更好的手感体验。
鼠标外观简介达尔优EM905造型设计保持流通的传统设计，而不是那种夸张的游戏风格。
EM905采用了人体工学的左右对称的造型设计，鼠标整体黑色，表面材质为细腻的类肤涂层，握感舒适。
三围尺寸为125×68×39mm，重量约为120g。
人体工程学设计流线型设计达尔优EM905侧裙部位采用了二色注塑工艺，大面积的橡胶防滑带来更好的手感，确保出汗时不易打滑。
达尔优EM905滚轮采用带有橡胶防滑纹路的设计，并且中间部分有镂空设计。
阻尼系数适中，通电后滚轮部位会有背光发出。
滚轮后方的DPI调节键，不同于我们常见的按键式调节，而是推杆式DPI调节键，需要调节时，玩家只需用中指向前或向后微微推动即可，非常方便。
鼠标默认DPI为500/1000/2000/3000/4000五档调节，通电后默认2000DPI档位，如果玩家想要使用自己的习惯设置，可通过驱动进行调节。
防滑贴片上方两个侧键默认设定为前进和后退键，后退键比较长，但是弧度比较大，在确保玩家方便按下的同时，避免误操作的发生，这项设计还是很贴心的。
达尔优EM905尾部透光LOGO设计新颖独特，它采用了马赛克拼接的形式亮出了达尔优的LOGO，通电后的效果让人眼前一亮。