ICC work shop cts

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Control Buffer/Inverter Selection

To set specific buffers/inverters to be used during each of the specific CTS optimizations:
It is recommended set_clock_tree_references to define all lists –references list1 (DRC buffering) –references list2 –sizing_only (skew balancing) –references list3 –delay_insertion_only

Meet the clock tree targets:

Maximum skew Minimum insertion delay
Targets are "nice to have" goals. If targets are not met, no violations will be reported.


Clock Tree Synthesis
Timing Optimization Routing of clock nets
Clock Tree Synthesis Timing Optimization Clock net routing
Routing
Note: The flow diagrams included in this unit represent an example flow, not the recommended flow

This command is used to model estimated clock skew, but can also be used to model the effects of clock jitter and to include some additional timing margin The specified setup number reduces the effective clock period of all paths captured by the specified clock and is used during synthesis to estimate clock behavior


Timing analysis post-CTS will also include the effects of this command, therefore:
Remove clock uncertainty if only skew is included remove_clock_uncertainty [all_clocks]
Placement
The “CTS phase” involves several key steps:

Setup steps to control CTS Optional Pre-CTS power optimization
Clock Tree Synthesis
CTS Setup

Pre-CTS Clock Tree Power Optimization
Estimated max cap/transition – no violations
High fanout nets:

Reset, Scan Enable synthesized with buffers

Clocks are still not buffered
4- 5
Starting Point before CTS
4- 4
Design Status Prior to Clock Tree Synthesis

Placement - completed Power and ground nets – prerouted Estimated congestion – acceptable Estimated setup timing – acceptable (~0ns slack)
Agenda
DAY 2
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Design Planning (Lab – continued)
3 4
Placement Clock Tree Synthesis
Synopsys 20-I-071-SSG-010
© 2010 Synopsys, Inc. All Rights Reserved
4- 1
Unit Objectives
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Clock
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Buffers are inserted to balance the loads, meet DRCs and minimize the skew
4- 7
Delay Cells Are Added to Meet Min. Insertion
set_driving_cell
4- 15
Remove “Skew” from Uncertainty

Your SDC constraints will most likely include a set_clock_uncertainty –setup <number> applied to each clock

There is no priority on how CTS uses the members from each list
If a list is not specified, by default all buffers/inverters (except dont_use cells) in the library can be used during its respective optimization
After completing this unit, you should be able to:

List the status of the design prior to CTS
Set up the design for clock tree synthesis Identify implicit clock tree start/end points and when explicit modifications are needed Control the constraints and targets used by CTS Execute the recommended clock tree synthesis and optimization flow Analyze timing and clock specifications post CTS 4- 2
General IC Compiler Flow
Synthesis

Design Setup
Design Planning Placement Clock Tree Synthesis Routing This Unit
Chip Finishing
4- 3
IC Compiler Clock Tree Synthesis Flow
4- 9
IC Compiler Clock Tree Synthesis Flow
Placement
Targets
Clock Tree Synthesis
CTS Setup
Constraints Control NDRs
Pre-CTS Clock Tree Power Optimization
Clock Tree Synthesis Timing Optimization Clock net routing

It is recommended to relax the clock skew target as much as possible

Reduces overall buffer count and run time

Specify minimum clock latencies as needed

OR
Reduce the uncertainty number by the estimated skew
4- 16
Defining CTS-Specific DRC Values
4- 11ts
Options can be set on all clocks defined in SDC (globally) or on a clock-by-clock basis. icc_shell>
set_clock_tree_options \ -target_early_delay 0.9 \ -target_skew 0.1

set_clock_tree_options \ –clock_trees clk1 -target_early_delay 0.9 set_clock_tree_options \ –clock_trees clk2 -target_skew 0.2
TIP: Use the GUI preview mode, then cut&paste the echo’d commands into your script.

Meet the clock tree Design Rule Constraints (DRC):