何志敏_可编程逻辑系统设计代码

实验二：一位全加器行为描述：process进程library ieee;use ieee.std_logic_1164.all;entity addall isport(a,b,c:in std_logic;sum,cout:out std_logic); end addall;architecture bhv of addall issignal m:std_logic_vector(2 downto 0); beginm<=c&a&b;process(a,b,c)beginif m="000" thensum<='0';cout<='0';elsif m="001" thensum<='1';cout<='0';elsif m<="010" thensum<='1';cout<='0';elsif m="011" thensum<='0';cout<='1';elsif m="100" thensum<='1';cout<='0';elsif m="101" thensum<='0';cout<='1';elsif m="110" thensum<='0';cout<='1';elsesum<='1';cout<='1';end if;end process;end bhv;一位全加器数据流描述：并行library ieee;use ieee.std_logic_1164.all;entity addall isport(a,b,c:in std_logic;sum,cout:out std_logic); end addall;architecture bhv of addall issignal m:std_logic_vector(2 downto 0); beginm<=c&a&b;sum<='0' when m="000" else'1' when m="001" else'1' when m="010" else'0' when m="011" else'1' when m="100" else'0' when m="101" else'0' when m="110" else'1';cout<='0' when m="000" else'0' when m="001" else'0' when m="010" else'1' when m="011" else'0' when m="100" else'1' when m="101" else'1' when m="110" else'1';end bhv;四位全加器网表描述：半加器：library ieee;use ieee.std_logic_1164.all; entity h_adder isport (a: in std_logic;b:in std_logic;co:out std_logic;so:out std_logic); end h_adder;architecture bhv of h_adder is beginso<=a xor b;co<=a and b;end bhv;或门：library ieee;use ieee.std_logic_1164.all; entity or2a isport (a，b: in std_logic;c: out std_logic); end or2a;architecture bhv of or2a is beginc<=a or b;end bhv;四位：library ieee;use ieee.std_logic_1164.all; entity h_adder isport (a: in std_logic;b:in std_logic;co:out std_logic;so:out std_logic); end h_adder;architecture bhv of h_adder is beginso<=a xor b;co<=a and b;end bhv;library ieee;use ieee.std_logic_1164.all; entity or2a isport (a: in std_logic;b:in std_logic;c: out std_logic); end or2a;architecture bhv of or2a is beginc<=a or b;end bhv;library ieee;use ieee.std_logic_1164.all; entity f_adder isport ( ain:in std_logic;bin:in std_logic;cin:in std_logic;cout:out std_logic;sum:out std_logic); end f_adder;architecture bhv of f_adder iscomponent h_adder isport ( a:in std_logic;b:in std_logic;co:out std_logic;so:out std_logic); end component;component or2a isport( a:in std_logic;b:in std_logic;c:out std_logic);end component;signal d,e,f:std_logic;beginu1:h_adder port map(a=>ain,b=>bin,co=>d,so=>e);u2:h_adder port map(a=>e,b=>cin,co=>f,so=>sum);u3:or2a port map(a=>d,b=>f,c=>cout);end bhv;实验三：38译码器：library ieee;use ieee.std_logic_1164.all;entity m3_8de isport(a:in std_logic_vector(2 downto 0);en:in std_logic_vector(2 downto 0);b:out std_logic_vector(7 downto 0));end m3_8de;architecture bhv of m3_8de issignal m:std_logic_vector(5 downto 0);beginm<=en&a;with m selectb<="00000001" when "100000","00000010" when "100001","00000100" when "100010","00001000" when "100011","00010000" when "100100","00100000" when "100101","01000000" when "100110","10000000" when "100111","00000010" when others;end bhv;阴极管：library ieee;use ieee.std_logic_1164.all;entity guan isport(a:in std_logic_vector(3 downto 0);b:out std_logic_vector(6 downto 0));end guan;architecture bhv of guan isbeginb<="0111111" when a="0000" else"0000110" when a="0001" else"1011011" when a="0010" else"1001111" when a="0011" else"1100110" when a="0100" else"1101101" when a="0101" else"1111101" when a="0110" else"0000111" when a="0111" else"1111111" when a="1000" else"1101111" when a="1001" else"0000000";end bhv;实验四：四位加减法计数器:LIBRARY IEEE;use ieee.std_logic_unsigned.all;USE IEEE.STD_LOGIC_1164.ALL;entity counter4 isport(clk,rst,updn:in std_logic;q:out std_logic_vector(3 downto 0)); end counter4;architecture behave of counter4 isbeginprocess(clk,rst)variable tmp_q:std_logic_vector(3 downto 0);beginIF rst = '1' THENtmp_q := (others=>'0');elsif clk='1' and clk'eventthenIF updn = '1' THENtmp_q := tmp_q + 1;ELSE tmp_q := tmp_q -1;END IF;q <= tmp_q;END IF;end process;end behave;一秒钟定时器：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity timers isport(clk:in std_logic;q:out std_logic);end timers;architecture bhv of timers isbeginprocess(clk)variable m:integer range 0 to 50000000;beginif(clk='1' and clk'event) then m:=m+1;if m<=24999999 then q<='0';elsif m<=49999999 then q<='1';else m:=0;end if;end if;end process;end bhv;8位左移移位寄存器：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity yiwei isgeneric(n:natural:=8);port(clk,a:in std_logic;q:out std_logic_vector(n-1 downto 0));end yiwei;architecture bhv of yiwei isbeginprocess(clk)variable m:std_logic_vector(n-1 downto 0);beginif clk='1' and clk'event thenm:=m(n-2 downto 0)&a;（右移就a&m(n-1 downto 1)）q<=m;end if;end process;end bhv;三、实验内容。