verilog可综合有限状态机的4种写法(夏文宇书注)

verilog可综合有限状态机的4种写法（夏文宇书注）
第一种：自然编码
module fsm1(
input i_clk,
input rst_n,
input A,
output reg K1,
output reg K2,
output reg [1:0] state
);
parameter Idle=2'b00,
Start=2'b01,
Stop=2'b10,
Clear=2'b11;
[email=always@(posedge]always@(posedge[/email] i_clk)
if(!rst_n)
begin
state<=Idle;
K2<=0;
K1<=0;
end
else
case(state)
Idle:if(A)
begin
state<=Start;
K1<=0;
end
else
begin
state<=Idle;
K2<=0;
K1<=0;
end
Start:if(!A)
state<=Stop;
else
state<=Start;
Stop:if(A)
begin
state<=Clear;
K2<=1;
else
begin
state<=Stop;
K2<=0;
K1<=0;
end
Clear:if(!A)
begin
state<=Idle;
K1<=1;
K2<=0;
end
else
begin
state<=Clear;
K2<=0;
K1<=1;
end
default:
state<=Idle;
endcase
endmodule
这种大家应该都熟悉的
第二种：采用独热编码，据说其可靠性和速度都不错module fsm2(
input i_clk,
input rst_n,
input A,
output reg K1,
output reg K2,
output reg [3:0] state
);
parameter Idle=4'b1000;
parameter Start=4'b0100;
parameter Stop=4'b0010;
parameter Clear=4'b0001;
always@(posedge i_clk)
begin
if(!rst_n)
state<=Idle;
K2<=0;
K1<=0;
end
else
case(state)
Idle:if(A)
begin
state<=Start;
K1<=0;
end
else
begin
state<=Idle;
K2<=0;
K1<=0;
end
Start:if(!A)
state<=Stop;
else
state<=Start; Stop:if(A)
begin
state<=Clear;
K2<=1;
end
else
begin
state<=Stop;
K1<=0;
K2<=0;
end
Clear:if(!A)
begin
state<=Idle;
K2<=0;
K1<=1;
end
else
begin
state<=Clear;
K2<=0;
K1<=0;
end
default:state<=Idle;
endcase
end
endmodule
第三种：把输出直接指定为状态码，即把状态码的指定和状态机的输出联系起来，状态的变化直接用做输出
据说可以提高输出信号的开关速度并节省电路资源（希望了解其机理的高手们能够解说下时怎样提高开关速度的？）
module fsm3(
input i_clk,
input rst_n,
input A,
output K1,
output K2,
output reg [4:0] state
);
assign K2=state[4];
assign K1=state[0];
parameter Idle =5'b00000;
parameter Start =5'b00010;
parameter Stop =5'b00100;
parameter StopToClear =5'b11000;
parameter Clear =5'b01010;
parameter ClearToIdle =5'b00111;
always@(posedge i_clk)
if(!rst_n)
begin
state<=Idle;
end
else
case(state)
Idle:if(A)
state<=Start;
else
state<=Idle;
Start:if(!A)
state<=Stop;
else
state<=Start;
Stop:if(A)
state<=StopToClear;
else
state<=Stop;
StopToClear:state<=Clear;
Clear:if(!A)
state<=ClearToIdle;
else
state<=Clear;
ClearToIdle:state<=Idle;
default:state<=Idle;
endcase
endmodule
第四：把状态的变化和输出开关的控制分成两部分考虑module fsm4(
input i_clk,
input rst_n,
input A,
output reg K1,
output reg K2,
output reg[1:0] state
);
//reg [1:0] state;
reg [1:0] nextstate;
parameter Idle=2'b00,
Start=2'b01,
Stop=2'b10,
Clear=2'b11; always@(posedge i_clk)
if(!rst_n)
state<=Idle;
else
state<=nextstate;
always@(state or A)
case(state)
Idle:if(A)
nextstate=Start;
else
nextstate=Idle;
Start:if(!A)
nextstate=Stop;
else
nextstate=Start;
Stop:if(A)
nextstate=Clear;
else
nextstate=Stop;
Clear:if(!A)
nextstate=Idle;
else
nextstate=Clear;
default:nextstate=2'bxx; endcase
always@(state or rst_n or A) if(!rst_n)
K1<=0;
else
if(state==Clear&&!A)
K1<=1;
else
K1<=0;
always@(state or rst_n or A) if(!rst_n)
K2<=0;
else
if(state==Stop&&A)
K2<=1; else
K2<=0; endmodule。