第一讲,有源器件、无源元件

模拟集成电路设计徐化E-mail:hxu@1教材与参考书•教材：–Behzad Razavi，“Design of Analog CMOSIntegrated Circuits”, （英文版或者中文版）•参考书：–P.R. Gray, “Analysis and Design of AnalogIntegrated Circuits”, Fourth Edition，高等教育出版社(影印版)–P.E. Allen, “CMOS Analog Circuit Design”,Second Edition, 电子工业出版社2课程内容3考核z课后作业：10％z课程设计：40％z期末考试：50％z作业：完成给满分z课程设计：设计思路是否正确、设计过程是否规范完整、是否具有创新性、设计和仿真结果、文档、以及报告质量。

z期末考试：闭卷考试4课程设计•采用恒温电流源作偏置电路的运算放大器•时间：实验课完成，第10周前提交中期进展报告，第14周前提交最终报告。

•提供的资源：Spectre的帮助文档（中文）、仿真工艺库文件、库文件使用说明。

5射频接收器•Why so many RF and analog building blocks?•In other words, why not just put the ADC right after the antenna?7模拟集成电路设计流程8Electrical Design •Electrical design :the process of goingfrom the specifications to a circuit solution.The electrical design requires active andpassive device electrical models for-Creating the design-Verifying the design-Determining the robustness of thedesign9Physical Design•Physical design is the process of representing the electrical design in a layout consisting of many distinct geometrical rectangles at.various level layers10Physical Design Process• 1.) The inputs are the W/L values and the schematic Æ• 2.) A CAD tool is used to enter the various geometries.Æ• 3.) During the layout, ensuring the robustness and reliability(DRC)Æ• 4.) layout versus schematchÆ• 5.) parasitics can be extracted.Æ– a.) Capacitance from a conductor to ground– b.) Capacitance between conductors– c.) Bulk resistance• 6.) Pre-simulation11Packaging•Function of Package–Protect IC–Power IC–Cool IC–Provide the electrical and mechanicalconnection between IC and the outside world.•Package Process–12Testing•Objective: To compare the experimental performance with the specifications and/or simulation results.•Types of tests:–Functional –verification of the nominal specifications –Parametric –verification of the characteristics towithin a specified tolerance–Static –verification of the static (AC and DC)characteristics of a circuit or system–Dynamic –verification of the dynamic (transient)characteristics of a circuit or system13“Digital”VS “Analog”•Abstraction in digital is Boolean logic (1’s, 0’s)–Works because of noise margins•At a higher level, it’s gates and registers (RTL)Digital layout is often automated•Abstraction in analog is the device model–(BSIM is a few thousand lines long)•At a higher level, it’s the (opamps) (filters) (comparators)–Abstraction depends on the problem you’re solving•Analog layout is usually hand crafted11“Analog”VS “RF”•RF = “Analog with inductors”•RF signal is usually narrowband (i.e., sinusoidal)•Tuned circuit techniques used for signal processing.•RF impedance levels are relatively low–Can’t make antenna impedance too high•Analog impedances are high for voltage gain.–Voltage/current gain versus power gain.1213混合信号•“Mixed-signal”analog is often discrete time (sampled).•Many building blocks involve analog and digital circuit co-design :PLLs, ADCs, etc.•Sometimes hard to even distinguish between analog and digital–Is VCO analog, or digital?提要•二极管的伏安特性与电容特性•MOS管的大信号特性、小信号等效模型、特征频率、短沟道效应•集成电阻器•集成电容器14二极管的伏安特性qkT V V T d =>>T d T d V V S V V S d eI e I I //)1(≈−=z 正向工作区：导通电压：V V V on 7.0~6.0≈z 反向工作区：T d V V −<<ST V d V S d I e I I −≈−=)1(/为耗尽区可以承受的最大电场强度，对于Si 材料，其值约为为没有击穿机制发生时的反向电流n ＝3～6二极管的伏安特性:击穿2max 2)(E N qN N N BV D A D A +≅εmax E cm V X /1035R n d R RA I BV V MI I )/(11−==R I二极管的电容特性z 势垒电容：空间电荷区电荷随外加电压的变化对于突变结，n=2；对于缓变结，n=3；为没有外加电压时的势垒电容 为内建电势n d j j V C C 001φ−=0j C 0φ20ln i D A T n N N V =φz 扩散电容：空间电荷区以外大约一个扩散长度范围内过剩载流子随外加电压变化，仅在正向偏压下有显著作用提要•二极管的伏安特性与电容特性•MOS管的大信号特性、小信号等效模型、特征频率、短沟道效应•集成电阻器•集成电容器15MOS管概述NMOS：B接VSS PMOS：B接VDD 耗尽型器件MOS管概述MOS管的大信号特性沟道长度调制因子与沟道长度的关系LV L L DS 1/∝∆=λ)1(2')1()(2'22DS ov DS t GS D V V LW k V V V L W k I λλ+=+−=21LL V I DS D ∝∝∂∂λz 饱和区：z 强反型与弱反型的划分：MOS 管的弱反型工作区)]exp(1)[exp(T DS T t GS t D V V nV V V I L W I −−−=T DS V V 3>T t GS ov nV V V V 2=−=v E c≈MOS 管的电压限制z pn 结击穿：漏－衬底pn 结由于雪崩效应而击穿，非破坏性z 源漏穿通：源漏极的耗尽区相连，电流逐渐增加，非破坏性z 热载流子：由于水平或垂直电场的作用，热载流子获得足够的速度注入氧化层，增加栅电流，改变阈值电压，破坏性z 氧化层击穿：垂直场，破坏性，ESD 保护cm V cm V /107~/10666××MOS管的小信号模型（饱和区）I∂WMOS管的电容效应CWLMOS管的电容效应MOS 管的电容效应：源漏耗尽区电容jswj totle C E W WEC C )(2++=2/100)1(φSB sb sb V C C +=2/100)1(φDB db db V C C +=z C j ：单位面积底盘电容z C jsw ：单位长度侧墙电容MOS管的完整小信号模型MOS 管的特征频率gsgd gb gs i v C C C s i )(++=gsm o v g i ≈)(gd gb gs m i o C C C s g i i ++≈)()(gd gb gs m i o C C C j g j i i ++≈ωωgd gb gs m T C C C g ++=ωgd gb gs m T T C C C g f ++==πωπ2121)(25.12t GS n T V V Lf −=πµMOS工艺下的双极型器件z垂直PNP管集电极是衬底，必须接最低电位，限制了其应用MOS工艺下的双极型器件z水平PNP管伴随着寄生的垂直PNP管，基区宽度为MOS的沟道长度，性能随着沟道长度的减小而提高提要•二极管的伏安特性与电容特性•MOS管的大信号特性、小信号等效模型、特征频率、短沟道效应•集成电阻器•集成电容器16MOS 工艺中的集成电阻器：多晶电阻z 形成MOS 管栅极的多晶硅作电阻，精度受工艺偏差影响较大z 多晶硅电阻做在场区上z 方块电阻较大：□/1000~300ΩΩ场氧N+N+集成电阻器的设计z阻值计算：R=R□•L/Wz修正：端头修正：端头处电力线弯曲，电流从引线孔正对着电阻条的一边流入，需要引入端头修正因子k1表示整个端头对总电阻方数的贡献¾根据不同的电阻条宽和端口形状，端头修正因子可以在0到0.9之间变化。