PLL Design Handbook

PLL Design Handbook1. Basic Theory1>The transfer functionAny second order PLL(means your loop filter is second order) will have the following transfer characteristics diagram.Fig. 1 PLL Transfer characteristicsTo me, this picture simply means:∙Wmod/Wn is the input jitter phase change over natural frequency(which is a fixed value decided by the loop design), the cut off frequency happens whenWmod/Wn =1, which means the Wn is actually loop bandwidth. Talking in asimple word, any jitter frequency(phase) will be following when it is less thanWn, and will be ingnored when it is bigger than Wn.∙In our case, we would like to choose Wn=2π100K Hz, since the cut off freq=100K Hz.∙There will be over-damping when damping factor D (ζ ) is not chosen correctly, which in consequence affect the stability of this loop. Based on thisdiagram and other material, we would like to choose this ζ=0.707 .∙First order LP is very hard to make it stable, and it is sensitive to change of gain and circuit component.2>Is My PLL Stable?∙PLL is 2nd-order system similar to mass-spring-dashpot or RLC circuit.∙PLL may be stable or unstable depending on phase margin (or damping factor).∙Phase margin is determined from linear model of PLL in frequency-domain.∙Find phase margin/damping using MATLAB, loop equations, or simulations.∙Stability affects phase error, settling, jitter.3>What Does PLL Bandwidth Mean?∙PLL acts as a low-pass filter with respect to the reference.∙Low-frequency reference modulation (e.g. spread spectrum clocking) is passed to the VCO clock.∙High-frequency reference jitter is rejected.∙“Bandwidth” is the frequency at which the PLL begins to lose lock with the reference (-3dB).∙PLL acts as a high-pass filter wrt VCO noise.∙Bandwidth affects phase error, settling, jitter.∙Lower bandwidth -> lower overshoot∙Higher over sampling ratio(Wref / Wn) -> lower bandwidth4>What determines bandwidth and stability?∙Damping factor (measure of stability)∙Natural frequency (measure of bandwidth)∙Damping factor and natural frequency can be set independently by LPF resistor5>The loop gainThe loop gain means the amount of phase change between the input signal and VCO signal for a shift in input signal frequency. (assuming the loop remains in lock). In servo theory, this is called the “velocity error coefficient ”6>Close loop bandwidth & Unit gain frequencyThe Nature frequency Wn come from you loop transfer equation, we haveClose loop bandwidth Wb is also called the -3DB bandwidth of a loop, its relationship to nature frequency is :When cata = 0.707, Wb = 2.06 Wnwhile the unit gain Wc frequency is the freq where loop gain is 1(open loop), as shown below:Its relationship with nature frequency (loop bandwidth) isAs a rule of thumb, we can assume cata to be around 1, then you haveWc = 2Wn , Wb=2.5Wn2. Digital PLL General AnalysisThe block diagram of a completely implemented 2rd order DPLL is shown below:Fig. 2 DPLL block diagramThis is a system that mapped to Z domain(since it is a discrete system), Z-1 means delay of one clock cycle, it is a register in real design1> An IIR filter has been designed as the loop-filter, H1(z) is its transferFunction2> A digitally-controlled VCO, or a discrete-time-oscillator, will have H2(z) as its transfer functionwhere, Gpd is the GAIN of the phase detector3> With these building blocks of the DPLL system, its closed-loop transfer function can be written as:4> The format of this transfer function can be rewritten as:5> By comparing the characteristic equation (z) of a DPLL (EQ020) the following equation can be constructed:6> And g1 and g2 can be resolved based on (EQ027) and (EQ022):7> With (EQ026) and (EQ028), the model of a DPLL is completely derived.3. Digital PLL Parameter Detail calculationsWe will start with the DPLL parameter calculation of 622M CDR macro used currentlyDFILT1_Arch025_phase1v1 Fig. 3 The actual CDPLL phase detector and loop filter structureAnalysis:1>If we simplify this diagram, the PFD and LF structure of CDPLL is exactly thesame as above figure 1, where d8to16v1, add5V4 and prsclrv1 become PFD,while freq1v1 and phase1v1 become loop filter.2>For the phase detector’s gain, the four phase input 155M clock give use four bitsof data and four bits of edge information. It is equivalent to one 622M clocksamples a 622Mbps data, which give one sample each clock. In that case, if the PD overflow limit (limar) = 10, we haveGpd = 1/10 =0.1 (ED01)3>For VCO gain, I have not idea at this moment, let it for later calculation(ED02)4> According to the analysis in chapter 1, we also should haveWn=2π100K (ED03) andζ=0.707 (ED04)5>Now using (EQ028), we haveWe haveg1 = 1-0.9985713=0.00142g2 = 1.9985713-1.9985708=1E-6 (ED05)6>Since Gpd = 0.1, we haveG1 = 0.0142G2 = 1E-57>If we assume the dumping factor always be 0.707, changing Wn will have thefollowing resultPlease be noted that the 3DB cut off freq is 1 ~ 2 times of its natural freq, I justdon’t know, different people got different option.8> Now I want to refer the current design, we have G1 = 5632/(2E+16) = 0.085G2 = 2 / (2E+14) =1.22E-4 (current when inc=2) or = 4/(2E+14) = (2.44-E4 (previously when inc=4)9> Refer to above table, we have Fn ~ 100K, now look at the typical device jittertransfer result from CDR design doc, the -3DB is around 70KHz, you have to refer to SDH requirement for detail for jitter transfer.。