EN29SL800B-70KI中文资料(Eon Silicon)中文数据手册「EasyDatasheet - 矽搜」

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Eon Silicon Solution IC产品顶部标记说明书

PurposeEon Silicon Solution Inc. (hereinafter called “Eon”) is going to provide its products’ top marking on ICs with < cFeon > from January 1st, 2009, and without any change of the part number and the compositions of the ICs. Eon is still keeping the promise of quality for all the products with the same as that of Eon delivered before. Please be advised with the change and appreciate your kindly cooperation and fully support Eon’s product family.Eon products’ New Top MarkingcFeon Top Marking Example:Continuity of SpecificationsThere is no change to this data sheet as a result of offering the device as an Eon product. Any changes that have been made are the result of normal data sheet improvement and are noted in the document revision summary, where supported. Future routine revisions will occur when appropriate, and changes will be noted in a revision summary.Continuity of Ordering Part NumbersEon continues to support existing part numbers beginning with “Eon” and “cFeon” topmarking. To order these products, during the transition please specify “Eon top marking” or “cFeon top marking” on your purchasing orders.For More InformationPlease contact your local sales office for additional information about Eon memory solutions.Distinctive Characteristics MCP Features■Power supply voltage of 2.7 V to 3.3V ■High performance- 70 ns■Package- 7 x 9 x 1.2mm 56 ball FBGA ■Operating Temperature - 25°C to +85°CGeneral DescriptionThe EN71GL series is a product line of stacked Multi-Chip Product (MCP) packages and consists of:■ EN29GL128 (Page mode) Flash memory with lowest address sector protected.■Pseudo SRAM.For detailed specifications, please refer to the individual datasheets listed in the following table.Device DocumentNOR Flash EN29GL128Pseudo SRAM ENPSL32Product Selector Guide128Mb Flash MemoryDevice-Model#EN71GL128B0pSRAM density32M pSRAMFlash Access time 70ns pSRAM Access time 70nsPage read Access time25ns pSRAM Page read Accesstime25nsPackage56 FBGAMCP Block DiagramConnection DiagramMCP Flash-only Addresses Shared Addresses EN71GL128B0 A22, A21 A20 – A0Pin DescriptionSignal Description A22–A0 23 Address Inputs (Common)DQ15–DQ0 16 Data Inputs/Outputs (Common)CE1#f Chip Enable 1 (Flash)CE1#ps Chip Enable 1 (pSRAM)CE2ps Chip Enable 2 (pSRAM)OE# Output Enable (Common)WE# Write Enable (Common)RY/BY# Ready/Busy Output (Flash)UB# Upper Byte Control (pSRAM)LB# Lower Byte Control (pSRAM)RESET# Hardware Reset Pin, Active Low (Flash)WP#/ACC Hardware Write Protect/Acceleration Pin (Flash)V CC f Flash 3.0 volt-only single power supplyV CC ps pSRAM Power SupplyV SS Device Ground (Common)NC Pin Not Connected InternallyLogic SymbolORDERING INFORMATIONEN71GL128 B0 ―70 C W PPACKAGING CONTENT(Blank) = ConventionalP = Pb FreeTEMPERATURE RANGEW = Wireless (-25°C to +85°C)PACKAGEC =56-Ball Fine Pitch Ball Grid Array (FBGA)0.80mm pitch, 7mm x 9mm packageSPEED70 = 70nspSRAM densityB0 = 32M pSRAMBASE PART NUMBEREN = Eon Silicon Solution Inc.71GL = Multi-chip Product (MCP)3.0V Page Mode Flash Memory and RAM128 = 128 Megabit (8M x 16)PACKAGE MECHANICAL56-ball Fine-Pitch Ball Grid Array (FBGA) 7 x 9 mm Package, pitch: 0.8mm, ball: 0.4mmNote : Controlling dimensions are in millimeters (mm).Revisions ListRevision No Description DateA Initial Release 2009/05/27B Update EN29GL128 (Page mode) Flash memory with lowest address sector2009/11/23 protected on page 2.。

EN29LV640L-90TIP资料

FEATURES• Single power supply operation- Full voltage range: 2.7 to 3.6 volts for read, erase and program operations• Low power cons umption (typical values at 5 MHz)- 9 mA typical active read current- 20 mA typical program/erase current- Less than 1 μA current in standby or automatic sleep mode.• JEDEC standards compatible- Pinout and software compatible with single-power supply Flash standard• Manufactured on 0.18μm process technology• Flexible Sector Architecture:- One hundred and twenty-eight 32K-Word /64K-byte sectors.• Minimum 100K program/erase endurance cycles.• High performance for program and erase - Word program time: 8µs typical - Sector Erase time: 500ms typical - Chip Erase time: 64s typical • Package Options - 48-pin TSOP - 48-ball FBGASoftware features: • Sector Group Protection- Provide locking of sectors to prevent program or erase operations within individual sectors - Additionally, temporary Sector GroupUnprotect allows code changes in previously protected sectors. • Standard DATA# polling and toggle bits feature• Unlock Bypass Program command supported • Sector Erase Suspend / Resume modes: Read and program another Sector during Sector Erase Suspend Mode• Support JEDEC Common Flash Interface (CFI).Hardware features:• Pin compatible to lower density, easy replacement for code expansion. • RESET# hardware reset pin- Hardware method to reset the device to read mode. • WP#/ACC input pin- Write Protect (WP#) function allowsprotection of first or last 32K-word sector, regardless of previous sector protect status - Acceleration (ACC) function provides accelerated program timesGENERAL DESCRIPTIONThe EN29LV640H/L / EN29LV640U is a 64-Megabit ( 4Mx16 ), electrically erasable, read/write non-volatile flash memory. Any word can be programmed typically in 8µs. This device is entirely command set compatible with the JEDEC single-power-supply Flash standard.The EN29LV640H/L / EN29LV640U is designed to allow either single Sector or full Chip erase operation, where each Sector Group can be protected against program/erase operations or temporarily unprotected to erase or program. The device can sustain a minimum of 100K program/erase cycles on each Sector.EN29LV640 64 Megabit (4M x 16-bit ) CMOS 3.0 Volt-only, Uniform Sector Flash MemoryPRODUCT SELECTOR GUIDEProduct Number EN29LV640H/LEN29LV640USpeed OptionFull Voltage Range: V CC =2.7 – 3.6 V90 90 Max Access Time (ns) 90 90 Max CE# Access Time (ns) 90 90 Max OE# Access Time (ns) 3535BLOCK DIAGRAMWE# CE# OE#State ControlCommand RegisterErase Voltage GeneratorInput/Output BuffersProgram Voltage GeneratorChip Enable Output EnableLogicData LatchY-Decoder X-Decoder Y-GatingCell MatrixTimerV CC DetectorA21-A0V CC V SS DQ15-DQ0Address LatchSector Protect SwitchesSTBSTBWP#/ ACC RY/BY#RESET#CONNECTION DIAGRAMSTABLE 1. PIN DESCRIPTIONLOGIC DIAGRAMDQ15 – DQ0A21 – A0WE#CE#RY/BY#OE#RESET#WP# / ACCPin Name Function A21-A0 22 Address inputs DQ15-DQ0 16 Data Inputs/Outputs CE# Chip Enable Input OE# Output Enable Input WE#Write Enable InputWP#/ACC Write Protect / Acceleration Pin RY/BY# Ready/Busy status output RESET# Hardware Reset Input Pin V cc Supply Voltage (2.7-3.6V) V ss GroundNCNot Connected to anythingORDERING INFORMATIONEN29LV640 H ─90 T C PPACKAGING CONTENT(Blank) = ConventionalP = Pb FreeTEMPERATURE RANGEI = Industrial (-40°C to +85°C)C = Commercial (0°C to +70°C)PACKAGET = 48-pin TSOPB = 48-Ball Fine Pitch Ball Grid Array (FBGA)0.80mm pitchSPEED OPTIONSee Product Selector Guide and Valid CombinationsSECTOR for WRITE PROTECT (WP#/ACC=0)H=highestaddresssectorprotectedL=lowestaddresssectorprotectedBASE PART NUMBEREN29LV640 / EN29LV640U64 Megabit(4M x 16-Bit) Uniform Sector Flash3V Read, Erase and ProgramPRODUCT SELECTOR GUIDEValid Combinations VccEN29LV640H–90 EN29LV640L–90 TI, TCBI,BCV cc = 2.7V-3.6VTable 2. Sector (Group) Address Tables Sector GroupProtect/UnprotectSector Address Range for Sector EraseSector Group A21-A17 Sector A21A20A19A18A17A16A15Address Range(hexadecimal) SA0 0 0 0 0 0 0 0 000000–007FFFSA1 0 0 0 0 0 0 1 008000–00FFFFSA2 0 0 0 0 0 1 0 010000–017FFFSG0 00000SA3 0 0 0 0 0 1 1 018000–01FFFFSA4 0 0 0 0 1 0 0 020000–027FFFSA5 0 0 0 0 1 0 1 028000–02FFFFSA6 0 0 0 0 1 1 0 030000–037FFF SG100001SA7 0 0 0 0 1 1 1 038000–03FFFFSA8 0 0 0 1 0 0 0 040000–047FFFSA9 0 0 0 1 0 0 1 048000–04FFFFSA10 0 0 0 1 0 1 0 050000–057FFF SG200010SA11 0 0 0 1 0 1 1 058000–05FFFFSA12 0 0 0 1 1 0 0 060000–067FFFSA13 0 0 0 1 1 0 1 068000–06FFFFSA14 0 0 0 1 1 1 0 070000–077FFF SG300011SA15 0 0 0 1 1 1 1 078000–07FFFFSA16 0 0 1 0 0 0 0 080000–087FFFSA17 0 0 1 0 0 0 1 088000–08FFFFSA18 0 0 1 0 0 1 0 090000–097FFF SG4 00100SA19 0 0 1 0 0 1 1 098000–09FFFFSA20 0 0 1 0 1 0 0 0A0000–0A7FFFSA21 0 0 1 0 1 0 1 0A8000–0AFFFFSA22 0 0 1 0 1 1 0 0B0000–0B7FFF SG5 00101SA23 0 0 1 0 1 1 1 0B8000–0BFFFFSA24 0 0 1 1 0 0 0 0C0000–0C7FFFSA25 0 0 1 1 0 0 1 0C8000–0CFFFFSA26 0 0 1 1 0 1 0 0D0000–0D7FFF SG6 00110SA27 0 0 1 1 0 1 1 0D8000–0DFFFFSA28 0 0 1 1 1 0 0 0E0000–0E7FFFSA29 0 0 1 1 1 0 1 0E8000–0EFFFFSA30 0 0 1 1 1 1 0 0F0000–0F7FFF SG700111SA31 0 0 1 1 1 1 1 0F8000–0FFFFFSector Group A21-A17 Sector A21 A20A19A18A17A16A15Address Range(hexadecimal) SA32 0 1 0 0 0 0 0 100000–107FFFSA33 0 1 0 0 0 0 1 108000–10FFFFSA34 0 1 0 0 0 1 0 110000–117FFFSG8 01000SA35 0 1 0 0 0 1 1 118000–11FFFFSA36 0 1 0 0 1 0 0 120000–127FFFSA37 0 1 0 0 1 0 1 128000–12FFFFSA38 0 1 0 0 1 1 0 130000–137FFF SG9 01001SA39 0 1 0 0 1 1 1 138000–13FFFFSA40 0 1 0 1 0 0 0 140000–147FFFSA41 0 1 0 1 0 0 1 148000–14FFFFSA42 0 1 0 1 0 1 0 150000–157FFF SG10 01010SA43 0 1 0 1 0 1 1 158000–15FFFFSA44 0 1 0 1 1 0 0 160000–167FFFSA45 0 1 0 1 1 0 1 168000–16FFFFSA46 0 1 0 1 1 1 0 170000–177FFF SG11 01011SA47 0 1 0 1 1 1 1 178000–17FFFFSA48 0 1 1 0 0 0 0 180000–187FFFSA49 0 1 1 0 0 0 1 188000–18FFFFSA50 0 1 1 0 0 1 0 190000–197FFF SG12 01100SA51 0 1 1 0 0 1 1 198000–19FFFFSA52 0 1 1 0 1 0 0 1A0000–1A7FFFSA53 0 1 1 0 1 0 1 1A8000–1AFFFFSA54 0 1 1 0 1 1 0 1B0000–1B7FFF SG13 01101SA55 0 1 1 0 1 1 1 1B8000–1BFFFFSA56 0 1 1 1 0 0 0 1C0000–1C7FFFSA57 0 1 1 1 0 0 1 1C8000–1CFFFFSA58 0 1 1 1 0 1 0 1D0000–1D7FFF SG14 01110SA59 0 1 1 1 0 1 1 1D8000–1DFFFFSA60 0 1 1 1 1 0 0 1E0000–1E7FFFSA61 0 1 1 1 1 0 1 1E8000–1EFFFFSA62 0 1 1 1 1 1 0 1F0000–1F7FFF SG15 01111SA63 0 1 1 1 1 1 1 1F8000–1FFFFFSector Group A21-A17 Sector A21A20A19A18A17A16A15Address Range(hexadecimal) SA64 1 0 0 0 0 0 0 200000–207FFFSA65 1 0 0 0 0 0 1 208000–20FFFFSA66 1 0 0 0 0 1 0 210000–217FFFSG16 10000SA67 1 0 0 0 0 1 1 218000–21FFFFSA68 1 0 0 0 1 0 0 220000–227FFFSA69 1 0 0 0 1 0 1 228000–22FFFFSA70 1 0 0 0 1 1 0 230000–237FFF SG1710001SA71 1 0 0 0 1 1 1 238000–23FFFFSA72 1 0 0 1 0 0 0 240000–247FFFSA73 1 0 0 1 0 0 1 248000–24FFFFSA74 1 0 0 1 0 1 0 250000–257FFF SG1810010SA75 1 0 0 1 0 1 1 258000–25FFFFSA76 1 0 0 1 1 0 0 260000–267FFFSA77 1 0 0 1 1 0 1 268000–26FFFFSA78 1 0 0 1 1 1 0 270000–277FFF SG1910011SA79 1 0 0 1 1 1 1 278000–27FFFFSA80 1 0 1 0 0 0 0 280000–287FFFSA81 1 0 1 0 0 0 1 288000–28FFFFSA82 1 0 1 0 0 1 0 290000–297FFF SG2010100SA83 1 0 1 0 0 1 1 298000–29FFFFSA84 1 0 1 0 1 0 0 2A0000–2A7FFFSA85 1 0 1 0 1 0 1 2A8000–2AFFFFSA86 1 0 1 0 1 1 0 2B0000–2B7FFF SG2110101SA87 1 0 1 0 1 1 1 2B8000–2BFFFFSA88 1 0 1 1 0 0 0 2C0000–2C7FFFSA89 1 0 1 1 0 0 1 2C8000–2CFFFFSA90 1 0 1 1 0 1 0 2D0000–2D7FFF SG2210110SA91 1 0 1 1 0 1 1 2D8000–2DFFFFSA92 1 0 1 1 1 0 0 2E0000–2E7FFFSA93 1 0 1 1 1 0 1 2E8000–2EFFFFSA94 1 0 1 1 1 1 0 2F0000–2F7FFF SG2310111SA95 1 0 1 1 1 1 1 2F8000–2FFFFFSector Group A21-A17 Sector A21A20A19A18A17A16A15Address Range(hexadecimal) SA96 1 1 0 0 0 0 0 300000–307FFFSA97 1 1 0 0 0 0 1 308000–30FFFFSA98 1 1 0 0 0 1 0 310000–317FFFSG24 11000SA99 1 1 0 0 0 1 1 318000–31FFFFSA100 1 1 0 0 1 0 0 320000–327FFFSA101 1 1 0 0 1 0 1 328000–32FFFFSA102 1 1 0 0 1 1 0 330000–337FFF SG25 11001SA103 1 1 0 0 1 1 1 338000–33FFFFSA104 1 1 0 1 0 0 0 340000–347FFFSA105 1 1 0 1 0 0 1 348000–34FFFFSA106 1 1 0 1 0 1 0 350000–357FFF SG26 11010SA107 1 1 0 1 0 1 1 358000–35FFFFSA108 1 1 0 1 1 0 0 360000–367FFFSA109 1 1 0 1 1 0 1 368000–36FFFFSA110 1 1 0 1 1 1 0 370000–377FFF SG27 11011SA111 1 1 0 1 1 1 1 378000–37FFFFSA112 1 1 1 0 0 0 0 380000–387FFFSA113 1 1 1 0 0 0 1 388000–38FFFFSA114 1 1 1 0 0 1 0 390000–397FFF SG28 11100SA115 1 1 1 0 0 1 1 398000–39FFFFSA116 1 1 1 0 1 0 0 3A0000–3A7FFFSA117 1 1 1 0 1 0 1 3A8000–3AFFFFSA118 1 1 1 0 1 1 0 3B0000–3B7FFF SG29 11101SA119 1 1 1 0 1 1 1 3B8000–3BFFFFSA120 1 1 1 1 0 0 0 3C0000–3C7FFFSA121 1 1 1 1 0 0 1 3C8000–3CFFFFSA122 1 1 1 1 0 1 0 3D0000–3D7FFF SG30 11110SA123 1 1 1 1 0 1 1 3D8000–3DFFFFSA124 1 1 1 1 1 0 0 3E0000–3E7FFFSA125 1 1 1 1 1 0 1 3E8000–3EFFFFSA126 1 1 1 1 1 1 0 3F0000–3F7FFF SG31 11111SA127 1 1 1 1 1 1 1 3F8000–3FFFFF Note: The sizes of all sectors are 32K-word.USER MODE DEFINITIONSTABLE 3. BUS OPERATIONSOperation CE#OE#WE#RESET#WP#/ACC A21-A0DQ15-DQ0 Read LLHHL/HA IN D OUTWrite LHLH(Note1)A IN(Note 3)AcceleratedProgramL H L H V HH A IN(Note 3)CMOS Standby V cc±0.3V X X V cc±0.3VH XHigh-ZTTL Standby H X X H L / H X High-Z Output Disable L H H H L / H X High-Z Hardware Reset X X X L L / H X High-ZSector Group Protect (Note 2) L H L V ID HSA,A6=L,A1=H,A0=L(Note 3)Sector GroupUnprotect (Note 2) L H L V ID HSA,A6=H,A1=H,A0=L(Note 3)TemporarySector GroupUnprotectX X X V ID H A IN(Note 3)L=logic low= V IL, H=Logic High= V IH, V ID= V HH = 11 ± 0.5V = 10.5 ─ 11.5V, X=Don’t Care (eitherL or H, but not floating!), SA=Sector Addresses (A21-A15), D IN=Data In, D OUT=Data Out,A IN=Address InNotes:1. If the system asserts V IL on the WP# / ACC pin, the device disables program and erasefunctions in the first or last sector independent of whether those sectors were protected orunprotected; if the system asserts V IH on the WP# /ACC pin, the device reverts to whether thefirst or last sector was previously protected or unprotected. If WP# / ACC = V HH, all sectors willbe unprotected.2. Please refer to “Sector Group Protection & Unprotection”, Flowchart 6a and Flowchart 6b.3. D IN or D OUT as required by command sequence, data polling, or sector protect algorithm.Read ModeThe device is automatically set to reading array data after device power-up or hardware reset. No commands are required to retrieve data. The device is also ready to read array data after completing an Embedded Program or Embedded Erase algorithmAfter the device accepts an Sector Erase Suspend command, the device enters the Sector Erase Suspend mode. The system can read array data using the standard read timings, except that if it reads at an address within erase-suspended sectors, the device outputs status data. After completing aprogramming operation in the Sector Erase Suspend mode, the system may once again read array data with the same exception. See “Sector Erase Suspend/Resume Commands” for more additional information.The system must issue the reset command to re-enable the device for reading array data if DQ5 goes high or while in the autoselect mode. See the “Reset Command” for additional details.Output Disable ModeWhen the OE# pin is at a logic high level (V IH), the output from the device is disabled. The output pins are placed in a high impedance state.Standby ModeThe device has a CMOS-compatible standby mode, which reduces the c urrent to < 1µA (typical). It is placed in CMOS-compatible standby when the CE# pin is at V CC± 0.5. RESET# and BYTE# pin must also be at CMOS input levels. The device also has a TTL-compatible standby mode, which reduces the maximum V CC c urrent to < 1mA. It is placed in TTL-compatible standby when the CE# pin is at V IH. When in standby modes, the outputs are in a high-impedance state independent of the OE# input.Automatic Sleep ModeThe device has an automatic sleep mode, which minimizes power consumption. The devices will enter this mode automatically when the states of address bus remain stable for t acc + 30ns. ICC4 in the DC Characteristics table shows the current specification. With standard access times, the device will output new data when addresses change.Writing Command SequencesTo write a command or command sequence to program data to the device or erase data, the system has to drive WE# and CE# to V IL, and OE# to V IH.The device has an Unlock Bypass mode to facilitate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are required to program a word, instead of four.The system can also read the autoselect codes by entering the autoselect mode, which need the autoselect command sequence to be written. Please refer to the “Command Definitions” for all the available commands.Autoselect Identification ModeThe autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on DQ15–DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system through the command register.When using programming equipment, the autoselect mode requires V ID(10.5 V to 11.5 V) on address pin A9. Address pins A6, A1, and A0 must be as shown in Autoselect Codes table. In addition, when verifying sector group protection, the sector group address must appear on the appropriate highest order address bits. Refer to the corresponding Sector Address Tables. The “Command Definitions” table shows the remaining address bits that are don’t-care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ15–DQ0. To access the autoselect codes in-system; the host system can issue the autoselect command via the command register, as shown in the Command Definitions table. This method does not require V ID. See“Command Definitions” for details on using the autoselect mode. Note that a Reset command is required to return to read mode when the device is in the autoselect mode.TABLE 4. Autoselect Codes (Using High Voltage, V ID )L=logic low= V IL , H=Logic High= V IH , V ID =11 ± 0.5V, X=Don’t Care (either L or H, but not floating!), SA=Sector AddressesNote:1. A8=H is recommended for Manufacturing ID check. If a manufacturing ID is read with A8=L, the chip will output a configuration code 7Fh.2. A9 = V ID is for HV A9 Autoselect mode only. A9 must be ≤ Vcc (CMOS logic level) for Command AutoselectMode.RESET#: Hardware ResetWhen RESET# is driven low for t RP , all output pins are tristates. All commands written in the internal state machine are reset to reading array data.Please refer to timing diagram for RESET# pin in “AC Characteristics”.Sector Group Protection & UnprotectionThe hardware sector group protection feature disables both program and erase operations in any sector group. The hardware chip unprotection feature re-enables both program and erase operations in previously protected sector group. A sector group consists of four adjacent sectors that would be protected at the same time. Please see Table 2 which show the organization of sector groups.There are two methods to enable this hardware protection circuitry. The first one requires only that the RESET# pin be at V ID and then standard microprocessor timings can be used to enable or disable this feature. See Flowchart 6a and 6b for the algorithm and Figure 11 for the timings.When doing Sector Group Unprotect, all the unprotected sector groups must be protected prior to any unprotect write cycle.The second method is for programming equipment. This method requires V ID to be applied to both OE# and A9 pins and non-standard microprocessor timings are used. This method is described in a separate document, the Datasheet Supplement of EN29LV640H/L ; EN29LV640U, which can be obtained by contacting a representative of Eon Silicon Solution, Inc.Description CE# OE# WE# A21toA15 A14 to A10A92A8A7A6A5 to A2A1 A0 DQ15 to DQ0H1XX1Ch Manufacturer ID: Eon L L H X X V IDLX L XL LXX7FhAutoselect Device ID L L H X X V IDX X L X L H 227Eh Sector Protection VerificationL L H SA X V IDX X L X H LXX01h(Protected)XX00h(Unprotected)Write Protect / Accelerated Program (WP# / ACC)The Write Protect function provides a hardware method to protect the first or last sector against erase and program without using V ID.When WP# is Low, the device protects the first or last sector regardless of whether these sectors were previously protected or unprotected using the method described in “Sector Group Protection & Unprotection”, Program and Erase operations in these sectors are ignored.When WP# is High, the device reverts to the previous protection status of the first or last sector. Program and Erase operations can now modify the data in those sectors unless the sector is protected using Sector Group Protection.Note that the WP# pin must not be left floating or unconnected.When WP#/ACC is raised to V HH the memory automatically enters the Unlock Bypass mode(please refer to “Command Definitions”), temporarily unprotects every protected sectors, and reduces the time required for program operation. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. When WP#/ACC returns to V IH or V IL, normal operation resumes. The transitions from V IH or V IL to V HH and from V HH to V IH or V IL must be slower than t V HH, see Figure 5. Note that the WP#/ACC pin must not be left floating or unconnected. In addition, WP#/ACC pin mustnot be at V HH for operations other than accelerated programming. It could cause the device to be damaged.Never raise this pin to V HH from any mode except Read mode, otherwise the memory may be left in an indeterminate state.A 0.1µF capacitor should be connected between the WP#/ACC pin and the VSS Ground pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during Unlock Bypass Program.Temporary Sector Group UnprotectThis feature allows temporary unprotection of previously protected sector groups to change data while in-system. The Temporary Sector Group Unprotect mode is activated by setting the RESET# pin to V I D. During this mode, formerly protected sector groups can be programmed or erased by simply selecting the sector group addresses. Once V I D is removed from the RESET# pin, all the previously protected sector groups are protected again. See accompanying flowchart and timing diagrams in Figure 10 for more details.StartReset#=V ID(note 1) Perform Erase or ProgramOperationsRESET#=V IH Temporary Sector Group Unprotect Completed (note 2)Notes:1. All protected sector groups are unprotected. (If WP#/ACC=V IL, the first or last sector will remain protected.)2. Previously protected sector groups are protected again.COMMON FLASH INTERFACE (CFI)The common flash interface (CFI) specification outlines device and host systems software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility.This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address 55h, any time the device is ready to read array data.The system can read CFI information at the addresses given in Tables 5-8.The upper address bits (A7–MSB) must be all zeros. To terminate reading CFI data, the system must write the reset command.The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI query mode and the system can read CFI data at the addresses given in Tables 5–8. The system must write the reset command to return the device to the autoselect mode.Table 5. CFI Query Identification StringAddresses Data Description10h 11h 12h 0051h0052h0059hQuery Unique ASCII string “QRY”13h 14h 0002h0000hPrimary OEM Command Set15h 16h 0040h0000hAddress for Primary Extended Table17h 18h 0000h0000hAlternate OEM Command set (00h = none exists)19h 1Ah 0000h0000hAddress for Alternate OEM Extended Table (00h = none exists)Table 6. System Interface StringAddresses Data Description1Bh 0027h Vcc Min (write/erase)DQ7-DQ4: volt, DQ3 –DQ0: 100 millivolt1Ch 0036h Vcc Max (write/erase)DQ7-DQ4: volt, DQ3 –DQ0: 100 millivolt1Dh 0000h Vpp Min. voltage (00h = no Vpp pin present)1Eh 0000h Vpp Max. voltage (00h = no Vpp pin present)1Fh 0003h Typical timeout per single byte/word write 2NμS20h 0000h Typical timeout for Min, size buffer write 2NμS (00h = not supported) 21h 000Ah Typical timeout per individual block erase 2N ms22h 0000h Typical timeout for full chip erase 2N ms (00h = not supported)23h 0005h Max. timeout for byte/word write 2N times typical24h 0000h Max. timeout for buffer write 2N times typical25h 0002h Max. timeout per individual block erase 2N times typical26h 0000h Max timeout for full chip erase 2N times typical (00h = not supported)Table 7. Device Geometry DefinitionAddresses Data Description27h 0017h Device Size = 2Nbytes 28h 29h 0001h0000h Flash Device Interface description (refer to CFI publication 100)2Ah 2Bh 0000h 0000h Max. number of byte in multi-byte write = 2N (00h = not supported) 2Ch 0001h Number of Erase Block Regions within device 2Dh 2Eh 2Fh 30h 007Fh 0000h 0000h 0001h Erase Block Region 1 Information (refer to the CFI specification of CFI publication 100) 31h 32h 33h 34h 0000h 0000h0000h 0000h Erase Block Region 2 Information35h 36h 37h 38h 0000h 0000h0000h 0000h Erase Block Region 3 Information39h 3Ah 3Bh 3Ch 0000h 0000h0000h 0000hErase Block Region 4 InformationTable 8. Primary Vendor-specific Extended QueryAddresses Data Description40h 41h 42h 0050h 0052h 0049h Query-unique ASCII string “PRI” 43h 0031h Major version number, ASCII 44h 0033h Minor version number, ASCII45h 0004hAddress Sensitive Unlock0 = Required, 1 = Not Required 46h 0002hErase Suspend0 = Not Supported, 1 = To Read Only, 2 = To Read & Write 47h 0004hSector Protect0 = Not Supported, X = Number of sectors in per group 48h 0001hSector Temporary Unprotect00 = Not Supported, 01 = Supported 49h 0004h Sector Protect/Unprotect scheme01 = 29F040 mode, 02 = 29F016 mode,03 = 29F400 mode, 04 = 29LV800A mode 4Ah 0000hSimultaneous Operation00 = Not Supported, 01 = Supported 4Bh 0000hBurst Mode Type00 = Not Supported, 01 = Supported 4Ch 0000hPage Mode Type00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page 4Dh 00A5hMinimum WP#/ACC (Acceleration) Supply Voltage00 = Not Supported, DQ7-DQ4 : Volts, DQ3-DQ0 : 100mV 4Eh 00B5hMaximum WP#/ACC (Acceleration) Supply Voltage00 = Not Supported, DQ7-DQ4 : Volts, DQ3-DQ0 : 100mV4Fh 00XXh 00h = Uniform Sector DevicesHardware Data protectionThe command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes as seen in the Command Definitions table. Additionally, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by false system level signals during Vcc power up and power down transitions, or from system noise.Low V CC Write InhibitWhen V CC is less than V LKO, the device does not accept any write cycles. This protects data during V CC power up and power down. The command register and all internal program/erase circuits are disabled, and the device resets. Subsequent writes are ignored until V CC is greater than V LKO. The system must provide the proper signals to the control pins to prevent unintentional writes when V CC is greater than V LKO.Write Pulse “Glitch” protectionNoise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.Logical InhibitWrite cycles are inhibited by holding any one of OE# = V IL, CE# = V IH, or WE# = V IH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one. If CE#, WE#, and OE# are all logical zero (not recommended usage), it will be considered a read.Power-up Write InhibitDuring power-up, the device automatically resets to READ mode and locks out write cycles. Even with CE# = V IL, WE#= V IL and OE# = V IH, the device will not accept commands on the rising edge of WE#.COMMAND DEFINITIONSThe operations of the device are selected by one or more commands written into the commandregister. Commands are made up of data sequences written at specific addresses via the command register. The sequences for the specified operation are defined in the Command Definitions table (Table 9). Incorrect addresses, incorrect data values or improper sequences will reset the device to Read Mode.Table 9. EN29LV640H/L / EN29LV640U Command DefinitionsBus Cycles (Note 1-2)1stCycle 2ndCycle3rdCycle4thCycle5thCycle6thCycleCommand Sequence C y c l e sAddr DataAddr DataAddr DataAddr DataAddr DataAddr DataRead (Note 3)1RA RD Reset 1xxx F0 Manufacturer ID 4555 AA 2AA 55 55590000 1007F 1CDevice ID 4555 AA 2AA 55 55590 X01 227E A u t o s e l e c tSector Protect Verify (Note 4)4555 AA 2AA 55 55590(SA)X02XX00 XX01Program 4555 AA 2AA 55 555A0 PA PD Unlock Bypass 3555 AA 2AA 55 55520 Unlock Bypass Program2XXX A0 PA PD Unlock Bypass Reset 2XXX90XXX00Chip Erase 6555 AA 2AA 55 55580 555 AA 2AA 55 55510Sector Erase 6555 AA 2AA 55 55580 555 AA 2AA 55 SA 30 Sector Erase Suspend 1BA B0 Sector Erase Resume 1BA 30 CFI Query 15598Address and Data values indicated are in hex. Unless specified, all bus cycles are write cycles RA = Read Address: address of the memory location to be read. This is a read cycle. RD = Read Data: data read from location RA during Read operation. This is a read cycle. PA = Program Address: address of the memory location to be programmed. X = Don’t-Care PD = Program Data: data to be programmed at location PASA = Sector Address: address of the Sector to be erased or verified (in Autoselect mode).Address bits A21-A15 uniquely select any Sector.Notes:1. Data bits DQ15-DQ8 are don’t care in command sequences, except for RD and PD.2. Unless otherwise noted, address bits A21-A15 are don’t cares.3. No unlock or command cycles required when device is in read mode.4. The data is 00h for an unprotected sector group and 01h for a protected sector group.。

Oeko-tex标准中文版

新版Oeko-Tex 100标准14.0 - 7.5 4.0 - 7.5 4.0 - 9.0 4.0 - 9.0 Law 112 n.d.不得检出75 300 300Sb (antimony 锑) 30.0 30.0 30.0As (arsenic 砷)0.2 1.0 1.0 1.0Pb (lead 铅注：严禁使用铅及其合金 ) 0.2 1.0 1.0 1.0 Cd (cadmium 镉) 0.1 0.1 0.1 0.1Cr (chromium 铬) 1.0 2.0 2.0 2.0Cr(VI) 铬 (六价)定量限值：六价铬 Cr(VI)0.5ppm, 禁用的芳香胺20ppm,禁用的燃料50ppm. Co (cobalt 钴) 1.0 4.0 4.0 4.0 Cu (copper 铜) 25.0 50.050.0 50.0Ni (nickel 镍) 1.0 4.0 4.0 4.0 Hg (mercury 汞)0.02 0.02 0.02 0.02sum 总计0.5 1.0 1.0 1.0Pentachlorphenol (PCP) 0.05 0.5 0.5 0.5 2,3,5,6-Tetrachlorphenol (TeCP) 0.05 0.5 0.5 0.5DINP, DNOP, DEHP, DIDP, BBP, DBPsum 总计0.1DEHP, BBP, DBPsum 总计0.1TBT 0.5 1.0 1.0 1.0 DBT 1.0Orthophenylphenol (OPP) 邻苯基苯酚 50.0 100.0 100.0 100.0cleavable arylamines 可分解之芳胺类not used 不可使用carcinogens 致癌物not used 不可使用allergens 致敏物not used 不可使用others 其他 not used 不可使用sum 总计 1.0 1.0 1.0 1.0none 没有general 总体none 没有PBB, TRIS, TEPA, pentaBDE, octaBDE not used 不可使用to water 耐水 3 3 3 3 to acidic perspiration 耐酸性汗液 3 - 4 3 - 4 3 - 4 3 - 4 to alkaline perspiration 耐碱性汗液 3 - 4 3 - 4 3 - 4 3 - 4 to rubbing, dry 耐干摩擦 4 4 4 4 to saliva and perspiration 耐唾液和汗液fast 坚牢Formaldehyd 甲醛[50-00-0]0.1 0.1 0.1 0.1 Toluol 甲苯[108-88-3]0.1 0.1 0.1 0.1 Styrol 苯乙烯[100-42-5]0.005 0.005 0.005 0.005Vinylcyclohexen 乙烯基环乙烷[100-40-3]0.002 0.002 0.002 0.0024-Phenylcyclohexen 苯基环乙烷 [4994-16-5]0.03 0.03 0.03 0.03Butadien 丁二烯[106-99-0]0.002 0.002 0.002 0.002 Vinylchlorid[75-01-4]0.002 0.002 0.002 0.002 aromatic hydrocarbons 芳香烃0.3 0.3 0.3 0.3organic volatiles 有机挥发物0.5 0.5 0.5 0.5general 总体no abnormal odour 无异味SNV 195 651 （modified 经修改） 3 3 3 3引自Oeko-Tex。

LED灯泡能源之星标准(译文)

LED灯泡（一体成型式）能源之星标准标准适用方：各生产商及分销商最新版本修订日期：2010年3月22日标准生效日期：2010年8月31日注：以下内容中“LED灯泡（一体成型式）”简称为：LED灯泡承担的义务以下内容为能源之星合作协议的条款，涉及具有资质的LED灯泡的生产商和分销商能源之星成员必须坚持以下程序要求：●遵守现行能源之星资格标准、性能标准的定义，必须配合能源之星相关部门关于有权按照能源之星标准对产品进行第三方检测，检验合格后方可获准进行公开销售。

●遵守现行能源之星标识指南。

该指南描述了能源之星标志被如何使用。

成员必须遵循哪些准则以及确保所有相关的法定代表人，例如广告代理商、经销商、分销商都必须遵守这些准则。

●成员在申请LED灯泡认证的一年内必须至少有一款产品经检测合格或已经获得能源之星标志使用授权。

一旦上述通过，该成员即被认可。

当成员在做产品认证时，必须符合当时最新的认证标准。

●使用清晰且一一对应的带能源之星LED灯泡的标贴。

主要外包装物正面必须有能源之星证书标志，企业网站、产品目录、用户手册及技术规格参数表必须包含能源之星信息。

●成员必须每半年一次向能源之星组委会提供最新产品样本，并更新产品内容，包含任何产品的修改、检测数据的修改、产品型号或销售代码的变更、以及该产品将在一定时间内逐步终止生产或淘汰。

在此基础上，成员资格才可以被保持。

●如有任何供应商变化，包括新设备、新型号、新包装的信息变更，必须在30天以内以书面或在线等方式，告知具体的变化内容。

●对于每一类产品，必须提供官方认可的检测机构出具的符合能源之星产品性能标准的检测报告。

●每一个分类产品必须提供电子版或者复印件形式的包装样式报告，只有产品性能和包装检测结果均合格，才能进入合格产品目录。

●组委会将任意抽选某一成员的产品进行第三方检测，检测相关费用由成员承担，如成员拒绝接受检测，则其成员资格将被免除。

●每半年提交一次产品出货信息，特别是符合能源之星标准产品出货的总量，信息提交时应写明以下信息：灯头类型ANSI标准外形型号全向灯：A、BT、P、PS、S、T装饰灯：B、BA、C、CA、DC、F、G定向灯：BR、ER、K、MR、PAR、R非标准的：功率数产品编号（如果有）能源之星希望成员能主动提供出货总量信息及其中能源之星产品在总数中所占品种及百分比。

2N70中文资料(Unisonic Technologies)中文数据手册「EasyDatasheet - 矽搜」

VDD =350V, I D =2.0A, R G=25Ω （注1,2）
VDS=560V, V GS=10V, I D=2.0A （注1,2）
VGS = 0 V, I SD = 2.0 A
VGS = 0 V, I SD = 2.0A di / dt = 100 A /μs（注1）
功率 M OSFET
最小典型最大单位
700
V
10 μA
100 nA
-100 nA
0.4
V/°С
2.0
4.0 V
5.0 6.3 Ω
270 350 pF 38 50 pF 5 7 pF
芯片中文手册,看全文,戳
2N70
电气特性（续）
参数
开关特性导通延迟时间导通上升时间关断延迟时间关断下降时间总栅极电荷栅源充栅漏极电荷
最小典型最大单位
30 ns
80 ns
50 ns
70 ns
8.1 11 nC
1.7
nC
4.4
nC
1.4 V
2.0 A
8.0 A
260
ns
1.09
μC
芯片中文手册,看全文,戳
2N70
测试电路和波形
D.U.T.
+
V
+
-
L
R
同类型
V
作为D.U.T.
司机
* dv / dt由R控制 * I 由脉冲周期控制 * D.U.T.-测试设备
功率 M OSFET
V
V
（驱动器）
I (D.U.T.)
V (D.U.T.)
图 . 1A峰值二极管恢复 dv / dt测试电路
期

EN29LV800BB-70BC中文资料(Eon Silicon)中文数据手册「EasyDatasheet - 矽搜」

扇区防护护：部门,以防止编程或擦除个别行业内运
营硬件锁定 - 另外,临时机构撤消允许先
前锁定行
业代码更改.
高性能
- 存取时间快55纳秒
低功耗（在5个典型值 MHz) - 6 mA典型有效读电流 - 24 mA典型编程/擦除电流
- 1 µA 典型待机电流（标准访问
时间到主动模式）
灵活部门架构：
- 一个16字节,两个8字节,一个32字节, 十五64K字节扇区（字节模式）
RY/BY#
DQ0 – DQ15 (A-1)
芯片中文手册,看全文,戳
EN29LV800B
扇形
18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
表 2A.顶部引导块扇区架构
地址范围
(X16)
(X8)
行业
SIZE （千字节/ A18 A17 A16 A15 A14 A13 A12
K字）
7E000h-7FFFFh FC000h-FFFFFh
16/8
111111X
7D000h-7DFFFh FA000h-FBFFFh
8/4
1111101
7C000h-7CFFFh F8000h-F9FFFh
8/4
1111100
78000h-7BFFFh F0000h – F7FFFh
32/16
11 1 1 0XX
44
DQ7
43
DQ14
42
DQ6
41
DQ13
40
DQ5
39
DQ12
38
DQ4
37
Vcc
36
DQ11
35

EN29LV040A-70RSIP中文资料(Eon Silicon)中文数据手册「EasyDatasheet - 矽搜」

EN29LV040A
cFeon顶部标记示例：
cFeon
型号： XXXX-XXX 批号： XXXXX 日期代码： XXXXX
规格连续性
有没有改变此数据表作为提供设备作为Eon公司产品结果.已作出任何变化是正常数据表改善结果,并指出在文档修订摘要,其中支持.今后日常产品更新会在适当时候改变会注意到在修订概要发生,.
表 2.均匀 BLOCK部门架构
扇形
地址范围
扇区大小
A18
A17
A16
（千字节）
7
70000h –7FFFFh
64
1
1
1
6
60000h – 6FFFFh
64
1
1
0
5
50000h – 5FFFFh
64
1
0
1
4
40000h – 4FFFFh
64
1
0
0
3
30000h – 3FFFFh
64
0
1
1
2
20000h – 2FFFFh
OE ）,芯片使能（ CE ）,和写使能（WE）
控制,这消除总线争用问题.该设备被设计为允许是单扇区或整片擦除操作,每个部门可以单独防
护护,防止编程/擦除操作或暂时未受防护护擦除或程序.该设备可以维持最低限度每个扇区10
0K编程/擦除周期.
芯片中文手册,看全文,戳接线图
EN29LV040A
特征
与EN29LV040完全兼容
单电源工作
- 全电压范围：2.7-3.6伏读写操作电池供电应用.
- 稳定电压范围：3.0-3.6伏读操作和写操作高性能3.3伏微处理器.

EN29GL064B-70BIP中文资料(Eon Silicon)中文数据手册「EasyDatasheet - 矽搜」

图 4.逻辑图
A0 – A21
复位＃
CE# OE# WE# Byte#
EN29GL064 RY/BY#
DQ0 – DQ15 (A-1)
芯片中文手册,看全文,戳
表 2.产品选择指南
产品编号
速度选项
全电压范围：VCC = 2.7 - 3.6 V V =1.65 – 3.6 V
功能
A21–A0 数据输入/输出. DQ15（数据输入/输出,文字模式）, A-1（LSB地址输入,字节模式）
芯片使能
输出使能
硬件复位引脚
就绪/忙输出
写使能
电源电压（2.7〜3.6V）
地面
V I / O输入. 字节/字模式选择写防护护/加速引脚留作将来使用.
没有连接到任何东西
初稿
EN29GL064
芯片中文手册,看全文,戳
初稿
EN29GL064
64兆位（8192K×8位/ 4096K×16位）闪存页模式闪存,CMOS 3.0电压只有
EN29GL064
特征
单电源工作
- 全电压范围：2.7至3.6伏读
写操作
高性能
- 存取时间快70纳秒
VIO 输入/输出1.65〜3.6伏特 - 所有输入电平（地址,控制和DQ输入
A10
A11
DQ7 DQ14 DQ13
DQ6
A5
B5
C5
D5
E5
F5
G5
H5
WE# RESET# A21
A19
DQ5 DQ12
VCC
DQ4
A4
B4
C4
D4
E4
F4
G4
H4

807阻燃型单组份室温硫化硅橡胶说明书

807阻燃型单组份室温硫化硅橡胶简介：●本产品为脱醇系阻燃型单组份室温硫化硅橡胶。

特点●电子专用：本产品专为电源等电器开发的室温硫化硅橡胶粘接剂。

●抑制触点失效：公司运用独特专利技术，解决挥发性材料导致封闭式电源触点失效的问题，大大延长使用寿命。

●环保无卤阻燃：产品阻燃等级为UL 94 V-0级，完全不含有溴系等有害阻燃剂，也不含有其它氯、氟化物、重金属等有害物质，符合ROHS指令以及最新环保要求。

固化时气味小，挥发物低，固化后的产品对铜等金属没有腐蚀性，是安全环保的电子粘接材料。

●快速固化：产品表干时间短（≤30min），深层固化快，有利于快速粘接。

●本品固化后拉伸强度和拉伸剪切强度较高，对橡胶、塑料、金属等材质具有非常优异的粘接性能。

且具有优良的挠曲性以及绝缘、防潮、防震功能。

●固化物耐臭氧和紫外线、具有良好的耐候性和耐老化性能，可在-45℃-180℃条件下使用。

用途●主要适用于各类电源电子元器件产品的粘接、密封。

性能参数使用说明●通常在室温及相对湿度为30%-80%的条件下固化，在24-72小时内固化物理性能可达完全性能的90%以上。

产品不适用于高度密闭或深层固化。

●请在通风良好的工作环境下使用产品。

不慎接触眼睛和皮肤应立即冲洗、擦洗干净或由医生治疗。

●可在-45℃至180℃的温度范围内长期使用。

然而在温度范围的上下限，在材料的特殊性和表现可能变得复杂化，需要经过对您的部件或者组件进行检验才能核实。

●所粘接的表面需保持清洁，如果表面有油污残留则会影响粘接。

适宜表面清洁可获得更好的效果，用户应确定最适合工艺方法。

●对多数活性金属、陶瓷、玻璃、树脂和塑料粘接牢固，但对非活性金属或非活性塑料表面如Teflon、聚乙烯或聚丙烯等材质不具良好的粘合性。

通常，增加固化温度和固化时间会提高粘合性。

●不推荐有油污、增塑剂、溶剂等会影响固化和粘接的表面直接使用，在涂层表面使用需考虑对涂层的影响。

●本产品在使用后，应将胶管密封，可保存再次使用。

EN29LV800CB-70TI中文资料

and fifteen 32-Kword sectors (word mode)
• High performance program/erase speed - Byte/Word program time: 8µs typical - Sector erase time: 500ms typical
B3
C3
RY/BY#
NC
A18
A2
B2
C2
A7
A17
A6
A1
B1
C1
A3
A4
A2
A11 D4 NC D3 NC D2 A5 D1 A1
DQ7 E4
DQ14 F4
DQ13
DQ6
G4
H4
DQ5
DQ12
Vcc
DQ4
E3 DQ2 E2
F3 DQ10 F2
G3
H3
DQ11
DQ3
G2
H2
DQ0 E1
DQ8 F1
1 1 1 1 0XX
14
70000h-77FFFh E0000h - EFFFFh 64/32
1 11 0XXX
13
68000h-6FFFFh D0000h - DFFFFh 64/32
1 10 1XXX
12
60000h-6FFFFh C0000h - CFFFFh 64/32
1 10 0XXX
11
Kwords)
18
7E000h-7FFFFh FC000h-FFFFFh
16/8
111111X
17
7D000h-7DFFFh FA000h-FBFFFh
8/4
1111101
16

EN25B32-100QC中文资料(Eon Silicon)中文数据手册「EasyDatasheet - 矽搜」

芯片中文手册,看全文,戳
EN25B32
32兆位串行闪存与引导和参数部门
EN25B32
特征
单电源工作
- 全电压范围：2.7-3.6伏
32 M位串行闪存 - 32 M位/ 4096 K-字节/ 16384页 - 每可编程页256字节
高性能
- 100MHz时钟频率
低功耗
- 5毫安典型工作电流
底部或顶部引导配置
16384 页（每256字节）
每一页都可以单独编程（位从1编程为0）.该设备部门或大容量可擦除而不是页面可擦除.
表2a.
底部引导块 ,部门架构
扇形
扇区大小（ K字节）
67
64
66
64
65
64
64
64
63
64
62
64
61
64
60
64
59
64
58
64
57
64
56
64
55
该EN25B32有68部门,包括63部门为64KB,32KB一个部门,一是部门有16KB,8KB一个部门和4KB两个部门.此装置被设计成允许或者单部门在同一时间或整片擦除操作.该EN25B32可以防护护存储在任一顶部或底部启动配置中小部门引导代码.该设备可以维持最低限度每个扇区100K编程/擦除周期.
串行数据输出（ DO）
SPI串行数据输出（DO）引脚提供数据和状态一种手段进行串行读取（移出）器件.数据移出对串行时钟（CLK）输入引脚下降沿.
串行时钟（ CLK）
SPI串行时钟输入（CLK）引脚提供串行输入和输出操作时机. （"见SPI 模式"）

可控硅参数说明及中英文对照表

mA
ID
Off-state leakage current
断态漏电流
-
mA
VGT
Triggering gate voltage
门极触发电压
—可以选择Vgt 25度时max值的β倍;β为门极触发电压—结温特性系数,查数据手册可得,取特性曲线中最低工作温度时的系数;若对器件工作环境温度无特殊需要,通常选择时β取1~1.2倍即可;
A
VTM
Peak on-state voltage drop
通态峰值电压
指器件通过规定正向峰值电流IFM整流管或通态峰值电流ITM晶闸管时的峰值电压也称峰值压降该参数直接反映了器件的通态损耗特性影响着器件的通态电流额定能力;
V
IDRM
Maximum forward or reverse leakage current
通态流上升率
当双向可控硅或闸流管在门极电流触发下导通,门极临近处立即导通,然后迅速扩展至整个有效面积;这迟后的时间有一个极限,即负载电流上升率的许可值;过高的dIT/dt可能导致局部烧毁,并使T1-T2 短路;假如过程中限制dIT/dt到一较低的值,双向可控硅可能可以幸存;因此,假如双向可控硅的VDRM在严重的、异常的电源瞬间过程中有可能被超出或导通时的dIT/dt有可能被超出,可在负载上串联一个几μH的不饱和空心电感;
℃
Tstg
Storage Temperature Range
贮存温度
-
℃
TL
Max.Lead Temperature for Soldering Purposes
引脚承受焊锡极限温度
-
℃
Rthj-mb
Thermal Resistance Junction tomounting base

EN29F010-70TIP中文资料

This Data Sheet may be revised by subsequent versions ©2003 Eon Silicon Solution, Inc., or modifications due to changes in technical specifications.1FEATURES• 5.0V operation for read/write/erase operations• Fast Read Access Time - 45ns, 55ns, 70ns, and 90ns• Sector Architecture:- 8 uniform sectors of 16Kbytes each - Supports full chip erase- Individual sector erase supported - Sector protection:Hardware locking of sectors to prevent program or erase operations within individual sectors• High performance program/erase speed - Byte program time: 7µs typical - Sector erase time: 300ms typical - Chip erase time: 3s typical • Low Standby Current- 1µA CMOS standby current-typical - 1mA TTL standby current • Low Power Active Current- 12mA typical active read current - 30mA program/erase current• JEDEC Standard program and erase commands• JEDEC standard DATA polling and toggle bits feature• Single Sector and Chip Erase • Sector Unprotect Mode• Embedded Erase and Program Algorithms • Erase Suspend / Resume modes:Read and program another Sector during Erase Suspend Mode• 0.23 µm triple-metal double-poly triple-well CMOS Flash Technology • Low Vcc write inhibit < 3.2V • 100K endurance cycle • Package Options - 32-pin PDIP - 32-pin PLCC- 32-pin 8mm x 20mm TSOP (Type 1) - 32-pin 8mm x 14mm TSOP (Type 1) • Commercial and Industrial Temperature RangesGENERAL DESCRIPTIONThe EN29F010 is a 1-Megabit, electrically erasable, read/write non-volatile flash memory. Organized into 128K bytes with 8 bits per byte, the 1M of memory is arranged in eight uniform sectors of 16Kbytes each. Any byte can be programmed typically in 7µs. The EN29F010 features 5.0V voltage read and write operation, with access times as fast as 45ns to eliminate the need for WAIT states in high-performance microprocessor systems.The EN29F010 has separate Output Enable (OE ), Chip Enable (CE ), and Write Enable (W E ) controls, which eliminate bus contention issues. This device is designed to allow either single Sector or full chip erase operation, where each Sector can be individually protected againstprogram/erase operations or temporarily unprotected to erase or program. The device can sustain a minimum of 100K program/erase cycles on each Sector.EN29F010 1 Megabit (128K x 8-bit) 5V Flash MemoryTABLE 1. PIN DESCRIPTIONFIGURE 1. LOGIC DIAGRAMTABLE 2. SECTOR ARCHITECTURESectorADDRESSESSIZE (Kbytes)A16 A15 A14 7 1C000h - 1FFFFh 16 1 11 618000h – 1BFFFh16115 14000h – 17FFFh 16 1 0 1 4 10000h – 13FFFh 16 1 0 0 3 0C000h – 0FFFFh 16 0 1 1 208000h – 0BFFFh1611 04000h - 07FFFh16 0 0 1 0 00000h - 03FFFh160 0 0DQ0 - DQ7VssBLOCK DIAGRAMFIGURE 2. PDIPFIGURE 3. PLCCFIGURE 4. TSOPTABLE 3. OPERATING MODES1M FLASH USER MODE TABLENOTES:1) L = V IL, H = V IH, V ID = 11.0V ± 0.5V2) X = Don’t care, either V IH or V IL3) Ax/y: Ax = Addr(x), Ay = Addr(y)TABLE 4. DEVICE IDENTIFICTION1M FLASH MANUFACTURER/DEVICE ID TABLEA8 A6 A1 A0 DQ(7-0) HEXREAD MANUFACTURER ID H(1) L L LMANUFACTURER ID1CREAD DEVICE ID X(2) L L HDEVICE ID20NOTES:1) If a Manufacturing ID is read with A8 = L, the chip will output a configuration code 7Fh. A furtherManufacturing ID must be read with A8 = H.2) X = Don’t careUSER MODE DEFINITIONSStandby ModeThe EN29F010 has a CMOS-compatible standby mode, which reduces the current to < 1µA (typical). It is placed in CMOS-compatible standby when the CE pin is at V CC± 0.5. The device also has a TTL-compatible standby mode, which reduces the maximum V CC current to < 1mA. It is placed in TTL-compatible standby when the pin is at V IH. When in standby modes, the outputs are in a high-impedance state independent of the OE input.Read ModeThe device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is also ready to read array data after completing an Embedded Program or Embedded Erase algorithm.After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode. The system can read array data using the standard read timings, except that if it reads at an address within erase-suspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See “Erase Suspend/Erase Resume Commands” for more information on this mode.The system must issue the reset command to re-enable the device for reading array data if DQ5 goes high, or while in the autoselect mode. See “Reset Command” section.See also “Requirements for Reading Array Data” in the “Device Bus Operations” section for more information. The Read Operations table provides the read parameters, and Read Operation Timings diagram shows the timing diagram.Output Disable ModeWhen the OE pin is at a logic high level (V IH), the output from the EN29F010 is disabled. The output pins are placed in a high impedance state.Auto Select Identification ModeThe autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on DQ7–DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system through the command register.When using programming equipment, the autoselect mode requires V ID (10.5 V to 11.5 V) on address pin A9. Address pins A6, A1, and A0 must be as shown in Autoselect Codes (High Voltage Method) table. In addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits. Refer to the corresponding Sector Address Tables. The Command Definitions table shows the remaining address bits that are don’t care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ7–DQ0.To access the autoselect codes in-system; the host system can issue the autoselect command via the command register, as shown in the Command Definitions table. This method does not require V ID. See “Command Definitions” for details on using the autoselect mode.Reset CommandWriting the reset command to the device resets the device to reading array data. Address bits are don’t care for this command.The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to reading array data. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to reading array data (also applies to programming in Erase Suspend mode). Once programming begins, however, the device ignores reset commands until the operation is complete.The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to reading array data (also applies to autoselect during Erase Suspend).If DQ5 goes high during a program or erase operation, writing the reset command returns the device to reading array data (also applies during Erase Suspend).Write ModeProgramming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verifies the programmed cell margin. Table 5 (Command Definitions) shows the address and data requirements for the byte program command sequence.When the Embedded Program algorithm is complete, the device then returns to reading array data and addresses are no longer latched. The system can determine the status of the program operation by using DQ7 or DQ6. See “Write Operation Status” for information on these status bits.Any commands written to the device during the Embedded Program Algorithm are ignored.Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from a “0” back to a “1”. Attempting to do so may halt the operation and set DQ5 to “1”, or cause the Data# Polling algorithm to indicate the operation was successful. However, a succeeding read will show that the data is still “0”. Only erase operations can convert a “0” to a “1”.COMMAND DEFINITIONSThe operations of the EN29F010 are selected by one or more commands written into the command register to perform Read/Reset Memory, Read ID, Read Sector Protection, Program, Sector Erase, Chip Erase, Erase Suspend and Erase Resume. Commands are made up of data sequences written at specific addresses via the command register. The sequences for the specified operation are defined in the Command Table (Table 5). Incorrect addresses, incorrect data values or improper sequences will reset the device to the read mode.Table 5. EN29F010 Command Definitions1stWrite Cycle2ndWrite Cycle3rdWrite Cycle 4thWrite Cycle5thWrite Cycle6thWrite CycleCommand Sequence Read/Reset Write Cycles Req’dAddr Data Addr DataAddr DataAddr Data Addr Data AddrDataRead 1 RA RDReset 1 XXXh F0hRead/Reset 4 555h AAh 2AAh 55h 555h F0h RA RD AutoSelect Manufacturer ID 4 555h AAh 2AAh 55h 555h 90h 000h/100h 7Fh/1ChAutoSelect Device ID 4 555h AAh 2AAh 55h 555h 90h 01h 20hAutoSelect Sector Protect Verify 4 555h AAh 2AAh 55h 555h 90h BA &02h 00h/01hByte Program 4 555h AAh 2AAh 55h 555h A0h PA PD Chip Erase 6 555h AAh 2AAh 55h 555h 80h 555h AAh 2AAh 55h 555h 10hSector Erase6 555h AAh 2AAh55h555h80h 555h AAh 2AAh 55h BA30hSector Erase Suspend 1 xxxh B0h Sector Erase Resume1 xxxh 30hNotes:RA = Read Address: address of the memory location to be read. This one is a read cycle. RD = Read Data: data read from location RA during Read operation. This one is a read cycle. PA = Program Address: address of the memory location to be programmed PD = Program Data: data to be programmed at location PABA = Sector Address: address of the Sector to be erased. Address bits A16-A14 uniquely select any Sector.The data is 00h for an unprotected sector and 01h for a protected sector.Byte Programming CommandProgramming the EN29F010 is performed on a byte-by-byte basis using a four bus-cycle operation (two unlock write cycles followed by the Program Setup command and Program Data Write cycle). When the program command is executed, no additional CPU controls or timings are necessary. An internal timer terminates the program operation automatically. Address is latched on the falling edge of CE or W E , whichever is last; data is latched on the rising edge of CE or W E , whichever is first. The program operation is completed when EN29F010 returns the equivalent data to the programmed location.Programming status may be checked by sampling data on DQ7 (DATA polling) or on DQ6 (toggle bit). Changing data from 0 to 1 requires an erase operation. When programming time limit is exceeded, DQ5 will produce a logical “1” and a Reset command can return the device to Read mode.Chip Erase CommandChip erase is a six-bus-cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. The Command Definitions table shows the address and data requirements for the chip erase command sequence.Any commands written to the chip during the Embedded Erase algorithm are ignored.The system can determine the status of the erase operation by using DQ7, DQ6, or DQ2. See “Write Operation Status” for information on these status bits. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched.Flowchart 4 illustrates the algorithm for the erase operation. See the Erase/Program Operations tables in “AC Characteristics” for parameters, and Chip/Sector Erase Operation Timings for timing waveforms. Sector Erase CommandSector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two un-lock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the address of the sector to be erased, and the sector erase command. The Command Definitions table shows the address and data requirements for the sector erase command sequence.The device does not require the system to preprogram the memory prior to erase. The Embedded Erase algorithm automatically programs and verifies the sector for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations.This device does not support multiple sector erase commands. Sector Erase operation will commence immediately after the first 30h command is written. The first sector erase operation must finish before another sector erase command can be given.Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored.When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, or DQ2. Refer to “Write Operation Status” for information on these status bits. Flowchart 4 illustrates the algorithm for the erase operation. Refer to the Erase/Program Operations tables in the “AC Characteristics” section for parameters, and to the Sector Erase Operations Timing diagram for timing waveforms.Erase Suspend / Resume CommandThe Erase Suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. This command is valid only during the sector erase operation. The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm. Addresses are “don’t-cares” when writing the Erase Suspend command.When the Erase Suspend command is written during a sector erase operation, the device requires a maximum of 20 µs to suspend the erase operation.After the erase operation has been suspended, the system can read array data from or program data to any sector not selected for erasure. (The device “erase suspends” all sectors selected for erasure.) Normal read and write timings and command definitions apply. Reading at any address within erase-suspended sectors produces status data on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. See “Write Operation Status” for information on these status bits.After an erase-suspended program operation is complete, the system can once again read array data within non-suspended sectors. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. See “Write Operation Status” for more information.The system must write the Erase Resume command (address bits are “don’t care”) to exit the erase suspend mode and continue the sector erase operation. Further writes of the Resume commandare ignored. Another Erase Suspend command can be written after the device has resumed erasing. Sector Protection/UnprotectionThe hardware sector protection feature disables both program and erase operations in any sector. The hardware sector unprotection feature re-enables both program and erase operations in previously protected sectors.Sector protection/unprotection must be implemented using programming equipment. The procedure re-quires a high voltage (V ID) on address pin A9 and the control pins. Contact Eon Silicon Solution, Inc. for an additional supplement on this feature.WRITE OPERATION STATUSDQ7DATA PollingThe EN29F010 provides DATA Polling on DQ7 to indicate to the host system the status of the embedded operations. The DATA Polling feature is active during the Byte Programming, Sector Erase, Chip Erase, and Erase Suspend. (See Table 6)When the Byte Programming is in progress, an attempt to read the device will produce the complement of the data last written to DQ7. Upon the completion of the Byte Programming, an attempt to read the device will produce the true data last written to DQ7. For the Byte Programming, DATA polling is valid after the rising edge of the fourth WE or CE pulse in the four-cycle sequence. When the embedded Erase is in progress, an attempt to read the device will produce a “0” at the DQ7 output. Upon the completion of the embedded Erase, the device will produce the “1” at the DQ7 output during the read. For Chip Erase, the DATA polling is valid after the rising edge of the sixth W E or CE pulse in the six-cycle sequence. For Sector Erase, DATA polling is valid after the last rising edge of the sector erase W E or C E pulse.DATA Polling must be performed at any address within a sector that is being programmed or erased and not a protected sector. Otherwise, DATA polling may give an inaccurate result if the address used is in a protected sector.Just prior to the completion of the embedded operations, DQ7 may change asynchronously when the output enable (OE) is low. This means that the device is driving status information on DQ7 at one instant of time and valid data at the next instant of time. Depending on when the system samples the DQ7 output, it may read the status of valid data. Even if the device has completed the embedded operations and DQ7 has a valid data, the data output on DQ0-DQ6 may be still invalid. The valid data on DQ0-DQ7 will be read on the subsequent read attempts.The flowchart for DATA Polling (DQ7) is shown on Flowchart 5. The DATA Polling (DQ7) timing diagram is shown in Figure 8.DQ6Toggle Bit IThe EN29F010 provides a “Toggle Bit” on DQ6 to indicate to the host system the status of the embedded programming and erase operations. (See Table 6)During an embedded Program or Erase operation, successive attempts to read data from the device at any address (by toggling OE or CE) will result in DQ6 toggling between “zero” and “one”. Once the embedded Program or Erase operation is complete, DQ6 will stop toggling and valid data will be read on the next successive attempts. During Byte Programming, the Toggle Bit is valid after the rising edge of the fourth WE pulse in the four-cycle sequence. For Chip Erase, the Toggle Bit is valid after the rising edge of the sixth-cycle sequence. For Sector Erase, the Toggle Bit is valid after the last rising edge of the Sector Erase W E pulse. The Toggle Bit is also active during the sector erase time-out window.In Byte Programming, if the sector being written to is protected, DQ6 will toggles for about 2 µs, then stop toggling without the data in the sector having changed. In Sector Erase or Chip Erase, if all selected sectors are protected, DQ6 will toggle for about 100 µs. The chip will then return to the read mode without changing data in all protected sectors.Toggling either CE or OE will cause DQ6 to toggle.The flowchart for the Toggle Bit (DQ6) is shown in Flowchart 6. The Toggle Bit timing diagram is shown in Figure 9.DQ5 Exceeded Timing LimitsDQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a “1.” (The Toggle Bit (DQ6) should also be checked at this time to make sure that the DQ5 is not a “1” due to the device having returned to read mode.) This is a failure condition that indicates the program or erase cycle was not successfully completed. . DATA Polling (DQ7), Toggle Bit (DQ6) and Erase Toggle Bit (DQ2) still function under this condition.Setting the CE to V IH will partially power down the device under those conditions.The DQ5 failure condition may appear if the system tries to program a “1” to a location that is previously programmed to “0.” Only an erase operation can change a “0” back to a “1.” Under this condition, the device halts the operation, and when the operation has exceeded the timing limits, DQ5 produces a “1.” Under both these conditions, the system must issue the reset command to return the device to reading array data.DQ2 Erase Toggle Bit IIThe “Toggle Bit” on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table 6 to compare outputs for DQ2 and DQ6.Flowchart 6 shows the toggle bit algorithm, and the section “DQ2: Toggle Bit” explains the algorithm. See also the “DQ6: Toggle Bit I” subsection. Refer to the Toggle Bit Timings figure for the toggle bit timing diagram. The DQ2 vs. DQ6 figure shows the differences between DQ2 and DQ6 in graphical form.Reading Toggle Bits DQ6/DQ2Refer to Flowchart 6 for the following discussion. Whenever the system initially begins reading toggle bit status, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, a system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7–DQ0 on the following read cycle.However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfullycompleted the program or erase operation. If it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data.The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of Flowchart 6).Table 6. Status Register BitsNotes:DQ7 DATA Polling: indicates the P/E status check during Program or Erase, and on completion before checking bits DQ5 for Program or Erase Success.DQ6 Toggle Bit: remains at constant level when P/E operations are complete or erase suspend is acknowledged. Successive reads output complementary data on DQ6 while programming or Erase operation are on-going.DQ5 Error Bit: set to “1” if failure in programming or eraseDQ2 Toggle Bit: indicates the Erase status and allows identification of the erased Sector.DATA PROTECTIONPower-up Write InhibitDuring power-up, the device automatically resets to READ mode and locks out write cycles. Even with CE = V IL, W E = V IL and OE = V IH, the device will not accept commands on the rising edge of W E.Low V CC Write InhibitDuring V CC power-up or power-down, the EN29F010 locks out write cycles to protect against any unintentional writes. If V CC < V LOK, the command register is disabled and all internal program or erase circuits are disabled. Under this condition, the device will reset to the READ mode. Subsequent writes will be ignored until V CC > V LKO.Write “Noise” Pulse ProtectionNoise pulses less than 5ns on OE, CE or WE will neither initiate a write cycle nor change the command register.Logical InhibitIf CE=V IH or WE=V IH, writing is inhibited. To initiate a write cycle, CE and W E must be a logical “zero”. If CE, W E, and OE are all logical zero (not recommended usage), it will be considered a write.Sector Protect and UnprotectThe hardware sector protection feature disables both program and erase operations in any sector. The hardware sector unprotection feature re-enables both program and erase operation in previously protected sectors.Sector protection/unprotection must be implemented using programming equipment. The procedure requires a high voltage (V ID) on address pin A9 and the control pins. Contact Eon Silicon Solution, Inc. for an additional supplement on this feature.EMBEDDED ALGORITHMSFlowchart 1. Embedded ProgramFlowchart 2. Embedded Program Command SequenceSee the Command Definitions section for more information.Flowchart 3. Embedded EraseFlowchart 4. Embedded Erase Command Sequence See the Command Definitions section for more information.Chip Erase Sector EraseFlowchart 5. DATA Polling AlgorithmFlowchart 6. Toggle Bit AlgorithmABSOLUTE MAXIMUM RATINGSStorage TemperaturePlastic Packages . . . . . . . . . . . . . . . –65°C to +125°CAmbient Temperaturewith Power Applied. . . . . . . . . . . . . . –55°C to +125°CVoltage with Respect to GroundV CC (Note 1) . . . . . . . . . . . . . . . . . . . . –0.5 V to 7.0 VA9, OE# (Note 2) . . . . . . . . . . . . . . . –0.5 V to 11.5 VAll other pins (Note 1) . . . . . . . . . . . . –0.5 V to Vcc+0.5VOutput Short Circuit Current (Note 3) . . . . . . . . . 200 mANotes:1. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, inputs may undershootV SS to –1.0V for periods of up to 50 ns and to –2.0 V for periods of up to 20 ns. See Left Figure below.Maximum DC voltage on input and I/O pins is V CC + 0.5 V. During voltage transitions, input and I/Opins may overshoot to V CC + 2.0 V for periods up to 20 ns. See Right Figure below.2. Minimum DC input voltage on A9 pin is –0.5 V. During voltage transitions, A9 and OE# mayundershoot V SS to –1.0V for periods of up to 20 ns and to –2.0 V for periods of up to 20 ns. See LeftFigure. Maximum DC input voltage on A9 and OE# is 11.5 V which may overshoot to 12.5 V forperiods up to 20 ns.3. No more than one output shorted to ground at a time. Duration of the short circuit should not be greaterthan one second. Stresses above those listed under “Absolute Maximum Ratings” may causepermanent damage to the device. This is a stress rating only; functional operation of the device atthese or any other conditions above those indicated in the operational sections of this specification isnot implied. Exposure of the device to absolute maximum rating conditions for extended periods mayaffect device reliability.OPERATING RANGESCommercial (C) DevicesAmbient Temperature (T A ) . . . . . . . . . . . 0°C to +70°CIndustrial (I) DevicesAmbient Temperature (T A ). . . . . . . . . . -40°C to +85°CV CC Supply VoltagesV CC for ± 5% devices . . . . . . . . . . . . +4.75 V to +5.25 VV CC for ± 10% devices . . . . . . . . . . . +4.50 V to +5.50 VOperating ranges define those limits between which thefunctionality of the device is guaranteed.Maximum Negative Overshoot Maximum Positive OvershootWaveform Waveform。

维沙伊·西利康晶体管数据手册说明书

Dual N-Channel 100 V (D-S) MOSFETFEATURES•TrenchFET ® power MOSFET •100 % R g and UIS tested •Material categorization:for definitions of compliance please see /doc?99912APPLICATIONS•Primary side switching •Synchronous rectificationNotesa.Based on T C = 25 °Cb.Surface mounted on 1" x 1" FR4 boardc.t = 10 sd.See solder profile (/doc?73257). The PowerPAK SO-8 is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure adequate bottom side solder interconnectione.Rework conditions: Manual soldering with a soldering iron is not recommended for leadless componentsf.Maximum under steady state conditions is 85 °C/WPowerPAK ® S O-8 DualTop View16.15mm5.15m mBottom ViewG 241S 12G 13S 2D 18D 26D 17D 25ABSOLUTE MAXIMUM RATINGS (T A = 25 °C, unless otherwise noted)Parameter S ymbol Limit UnitDrain-source voltageV DS 100VGate-source voltageV GS± 20Continuous drain current (T J = 150 °C)T C = 25 °C I D36.7AT C = 85 °C29.2T A = 25 °C 10.1 b, c T A = 85 °C 8 b, cPulsed drain current (t = 300 μs)I DM 80Continuous source-drain diode current T C = 25 °C I S38T A = 25 °C 2.9 b, cSingle pulse avalanche current L = 0.1 mHI AS 20Single pulse avalanche energy E AS20mJMaximum power dissipation T C = 25 °C P D46WT C = 85 °C 29T A = 25 °C3.5 b, c T A = 85 °C 2.2 b, cOperating junction and storage temperature range T J , T stg -55 to +150°CSoldering recommendations (peak temperature) d, e 260THERMAL RESISTANCE RATINGSParameter S ymbol Typical Maximum UnitMaximum junction-to-ambient b, ft ≤ 10 s R thJA 2635°C/WMaximum junction-to-case (drain)Steady state R thJC 2.2 2.7Notesa.Pulse test; pulse width ≤ 300 μs, duty cycle ≤ 2 %b.Guaranteed by design, not subject to production testingStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.SPECIFICATIONS (T J = 25 °C, unless otherwise noted)Parameter S ymbol Test Conditions Min.Typ.Max.Unit StaticDrain-source breakdown voltage V DS V GS = 0 V, I D = 250 μA100--V V DS Temperature coefficient ∆V DS /T J I D = 250 μA -67-mV/°C V GS(th) Temperature coefficient ∆V GS(th)/T J --5.7-Gate-source threshold voltage V GS(th)V DS = V GS , I D = 250 μA 1.5- 3.5V Gate-source leakageI GSS V DS = 0 V, V GS = ± 20 V --± 100nA Zero gate voltage drain current I DSS V DS = 100 V, V GS = 0 V --1μA V DS = 100 V, V GS = 0 V, T J = 55 °C--10On-state drain current aI D(on) V DS ≥ 5 V, V GS = 10 V 30--ADrain-source on-state resistance a R DS(on)V GS = 10 V, I D = 15 A -0.0140.018ΩV GS = 7.5 V, I D = 12 A -0.0150.019V GS = 6 V, I D = 10 A -0.0160.021Forward transconductance a g fsV DS = 15 V, I D = 15 A-40-S Dynamic bInput capacitance C issV DS = 50 V, V GS = 0 V, f = 1 MHz -1170-pF Output capacitanceC oss -311-Reverse transfer capacitance C rss-33-Total gate charge Q gV DS = 50 V, V GS = 10 V, I D = 10 A-17.527nC V DS = 50 V, V GS = 7.5 V, I D = 10 A-13.420V DS = 50 V, V GS = 6 V, I D = 10 A -12.218.5Gate-source charge Q gs - 3.5-Gate-drain charge Q gd - 5.2-Out charge Q oss V DS = 50 V, V GS = 0 V-2741Gate resistance R g f = 1 MHz0.4 1.8 3.6ΩTurn-on delay time t d(on)V DD = 50 V, R L = 5 ΩI D ≅ 10 A, V GEN = 7.5 V, R g = 1 Ω-1224ns Rise timet r -1326Turn-off delay time t d(off) -1836Fall timet f -714Turn-on delay time t d(on)V DD = 50 V, R L = 5 ΩI D ≅ 10 A, V GEN = 10 V, R g = 1 Ω-816Rise timet r -1224Turn-off delay time t d(off) -2040Fall timet f-714Drain-Source Body Diode Characteristics Continuous source-drain diode current I S T C = 25 °C--38A Pulse diode forward current I SM --80Body diode voltageV SD I S = 5 A, V GS = 0 V-0.78 1.2V Body diode reverse recovery time t rr I F = 10 A, dI/dt = 100 A/μs, T J = 25 °C-3975ns Body diode reverse recovery charge Q rr -53100nC Reverse recovery fall time t a -26-nsReverse recovery rise timet b-13-TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)Output CharacteristicsOn-Resistance vs. Drain Current and Gate VoltageGate ChargeTransfer CharacteristicsCapacitanceOn-Resistance vs. Junction TemperatureTYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)Source-Drain Diode Forward Voltage Threshold Voltage On-Resistance vs. Gate-to-Source VoltageSingle Pulse Power (Junction-to-Ambient)Safe Operating Area, Junction-to-AmbientTYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)Current Derating a Power Junction to CasePower Junction to AmbientNotea.The power dissipation P D is based on T J max. = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below thepackage limit.TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)Normalized Thermal Transient Impedance, Junction-to-CaseVishay Silico nix maintains wo rldwide manufacturing capability. Pro ducts may be manufactured at o ne o f several qualified lo catio ns. Reliability data fo r Silico n Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see /ppg?62634.Package Information Vishay SiliconixPowerPAK® SO-8, (Single/Dual)DIM.MILLIMETERS INCHESMIN.NOM.MAX.MIN.NOM.MAX.A0.97 1.04 1.120.0380.0410.044 A1-0.050-0.002 b0.330.410.510.0130.0160.020 c0.230.280.330.0090.0110.013D 5.05 5.15 5.260.1990.2030.207D1 4.80 4.90 5.000.1890.1930.197 D2 3.56 3.76 3.910.1400.1480.154 D3 1.32 1.50 1.680.0520.0590.066 D40.57 typ.0.0225 typ.D5 3.98 typ.0.157 typ.E 6.05 6.15 6.250.2380.2420.246E1 5.79 5.89 5.990.2280.2320.236 E2 3.48 3.66 3.840.1370.1440.151 E3 3.68 3.78 3.910.1450.1490.154 E40.75 typ.0.030 typ.e 1.27 BSC0.050 BSCK 1.27 typ.0.050 typ.K10.56--0.022--H0.510.610.710.0200.0240.028 L0.510.610.710.0200.0240.028 L10.060.130.200.0020.0050.008 0°-12°0°-12°W0.150.250.360.0060.0100.014 M0.125 typ.0.005 typ.ECN: S17-0173-Rev. L, 13-Feb-17DWG: 5881V I S H A Y S I L I C O N I XPower MOSFETsPowerPAK ® SO-8 Mounting and Thermal ConsiderationsA P P L I C A T I O N N O T by Wharton McDanielMOSFETs for switching applications are now available with die on resistances around 1 m and with the capability to handle 85 A. While these die capabilities represent a major advance over what was available just a few years ago, it is important for power MOSFET packaging technology to keep pace. t should be obvious that degradation of a high performance die by the package is undesirable. PowerPAK is a new package technology that addresses these issues.I n this application note, PowerPAK’s construction is described. Following this mounting information is presented including land patterns and soldering profiles for maximum reliability. Finally, thermal and electrical performance is discussed.THE PowerPAK PACKAGEThe PowerPAK package was developed around the SO-8package (figure 1). The PowerPAK SO-8 utilizes the same footprint and the same pin-outs as the standard SO-8. This allows PowerPAK to be substituted directly for a standard SO-8 package. Being a leadless package, PowerPAK SO-8utilizes the entire SO-8 footprint, freeing space normally occupied by the leads, and thus allowing it to hold a larger die than a standard SO-8. In fact, this larger die is slightly larger than a full sized DPAK die. The bottom of the die attach pad is exposed for the purpose of providing a direct,low resistance thermal path to the substrate the device is mounted on. Finally, the package height is lower than the standard SO-8, making it an excellent choice forapplications with space constraints.Fig. 1 PowerPAK 1212 DevicesPowerPAK SO-8 SINGLE MOUNTINGThe PowerPAK single is simple to use. The pin arrangement (drain, source, gate pins) and the pin dimensions are the same as standard SO-8 devices (see figure 2). Therefore, the PowerPAK connection pads match directly to those of theSO-8. The only difference is the extended drain connection area. To take immediate advantage of the PowerPAK SO-8single devices, they can be mounted to existing SO-8 land patterns.Fig. 2The minimum land pattern recommended to take full advantage of the PowerPAK thermal performance see Application Note 826, Recommended Minimum Pad Patterns With Outline Drawing Access for Vishay Siliconix MOSFETs . Click on the PowerPAK SO-8 single in the index of this document.I n this figure, the drain land pattern is given to make full contact to the drain pad on the PowerPAK package.This land pattern can be extended to the left, right, and top of the drawn pattern. This extension will serve to increase the heat dissipation by decreasing the thermal resistance from the foot of the PowerPAK to the PC board and therefore to the ambient. Note that increasing the drain land area beyond a certain point will yield little decrease in foot-to-board and foot-to-ambient thermal resistance.Under specific conditions of board configuration, copper weight and layer stack, experiments have found that more than about 0.25 in 2 to 0.5 in 2 of additional copper (in addition to the drain land) will yield little improvement in thermal performance.Standard SO-8Po w erPAK SO-8PowerPAK ® SO-8 Mounting and Thermal ConsiderationsP P L I C A T I O N N O T EPowerPAK SO-8 DUALThe pin arrangement (drain, source, gate pins) and the pin dimensions of the PowerPAK SO-8 dual are the same as standard SO-8 dual devices. Therefore, the PowerPAK device connection pads match directly to those of the SO-8.As in the single-channel package, the only exception is the extended drain connection area. Manufacturers can likewise take immediate advantage of the PowerPAK SO-8 dual devices by mounting them to existing SO-8 dual land patterns.To take the advantage of the dual PowerPAK SO-8’s thermal performance, the minimum recommended land pattern can be found in Application Note 826,Recommended Minimum Pad Patterns With Outline Drawing Access for Vishay Siliconix MOSFETs . Click on the PowerPAK 1212-8 dual in the index of this document.The gap between the two drain pads is 24 mils. This matches the spacing of the two drain pads on the PowerPAK SO-8 dual package.REFLOW SOLDERINGVishay Siliconix surface-mount packages meet solder reflow reliability requirements. Devices are subjected to solder reflow as a test preconditioning and are then reliability-tested using temperature cycle, bias humidity,HAST, or pressure pot. The solder reflow temperature profile used, and the temperatures and time duration, are shown in figures 3 and 4.For the lead (Pb)-free solder profile, see /doc?73257.Fig. 3 Solder Reflow Temperature ProfileFig. 4 Solder Reflow Temperatures and Time DurationsRamp-Up Rate+ 3 °C /s max.Temperature at 150 - 200 °C120 s max.Temperature Above 217 °C 60 - 150 s Maximum Temperature 255 + 5/- 0 °CTime at Maximum Temperature 30 s Ramp-Down Rate+ 6 °C/s max.PowerPAK ® SO-8 Mounting and Thermal ConsiderationsP P L I C A T I O N N O T ETHERMAL PERFORMANCEIntroductionA basic measure of a device’s thermal performance is the junction-to-case thermal resistance, R thJC , or the junction-to-foot thermal resistance, R thJF This parameter is measured for the device mounted to an infinite heat sink and is therefore a characterization of the device only, in other words, independent of the properties of the object to which the device is mounted. Table 1 shows a comparison of the DPAK, PowerPAK SO-8, and standard SO-8. The PowerPAK has thermal performance equivalent to the DPAK, while having an order of magnitude better thermal performance over the SO-8.Thermal Performance on Standard SO-8 Pad Pattern Because of the common footprint, a PowerPAK SO-8can be mounted on an existing standard SO-8 pad pattern.The question then arises as to the thermal performance of the PowerPAK device under these conditions. A characterization was made comparing a standard SO-8 and a PowerPAK device on a board with a trough cut out underneath the PowerPAK drain pad. This configuration restricted the heat flow to the SO-8 land pads. The results are shown in figure 5.Fig. 5 PowerPAK SO-8 and Standard SO-0 Land Pad ThermalPathBecause of the presence of the trough, this result suggests a minimum performance improvement of 10 °C/W by using a PowerPAK SO-8 in a standard SO-8 PC board mount. The only concern when mounting a PowerPAK on a standard SO-8 pad pattern is that there should be no traces running between the body of the MOSFET. Where the standard SO-8 body is spaced away from the pc board,allowing traces to run underneath, the PowerPAK sits directly on the pc board.Thermal Performance - Spreading CopperDesigners may add additional copper, spreading copper, to the drain pad to aid in conducting heat from a device. It is helpful to have some information about the thermal performance for a given area of spreading copper. Figure 6 shows the thermal resistance of a PowerPAK SO-8device mounted on a 2-in. 2-in., four-layer FR-4 PC board.The two internal layers and the backside layer are solid copper. The internal layers were chosen as solid copper to model the large power and ground planes common in many applications. The top layer was cut back to a smaller area and at each step junction-to-ambient thermal resistance measurements were taken. The results indicate that an area above 0.3 to 0.4 square inches of spreading copper gives no additional thermal performance improvement. A subsequent experiment was run where the copper on the back-side was reduced, first to 50 % in stripes to mimic circuit traces, and then totally removed. No significant effect was observed.Fig. 6 Spreading Copper Junction-to-Ambient PerformanceTABLE 1 - DPAK AND POWERPAK SO-8EQUIVALENT STEADY STATE PERFORMANCEDPAKPowerPAKSO-8 Standard SO-8 Thermal Resistance R thJC1.2 °C/W1 °C/W16 °C/WR th v s. Spreading Copper (0 %, 50 %, 100 % Back Copper)Spreading Copper (sq in))s t t a w /C ( e c n a d e p m I 0.0056514641360.250.500.751.001.251.501.752.000 %50 %100 %PowerPAK ® SO-8 Mounting and Thermal ConsiderationsA P P L I C A T I O N N O T EApplication Note AN821Vishay SiliconixRevision: 16-Mai-134Document Number: 71622For technical questions, contact: *********************************THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENTARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT /doc?91000SYSTEM AND ELECTRICAL IMPACT OF PowerPAK SO-8I n any design, one must take into account the change in MOSFET R DS(on) with temperature (figure 7).Fig. 7 MOSFET R DS(on) vs. TemperatureA MOSFET generates internal heat due to the currentpassing through the channel. This self-heating raises the junction temperature of the device above that of the PC board to which it is mounted, causing increased power dissipation in the device. A major source of this problem lies in the large values of the junction-to-foot thermal resistance of the SO-8 package.PowerPAK SO-8 minimizes the junction-to-board thermal resistance to where the MOSFET die temperature is very close to the temperature of the PC board. Consider two devices mounted on a PC board heated to 105 °C by other components on the board (figure 8).Fig. 8 Temperature of Devices on a PC BoardSuppose each device is dissipating 2.7 W. Using thejunction-to-foot thermal resistance characteristics of the PowerPAK SO-8 and the standard SO-8, the die temperature is determined to be 107 °C for the PowerPAK (and for DPAK) and 148 °C for the standard SO-8. This is a 2 °C rise above the board temperature for the PowerPAK and a 43 °C rise for the standard SO-8. Referring to figure 7,a 2 °C difference has minimal effect on R DS(on) whereas a 43 °C difference has a significant effect on R DS(on). Minimizing the thermal rise above the board temperature by using PowerPAK has not only eased the thermal design but it has allowed the device to run cooler, keep r DS(on) low, and permits the device to handle more current than the same MOSFET die in the standard SO-8 package.CONCLUSIONSPowerPAK SO-8 has been shown to have the same thermal performance as the DPAK package while having the same footprint as the standard SO-8 package. The PowerPAK SO-8 can hold larger die approximately equal in size to the maximum that the DPAK can accommodate implying no sacrifice in performance because of package limitations. Recommended PowerPAK SO-8 land patterns are provided to aid in PC board layout for designs using this new package.Thermal considerations have indicated that significant advantages can be gained by using PowerPAK SO-8devices in designs where the PC board was laid out for the standard SO-8. Applications experimental data gave thermal performance data showing minimum and typical thermal performance in a SO-8 environment, plus information on the optimum thermal performance obtainable including spreading copper. This further emphasized the DPAK equivalency.PowerPAK SO-8 therefore has the desired small size characteristics of the SO-8 combined with the attractive thermal characteristics of the DPAK package.Application Note 826Vishay Siliconix Document Number: 7260016Revision: 21-Jan-08A P P L I C A T I O N N O T ERECOMMENDED MINIMUM PADS FOR PowerPAK ® SO-8 DualLegal Disclaimer Notice VishayDisclaimerALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROV E RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.V ishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively,“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product.Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product. To the maximum extent permitted by applicable law, Vishay disclaims (i) any and all liability arising out of the application or use of any product, (ii) any and all liability, including without limitation special, consequential or incidental damages, and (iii) any and all implied warranties, including warranties of fitness for particular purpose, non-infringement and merchantability.Statements regarding the suitability of products for certain types of applications are based on Vishay's knowledge of typical requirements that are often placed on Vishay products in generic applications. Such statements are not binding statements about the suitability of products for a particular application. It is the customer's responsibility to validate that a particular product with the properties described in the product specification is suitable for use in a particular application. Parameters provided in datasheets and / or specifications may vary in different applications and performance may vary over time. All operating parameters, including typical parameters, must be validated for each customer application by the customer's technical experts. Product specifications do not expand or otherwise modify Vishay's terms and conditions of purchase, including but not limited to the warranty expressed therein.Hyperlinks included in this datasheet may direct users to third-party websites. These links are provided as a convenience and for informational purposes only. Inclusion of these hyperlinks does not constitute an endorsement or an approval by Vishay of any of the products, services or opinions of the corporation, organization or individual associated with the third-party website. Vishay disclaims any and all liability and bears no responsibility for the accuracy, legality or content of the third-party website or for that of subsequent links.Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the Vishay product could result in personal injury or death. Customers using or selling Vishay products not expressly indicated for use in such applications do so at their own risk. Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners.© 2021 VISHAY INTERTECHNOLOGY, INC. ALL RIGHTS RESERVEDRevision: 09-Jul-20211Document Number: 91000。

29LV800BT-70资料

MX29LV800BT/BB8M-BIT [1Mx8/512K x16] CMOS SINGLE VOLTAGE3V ONLY FLASH MEMORYand erase operation completion.•Ready/Busy# pin (RY/BY#)- Provides a hardware method of detecting program or erase operation completion.•Sector protection- Hardware method to disable any combination of sectors from program or erase operations- Temporary sector unprotected allows code changes in previously locked sectors.•CFI (Common Flash Interface) compliant- Flash device parameters stored on the device and provide the host system to access•100,000 minimum erase/program cycles•Latch-up protected to 100mA from -1V to VCC+1V •Boot Sector Architecture - T = Top Boot Sector - B = Bottom Boot Sector •Package type:- 44-pin SOP - 48-pin TSOP - 48-pin CSP•Compatibility with JEDEC standard- Pinout and software compatible with single-power supply Flash•10 years data retentionFEATURES•Extended single - supply voltage range 2.7V to 3.6V •1,048,576 x 8/524,288 x 16 switchable •Single power supply operation- 3.0V only operation for read, erase and program operation•Fast access time: 70/90ns •Low power consumption- 20mA maximum active current - 0.2uA typical standby current •Command register architecture- Byte/word Programming (9us/11us typical)- Sector Erase (Sector structure 16K-Bytex1,8K-Bytex2, 32K-Bytex1, and 64K-Byte x15)•Fully compatible with MX29LV800T/B device •Auto Erase (chip & sector) and Auto Program- Automatically erase any combination of sectors with Erase Suspend capability.- Automatically program and verify data at specified address•Erase suspend/Erase Resume- Suspends sector erase operation to read data from,or program data to, any sector that is not being erased,then resumes the erase.•Status Reply- Data# polling & Toggle bit for detection of programGENERAL DESCRIPTIONThe MX29L V800BT/BB is a 8-mega bit Flash memory organized as 1M bytes of 8 bits or 512K words of 16bits. MXIC's Flash memories offer the most cost-effec-tive and reliable read/write non-volatile random access memory. The MX29L V800BT/BB is packaged in 44-pin SOP , 48-pin TSOP , and 48-ball CSP . It is designed to be reprogrammed and erased in system or in standard EPROM programmers.The standard MX29LV800BT/BB offers access time as fast as 70ns, allowing operation of high-speed micropro-cessors without wait states. To eliminate bus conten-tion, the MX29LV800BT/BB has separate chip enable (CE#) and output enable (OE#) controls.MXIC's Flash memories augment EPROM functionality with in-circuit electrical erasure and programming. The MX29LV800BT/BB uses a command register to man-age this functionality. The command register allows for100% TTL level control inputs and fixed power supply levels during erase and programming, while maintaining maximum EPROM compatibility.MXIC Flash technology reliably stores memory contents even after 100,000 erase and program cycles. The MXIC cell is designed to optimize the erase and programming mechanisms. In addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and program operations produces reliable cy-cling. The MX29LV800BT/BB uses a 2.7V~3.6V VCC supply to perform the High Reliability Erase and auto Program/Erase algorithms.The highest degree of latch-up protection is achieved with MXIC's proprietary non-epi process. Latch-up pro-tection is proved for stresses up to 100 milliamperes on address and data pin from -1V to VCC + 1V.MX29LV800BT/BBPIN CONFIGURATIONSPIN DESCRIPTIONSYMBOL PIN NAME A0~A18Address Input Q0~Q14Data Input/OutputQ15/A-1Q15(Word mode)/LSB addr(Byte mode)CE#Chip Enable Input WE#Write Enable Input BYTE#Word/Byte Selection input RESET#Hardware Reset Pin OE#Output Enable Input RY/BY#Ready/Busy OutputVCC Power Supply Pin (2.7V~3.6V)GNDGround Pin48 TSOP (Standard Type) (12mm x 20mm)48-Ball CSP Ball Pitch = 0.8 mm, Top View, Balls Facing Down44 SOP(500 mil)A B C D E F GH6A13A12A14A15A16BYTE#Q15/A-1GND 5A9A8A10A11Q7Q14Q13Q64 WE#RESET#NCNC Q5Q12Vcc Q43RY/BY#NC A18NC Q2Q10Q11Q32A7A17A6A5Q0Q8Q9Q11A3A4A2A1A0CE#OE#GND234567891011121314151617181920212244434241403938373635343332313029282726252423RY/BY#A18A17A7A6A5A4A3A2A1A0CE#GND OE#Q0Q8Q1Q9Q2Q10Q3Q11RESET#WE#A8A9A10A11A12A13A14A15A16BYTE#GND Q15/A-1Q7Q14Q6Q13Q5Q12Q4VCCM X 29L V 800B T /B BA15A14A13A12A11A10A9A8NC NC WE#RESET#NC NC RY/BY#A18A17A7A6A5A4A3A2A1123456789101112131415161718192021222324A16BYTE#GND Q15/A-1Q7Q14Q6Q13Q5Q12Q4VCC Q11Q3Q10Q2Q9Q1Q8Q0OE#GND CE#A0484746454443424140393837363534333231302928272625MX29LV800BT/BBMX29LV800BT/BBBLOCK STRUCTURETABLE 1: MX29LV800BT SECTOR ARCHITECTURENote: Byte mode:address range A18:A-1, word mode:address range A18:A0.Sector Sector SizeAddress range Sector AddressByte Mode Word ModeByte Mode (x8)Word Mode (x16)A18A17A16A15A14A13A12SA064Kbytes 32Kwords 00000h-0FFFFh 00000h-07FFFh 0000X X X SA164Kbytes 32Kwords 10000h-1FFFFh 08000h-0FFFFh 0001X X X SA264Kbytes 32Kwords 20000h-2FFFFh 10000h-17FFFh 0010X X X SA364Kbytes 32Kwords 30000h-3FFFFh 18000h-1FFFFh 0011X X X SA464Kbytes 32Kwords 40000h-4FFFFh 20000h-27FFFh 0100X X X SA564Kbytes 32Kwords 50000h-5FFFFh 28000h-2FFFFh 0101X X X SA664Kbytes 32Kwords 60000h-6FFFFh 30000h-37FFFh 0110X X X SA764Kbytes 32Kwords 70000h-7FFFFh 38000h-3FFFFh 0111X X X SA864Kbytes 32Kwords 80000h-8FFFFh 40000h-47FFFh 1000X X X SA964Kbytes 32Kwords 90000h-9FFFFh 48000h-4FFFFh 1001X X X SA1064Kbytes 32Kwords A0000h-AFFFFh 50000h-57FFFh 1010X X X SA1164Kbytes 32Kwords B0000h-BFFFFh 58000h-5FFFFh 1011X X X SA1264Kbytes 32Kwords C0000h-CFFFFh 60000h-67FFFh 1100X X X SA1364Kbytes 32Kwords D0000h-DFFFFh 68000h-6FFFFh 1101X X X SA1464Kbytes 32Kwords E0000h-EFFFFh 70000h-77FFFh 1110X X X SA1532Kbytes 16Kwords F0000h-F7FFFh 78000h-7BFFFh 11110X X SA168Kbytes 4Kwords F8000h-F9FFFh 7C000h-7CFFFh 1111100SA178Kbytes 4Kwords FA000h-FBFFFh 7D000h-7DFFFh 1111101SA1816Kbytes8KwordsFC000h-FFFFFh7E000h-7FFFFh111111XMX29LV800BT/BBTABLE 2: MX29LV800BB SECTOR ARCHITECTURESector Sector Size Address range Sector Address Byte Mode Word Mode Byte Mode (x8)Word Mode (x16)A18A17A16A15A14A13A12 SA016Kbytes8Kwords00000h-03FFFh00000h-01FFFh000000X SA18Kbytes4Kwords04000h-05FFFh02000h-02FFFh0000010 SA28Kbytes4Kwords06000h-07FFFh03000h-03FFFh0000011 SA332Kbytes16Kwords08000h-0FFFFh04000h-07FFFh00001X X SA464Kbytes32Kwords10000h-1FFFFh08000h-0FFFFh0001X X X SA564Kbytes32Kwords20000h-2FFFFh10000h-17FFFh0010X X X SA664Kbytes32Kwords30000h-3FFFFh18000h-1FFFFh0011X X X SA764Kbytes32Kwords40000h-4FFFFh20000h-27FFFh0100X X X SA864Kbytes32Kwords50000h-5FFFFh28000h-2FFFFh0101X X X SA964Kbytes32Kwords60000h-6FFFFh30000h-37FFFh0110X X X SA1064Kbytes32Kwords70000h-7FFFFh38000h-3FFFFh0111X X X SA1164Kbytes32Kwords80000h-8FFFFh40000h-47FFFh1000X X X SA1264Kbytes32Kwords90000h-9FFFFh48000h-4FFFFh1001X X X SA1364Kbytes32Kwords A0000h-AFFFFh50000h-57FFFh1010X X X SA1464Kbytes32Kwords B0000h-BFFFFh58000h-5FFFFh1011X X X SA1564Kbytes32Kwords C0000h-CFFFFh60000h-67FFFh1100X X X SA1664Kbytes32Kwords D0000h-DFFFFh68000h-6FFFFh1101X X X SA1764Kbytes32Kwords E0000h-EFFFFh70000h-77FFFh1110X X X SA1864Kbytes32Kwords F0000h-FFFFFh78000h-7FFFFh1111X X XNote: Byte mode:address range A18:A-1, word mode:address range A18:A0.MX29LV800BT/BBBLOCK DIAGRAMCONTROL INPUT LOGICPROGRAM/ERASE HIGH VOLTAGEWRITE STATE MACHINE (WSM)STATEREGISTERMX29LV800BT/BBFLASH ARRAYX-DECODERADDRESS LATCHAND BUFFERY -PASS GATEY -DECODERARRAY SOURCE HVCOMMAND DATADECODERCOMMAND DATA LATCHI/O BUFFERPGM DATA HVPROGRAM DATA LATCHSENSE AMPLIFIERQ0-Q15/A-1A0-A18CE#OE#WE#RESET#MX29LV800BT/BBAUTOMATIC PROGRAMMINGThe MX29L V800BT/BB is byte programmable using the Automatic Programming algorithm. The Automatic Pro-gramming algorithm makes the external system do not need to have time out sequence nor to verify the data programmed. The typical chip programming time at room temperature of the MX29LV800BT/BB is less than 10 seconds.AUTOMATIC PROGRAMMING ALGORITHM MXIC's Automatic Programming algorithm requires the user to only write program set-up commands (including 2 unlock write cycle and A0H) and a program command (program data and address). The device automatically times the programming pulse width, provides the pro-gram verification, and counts the number of sequences. The device provides an unlock bypass mode with faster programming. Only two write cycles are needed to pro-gram a word or byte, instead of four. A status bit similar to DA TA# polling and a status bit toggling between con-secutive read cycles, provide feedback to the user as to the status of the programming operation. Refer to write operation status, table 8, for more information on these status bits.AUTOMATIC CHIP ERASEThe entire chip is bulk erased using 10 ms erase pulses according to MXIC's Automatic Chip Erase algorithm. T ypical erasure at room temperature is accomplished in less than 25 second. The Automatic Erase algorithm automatically programs the entire array prior to electri-cal erase. The timing and verification of electrical erase are controlled internally within the device. AUTOMATIC SECTOR ERASEThe MX29LV800BT/BB is sector(s) erasable using MXIC's Auto Sector Erase algorithm. The Automatic Sector Erase algorithm automatically programs the specified sector(s) prior to electrical erase. The timing and verification of electrical erase are controlled inter-nally within the device. An erase operation can erase one sector, multiple sectors, or the entire device.AUTOMATIC ERASE ALGORITHMMXIC's Automatic Erase algorithm requires the user to write commands to the command register using stan-dard microprocessor write timings. The device will auto-matically pre-program and verify the entire array. Then the device automatically times the erase pulse width, provides the erase verification, and counts the number of sequences. A status bit toggling between consecu-tive read cycles provides feedback to the user as to the status of the erasing operation.Register contents serve as inputs to an internal state-machine which controls the erase and programming cir-cuitry. During write cycles, the command register inter-nally latches address and data needed for the program-ming and erase operations. During a system write cycle, addresses are latched on the falling edge, and data are latched on the rising edge of WE# or CE#, whichever happens first.MXIC's Flash technology combines years of EPROM experience to produce the highest levels of quality, reli-ability, and cost effectiveness. The MX29LV800BT/BB electrically erases all bits simultaneously using Fowler-Nordheim tunneling. The bytes are programmed by us-ing the EPROM programming mechanism of hot elec-tron injection.During a program cycle, the state-machine will control the program sequences and command register will not respond to any command set. During a Sector Erase cycle, the command register will only respond to Erase Suspend command. After Erase Suspend is completed, the device stays in read mode. After the state machine has completed its task, it will allow the command regis-ter to respond to its full command set. AUTOMATIC SELECTThe auto select mode provides manufacturer and de-vice identification, and sector protection verification, through identifier codes output on Q7~Q0. This mode is mainly adapted for programming equipment on the de-vice to be programmed with its programming algorithm. When programming by high voltage method, automatic select mode requires VID (11.5V to 12.5V) on address pin A9 and other address pin A6, A1 and A0 as referring to Table 3. In addition, to access the automatic select codes in-system, the host can issue the automatic se-MX29LV800BT/BBlect command through the command register withoutrequiring VID, as shown in table 5.T o verify whether or not sector being protected, the sec-tor address must appear on the appropriate highest or-der address bit (see Table 1 and Table 2). The rest ofaddress bits, as shown in table 3, are don't care. Onceall necessary bits have been set as required, the pro-gramming equipment may read the corresponding iden-tifier code on Q7~Q0.TABLE 3. MX29LV800BT/BB AUTO SELECT MODE OPERATIONA18A11A9A8A6A5A1A0Description Mode CE#OE#WE#| | | |Q15~Q0A12A10A7A2Manufacturer Code L L H X X VID X L X L L C2H Read Device ID Word L L H X X VID X L X L H22DAH Silicon(T op Boot Block)Byte L L H X X VID X L X L H XXDAHID Device ID Word L L H X X VID X L X L H225BH (Bottom Boot Block)Byte L L H X X VID X L X L H XX5BHXX01H Sector Protection L L H SA X VID X L X H L(protected) Verification XX00H(unprotected) NOTE:SA=Sector Address, X=Don't Care, L=Logic Low, H=Logic HighMX29LV800BT/BBQUERY COMMAND AND COMMON FLASH INTERFACE (CFI) MODE ( for MX29L V800BT/ BB)MX29LV800BT/BB is capable of operating in the CFI mode. This mode all the host system to determine the manufacturer of the device such as operating param-eters and configuration. Two commands are required in CFI mode. Query command of CFI mode is placed first, then the Reset command exits CFI mode. These are described in T able 6.The single cycle Query command is valid only when the device is in the Read mode, including Erase Suspend, Standby mode, and Read ID mode; however, it is ig-nored otherwise.The Reset command exits from the CFI mode to the Read mode, or Erase Suspend mode, or read ID mode. The command is valid only when the device is in the CFI mode.TABLE 4-1. CFI mode: Identification Data Values(All values in these tables are in hexadecimal)Description Address Address Data(Byte Mode)(Word Mode) Query-unique ASCII string "QRY"201000512211005224120059 Primary vendor command set and control interface ID code2613000228140000 Address for primary algorithm extended query table2A1500402C160000 Alternate vendor command set and control interface ID code (none)2E17000030180000 Address for secondary algorithm extended query table (none)32190000341A0000 TABLE 4-2. CFI Mode: System Interface Data Values(All values in these tables are in hexadecimal)Description Address Address Data(Byte Mode)(Word Mode) VCC supply, minimum (2.7V)361B0027 VCC supply, maximum (3.6V)381C0036 VPP supply, minimum (none)3A1D0000 VPP supply, maximum (none)3C1E0000 Typical timeout for single word/byte write (2N us)3E1F0004 Typical timeout for Minimum size buffer write (2N us)40200000 Typical timeout for individual block erase (2N ms)4221000A Typical timeout for full chip erase (2N ms)44220000 Maximum timeout for single word/byte write times (2N X Typ)46230005 Maximum timeout for buffer write times (2N X Typ)48240000 Maximum timeout for individual block erase times (2N X Typ)4A250004 Maximum timeout for full chip erase times (not supported)4C260000MX29LV800BT/BB TABLE 4-3. CFI Mode: Device Geometry Data Values(All values in these tables are in hexadecimal)Description Address Address Data(Byte Mode)(Word Mode) Device size (2N bytes)4E270014 Flash device interface code (refer to the CFI publication 100)5028000252290000 Maximum number of bytes in multi-byte write (not supported)542A0000562B0000 Number of erase block regions582C0004 Erase block region 1 information (refer to the CFI publication 100)5A2D00005C2E00005E2F004060300000 Erase block region 2 information62310001643200006633002068340000 Erase block region 3 information6A3500006C3600006E37008070380000 Erase block region 4 information7239000E743A0000763B0000783C0001 TABLE 4-4. CFI Mode: Primary Vendor-Specific Extended Query Data Values(All values in these tables are in hexadecimal)Description Address Address Data(Byte Mode)(Word Mode) Query-unique ASCII string "PRI"804000508241005284420049 Major version number, ASCII86430031 Minor version number, ASCII88440030 Address sensitive unlock (0=required, 1= not required)8A450000 Erase suspend (2= to read and write)8C460002 Sector protect (N= # of sectors/group)8E470001 Temporary sector unprotected (1=supported)90480001 Sector protect/unprotected scheme92490004 Simultaneous R/W operation (0=not supported)944A0000 Burst mode type (0=not supported)964B0000 Page mode type (0=not supported)984C0000MX29LV800BT/BBTABLE 5. MX29LV800BT/BB COMMAND DEFINITIONSFirst Bus Second Bus Third Bus Fourth Bus Fifth Bus Sixth Bus Command Bus Cycle Cycle Cycle Cycle Cycle CycleCycle Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Reset 1XXXH F0HRead1RA RDRead Silicon ID Word4555H AAH2AAH55H555H90H ADI DDIByte4AAAH AAH555H55H AAAH90H ADI DDISector Protect Word4555H AAH2AAH55H555H90H(SA)XX00HVerify x02H XX01HByte4AAAH AAH555H55H AAAH90H(SA)00Hx04H01HProgram Word4555H AAH2AAH55H555H A0H PA PDByte4AAAH AAH555H55H AAAH A0H PA PDChip Erase Word6555H AAH2AAH55H555H80H555H AAH2AAH55H555H10H Byte6AAAH AAH555H55H AAAH80H AAAH AAH555H55H AAAH10H Sector Erase Word6555H AAH2AAH55H555H80H555H AAH2AAH55H SA30H Byte6AAAH AAH555H55H AAAH80H AAAH AAH555H55H SA30H Sector Erase Suspend1XXXH B0HSector Erase Resume1XXXH30HCFI Query Word155H98Byte1AAH98Note:1.ADI = Address of Device identifier; A1=0, A0 = 0 for manufacturer code,A1=0, A0 = 1 for device code. A2-A18=do not care.(Refer to table 3)DDI = Data of Device identifier : C2H for manufacture code, 22DA/DA(T op), and 225B/5B(Bottom) for device code.X = X can be VIL or VIHRA=Address of memory location to be read.RD=Data to be read at location RA.2.P A = Address of memory location to be programmed.PD = Data to be programmed at location P A.SA = Address of the sector.3.The system should generate the following address patterns: 555H or 2AAH to Address A10~A0 in word mode/AAAH or555H to Address A10~A-1 in byte mode.Address bit A11~A18=X=Don't care for all address commands except for Program Address (PA) and Sector Address (SA).Write Sequence may be initiated with A11~A18 in either state.4.For Sector Protect Verify operation: If read out data is 01H, it means the sector has been protected. If read out data is 00H,it means the sector is still not being protected.5.Any number of CFI data read cycle are permitted.MX29LV800BT/BBTABLE 6. MX29LV800BT/BB BUS OPERATIONNOTES:1. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to T able 5.2. VID is the Silicon-ID-Read high voltage, 11.5V to 12.5V .3. Refer to T able 5 for valid Data-In during a write operation.4. X can be VIL or VIH.5. Code=00H/XX00H means unprotected.Code=01H/XX01H means protected.6.A18~A12=Sector address for sector protect.7.The sector protect and chip unprotected functions may also be implemented via programming equipment.sequences. Note that the Erase Suspend (B0H) and Erase Resume (30H) commands are valid only while the Sector Erase operation is in progress.COMMAND DEFINITIONSDevice operations are selected by writing specific ad-dress and data sequences into the command register.Writing incorrect address and data values or writing them in the improper sequence will reset the device to the read mode. Table 5 defines the valid register commandADDRESSQ8~Q15DESCRIPTION CE#OE#WE#RESET#A18A10A9A8A6A5A1A0Q0~Q7BYTE BYTE A12A11A7A2=VIH =VIL ReadLLHHAINDoutDoutQ8~Q14=High Z Q15=A-1Write L H L H AIN DIN(3)DIN ResetX X X L X High Z High Z High Z Temporary sector unlock X X X VID AIN DIN DIN High Z Output Disable L HH H X High Z High Z High Z Standby Vcc ±XX Vcc ± X High Z High Z High Z 0.3V 0.3V Sector Protect L H L VID SA X X X L X H L DIN X X Chip Unprotected L H L VID X X X X H X H L DIN X X Sector Protection VerifyLLHHSAXVIDXLXHLCODE(5)XXMX29LV800BT/BBREQUIREMENTS FOR READING ARRAY DATAT o read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power control and selects the device. OE# is the output control and gates array data to the output pins. WE# should remain at VIH.The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid address on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered. WRITE COMMANDS/COMMAND SEQUENCEST o program data to the device or erase sectors of memory , the system must drive WE# and CE# to VIL, and OE# to VIH.The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are required to program a byte, instead of four. The "byte Program Command Sequence" section has details on programming data to the device using both standard and Unlock Bypass command sequences.An erase operation can erase one sector, multiple sectors , or the entire device. T able indicates the address space that each sector occupies. A "sector address" consists of the address bits required to uniquely select a sector. The "Writing specific address and data commands or sequences into the command register initiates device operations. Table 1 defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. Section has details on erasing a sector or the entire chip, or suspending/resuming the erase operation.After the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on Q7-Q0. Standard read cycle timings apply in this mode.Refer to the Autoselect Mode and Autoselect Command Sequence section for more information.ICC2 in the DC Characteristics table represents the active current specification for the write mode. The "AC Characteristics" section contains timing specification table and timing diagrams for write operations. STANDBY MODEWhen using both pins of CE# and RESET#, the device enter CMOS Standby with both pins held at Vcc ± 0.3V. If CE# and RESET# are held at VIH, but not within the range of VCC ±0.3V, the device will still be in the standby mode, but the standby current will be larger. During Auto Algorithm operation, Vcc active current (Icc2) is required even CE# = "H" until the operation is completed. The device can be read with standard access time (tCE) from either of these standby modes, before it is ready to read data.OUTPUT DISABLEWith the OE# input at a logic high level (VIH), output from the devices are disabled. This will cause the output pins to be in a high impedance state.RESET# OPERATIONThe RESET# pin provides a hardware method of resetting the device to reading array data. When the RESET# pin is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tri-states all output pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrityCurrent is reduced for the duration of the RESET# pulse. When RESET# is held at VSS±0.3V, the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS±0.3V, the standby current will be greater.The RESET# pin may be tied to system reset circuitry.A system reset would that also reset the Flash memory, enabling the system to read the boot-up firmware fromMX29LV800BT/BBREAD/RESET COMMANDThe read or reset operation is initiated by writing the read/reset command sequence into the command reg-ister. Microprocessor read cycles retrieve array data. The device remains enabled for reads until the command register contents are altered.If program-fail or erase-fail happen, the write of F0H will reset the device to abort the operation. A valid com-mand must then be written to place the device in the desired state.SILICON-ID READ COMMANDFlash memories are intended for use in applications where the local CPU alters memory contents. As such, manu-facturer and device codes must be accessible while the device resides in the target system. PROM program-mers typically access signature codes by raising A9 to a high voltage (VID). However, multiplexing high volt-age onto address lines is not generally desired system design practice.The MX29LV800BT/BB contains a Silicon-ID-Read op-eration to supple traditional PROM programming meth-odology. The operation is initiated by writing the read silicon ID command sequence into the command regis-ter. Following the command write, a read cycle with A1=VIL, A0=VIL retrieves the manufacturer code of C2H/ 00C2H. A read cycle with A1=VIL, A0=VIH returns the device code of DAH/22DAH for MX29L V800BT, 5BH/ 225BH for MX29LV800BB.SET-UP AUTOMATIC CHIP/SECTOR ERASE COMMANDSChip erase is a six-bus cycle operation. There are two "unlock" write cycles. These are followed by writing the "set-up" command 80H. Two more "unlock" write cy-cles are then followed by the chip erase command 10H or sector erase command 30H.The Automatic Chip Erase does not require the device to be entirely pre-programmed prior to executing the Au-tomatic Chip Erase. Upon executing the Automatic Chip Erase, the device will automatically program and verify the entire memory for an all-zero data pattern. When the device is automatically verified to contain an all-zero pattern, a self-timed chip erase and verify begin. The erase and verify operations are completed when the data on Q7 is "1" at which time the device returns to the Read mode. The system is not required to provide any control or timing during these operations.When using the Automatic Chip Erase algorithm, note that the erase automatically terminates when adequate erase margin has been achieved for the memory array (no erase verification command is required).If the Erase operation was unsuccessful, the data on Q5 is "1" (see Table 8), indicating the erase operation exceed internal timing limit.The automatic erase begins on the rising edge of the last WE# or CE# pulse, whichever happens first in the command sequence and terminates when the data on Q7 is "1" at which time the device returns to the Read mode, or the data on Q6 stops toggling for two consecu-tive read cycles at which time the device returns to the Read mode.the Flash memory.If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a "0" (busy) until the internal reset operation is complete, which requires a time of tREADY (during Embedded Algorithms). The system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is completed within a time of tREADY (not during Embedded Algorithms). The system can read data tRH after the RESET# pin returns to VIH.Refer to the AC Characteristics tables for RESET# parameters and to Figure 22 for the timing diagram.。

HY29F800ABT-70资料

KEY FEATURESn 5 Volt Read, Program, and Erase–Minimizes system-level power requirements n High Performance–Access times as fast as 50 ns n Low Power Consumption–20 mA typical active read current in byte mode, 28 mA typical in word mode –35 mA typical program/erase current – 5 µA maximum CMOS standby current n Compatible with JEDEC Standards–Package, pinout and command-set compatible with the single-supply Flash device standard–Provides superior inadvertent write protectionn Sector Erase Architecture–Boot sector architecture with top and bottom boot block options available–One 16 Kbyte, two 8 Kbyte, one 32 Kbyte and fifteen 64 Kbyte sectors in byte mode –One 8 Kword, two 4 Kword, one 16 Kword and fifteen 32 Kword sectors in word mode – A command can erase any combination of sectors–Supports full chip erase n Erase Suspend/Resume–Temporarily suspends a sector eraseoperation to allow data to be read from, or programmed into, any sector not being erased n Sector Protection–Any combination of sectors may be locked to prevent program or erase operations within those sectorsn Temporary Sector Unprotect–Allows changes in locked sectors(requires high voltage on RESET# pin)n Internal Erase Algorithm–Automatically erases a sector, anycombination of sectors, or the entire chip n Internal Programming Algorithm–Automatically programs and verifies data at a specified addressn Fast Program and Erase Times–Byte programming time: 7 µs typical –Sector erase time: 1.0 sec typical –Chip erase time: 19 sec typicaln Data# Polling and Toggle Status Bits–Provide software confirmation of completion of program or erase operationsn Ready/Busy# Output (RY/BY#)–Provides hardware confirmation of completion of program and erase operationsn Minimum 100,000 Program/Erase Cycles n Space Efficient Packaging–Available in industry-standard 44-pin PSOP and 48-pin TSOP and reverse TSOP packages PreliminaryRevision 1.1, February 2002GENERAL DESCRIPTIONThe HY29F800A is an 8 Megabit, 5 volt only CMOS Flash memory organized as 1,048,576 (1M) bytes or 524,288 (512K) words. The device is offered in industry-standard 44-pin PSOP and 48-pin TSOP packages.The HY29F800A can be programmed and erased in-system with a single 5-volt V CC supply. Internally generated and regulated voltages are provided for program and erase operations, so that the device does not require a high voltage power supply to perform those functions. The device can also be programmed in standard EPROM programmers.Access times as fast as 55 ns over the full operat-ing voltage range of 5.0 volts ± 10% are offered for timing compatibility with the zero wait state require-ments of high speed microprocessors. A 50 nsLOGIC DIAGRAMHY29F800A8 Megabit (1Mx8/512Kx16), 5 Volt-only, Flash Memory元器件交易网2Rev. 1.1/Feb 02HY29F800Aversion operating over 5.0 volts ± 5% is also avail-able. To eliminate bus contention, the HY29F800A has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls.The device is compatible with the JEDEC single power-supply Flash command set standard. Com-mands are written to the command register using standard microprocessor write timings, from where they are routed to an internal state-machine that controls the erase and programming circuits. De-vice programming is performed a byte at a time by executing the four-cycle Program Command.This initiates an internal algorithm that automati-cally times the program pulse widths and verifies proper cell margin.The HY29F800A ’s sector erase architecture allows any number of array sectors to be erased and re-programmed without affecting the data contents of other sectors. Device erasure is initiated by ex-ecuting the Erase Command. This initiates an in-ternal algorithm that automatically preprograms the array (if it is not already programmed) before ex-ecuting the erase operation. During erase cycles,the device automatically times the erase pulse widths and verifies proper cell margin.To protect data in the device from accidental or unauthorized attempts to program or erase the device while it is in the system (e.g., by a virus),the device has a Sector Protect function which hardware write protects selected sectors. The sector protect and unprotect features can be en-abled in a PROM programmer. Temporary Sector Unprotect, which requires a high voltage, allows in-system erasure and code changes in previously protected sectors.Erase Suspend enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. The device is fully erased when shipped from the factory.Addresses and data needed for the programming and erase operations are internally latched during write cycles, and the host system can detect completion of a program or erase operation by observing the RY/BY# pin, or by reading the DQ[7](Data# Polling) and DQ[6] (toggle) status bits.Reading data from the device is similar to reading from SRAM or EPROM devices. Hardware data protection measures include a low V CC detector that automatically inhibits write operations during power transitions.The host can place the device into the standby mode. Power consumption is greatly reduced in this mode.BLOCK DIAGRAM元器件交易网HY29F800A PIN CONFIGURATIONSCONVENTIONSUnless otherwise noted, a positive logic (active High) convention is assumed throughout this docu-ment, whereby the presence at a pin of a higher, more positive voltage (nominally 5VDC) causes assertion of the signal. A ‘#’ symbol following the signal name, e.g., RESET#, indicates that the sig-nal is asserted in a Low state (nominally 0 volts).Whenever a signal is separated into numbered bits, e.g., DQ[7], DQ[6], ..., DQ[0], the family of bits may also be shown collectively, e.g., as DQ[7:0].The designation 0xNNNN (N = 0, 1, 2, . . . , 9, A, . . . , E, F) indicates a number expressed in hexadeci-mal notation. The designation 0bXXXX indicates a number expressed in binary notation (X = 0, 1).元器件交易网3 Rev. 1.1/Feb 02HY29F800AMEMORY ARRAY ORGANIZATIONThe 1 Mbyte Flash memory array is organized into nineteen blocks called sectors (S0, S1, . . . , S18).A sector is the smallest unit that can be erased and which can be protected to prevent accidental or unauthorized erasure. See the ‘Bus Operations’and ‘Command Definitions’ sections of this docu-ment for additional information on these functions. In the HY29F800A, four of the sectors, which com-prise the boot block, vary in size from 8 to 32Kbytes (4 to 16 Kwords), while the remaining fif-teen sectors are uniformly sized at 64 Kbytes (32 Kwords). The boot block can be located at the bottom of the address range (HY29F800AB) or at the top of the address range (HY29F800AT). Table 1 defines the sector addresses and corre-sponding address ranges for the top and bottom boot block versions of the HY29F800A.元器件交易网4Rev. 1.1/Feb 02元器件交易网HY29F800A1.X indicates Don’t Care.2.Address in Byte Mode is A[18:-1].3.Address in Word Mode is A[18:0].5 Rev. 1.1/Feb 02HY29F800A1 Notes:1.L = VIL , H = VIH, X = Don’t Care, DOUT= Data Out, DIN= Data In. See DC Characteristics for voltage levels.2.Address is A[18:-1] in Byte Mode and A[18:0] in Word Mode.3.DQ[15] is the A[-1] input in Byte Mode (BYTE# = L).BUS OPERATIONSDevice bus operations are initiated through the internal command register, which consists of sets of latches that store the commands, along with the address and data information, if any, needed to execute the specific command. The command register itself does not occupy any addressable memory location. The contents of the command register serve as inputs to an internal state ma-chine whose outputs control the operation of the device. Table 2 lists the normal bus operations, the inputs and control levels they require, and the resulting outputs. Certain bus operations require a high voltage on one or more device pins. Those are described in Table 3.Read OperationData is read from the HY29F800A by using stan-dard microprocessor read cycles while placing the address of the byte or word to be read on the device’s address inputs, A[18:0] in Word mode (BYTE# = H) or A[18:-1] in Byte mode (BYTE# = L) . As shown in Table 2, the host system must drive the CE# and OE# inputs Low and drive WE# High for a valid read operation to take place. The device outputs the specified array data on DQ[7:0] in Byte mode and on DQ[15:0] in Word mode. Note that DQ[15] serves as address input A[-1] when the device is operating in Byte mode.The HY29F800A is automatically set for reading array data after device power-up and after a hard-ware reset to ensure that no spurious alteration of the memory content occurs during the power tran-sition. No command is necessary in this mode to obtain array data, and the device remains enabled for read accesses until the command register con-tents are altered.This device features an Erase Suspend mode. While in this mode, the host may read the array data from any sector of memory that is not marked for erasure. If the host attempts to read from an address within an erase-suspended sector, or while the device is performing an erase or byte/ word program operation, the device outputs sta-tus data instead of array data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exceptions noted above. After com-pleting an internal program or internal erase algo-rithm, the HY29F800A automatically returns to the read array data mode.The host must issue a hardware reset or the soft-ware reset command (see Command Definitions) to return a sector to the read array data mode if DQ[5] goes high during a program or erase cycle, or to return the device to the read array data mode while it is in the Electronic ID mode.Write OperationCertain operations, including programming data and erasing sectors of memory, require the host to write a command or command sequence to the HY29F800A. Writes to the device are performed元器件交易网6Rev. 1.1/Feb 02HY29F800A1, 2Notes:1.L = VIL , H = VIH, X = Don’t Care. See DC Characteristics for voltage levels.2.Address bits not specified are Don’t Care.3.See text for additional information.4.SA = sector address. See Table 1.5.DQ[15] is the A[-1] input in Byte Mode (BYTE# = L).by placing the byte or word address on the device’s address inputs while the data to be written is input on DQ[7:0] in Byte mode (BYTE# = L) and on DQ[15:0] in Word mode (BYTE# = H). The host system must drive the CE# and WE# pins Low and drive OE# High for a valid write operation to take place. All addresses are latched on the fall-ing edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first.The ‘Device Commands’ section of this document provides details on the specific device commands implemented in the HY29F800A.Output Disable OperationWhen the OE# input is at VIH , output data from thedevice is disabled and the data bus pins are placed in the high impedance state.Standby OperationWhen the system is not reading from or writing to the HY29F800A, it can place the device in the Standby mode. In this mode, current consump-tion is greatly reduced, and the data bus outputs are placed in the high impedance state, indepen-dent of the OE# input. The Standby mode can invoked using two methods.The device enters the CE# CMOS Standby mode if the CE# and RESET# pins are both held at VCC ± 0.5V. Note that this is a more restricted voltage range than VIH. If both CE# and RESET# are heldHigh, but not within VCC± 0.5V, the device will be in the CE# TTL Standby mode, but the standby current will be greater.The device enters the RESET# CMOS Standbymode when the RESET# pin is held at VSS± 0.5V.If RESET# is held Low but not within VSS± 0.5V, the HY29F800A will be in the RESET# TTL Standby mode, but the standby current will be greater. See Hardware Reset Operation section for additional information on the reset operation.The device requires standard access time (tCE) forread access when the device is in either of the standby modes, before it is ready to read data. If the device is deselected during erasure or pro-gramming, it continues to draw active current until the operation is completed.Hardware Reset OperationThe RESET# pin provides a hardware method ofresetting the device to reading array data. When the RESET# pin is driven Low for the minimum specified period, the device immediately termi-nates any operation in progress, tri-states the data bus pins, and ignores all read/write commands for元器件交易网7 Rev. 1.1/Feb 028Rev. 1.1/Feb 02HY29F800Athe duration of the RESET# pulse. The device also resets the internal state machine to reading array data. If an operation was interrupted by the as-sertion of RESET#, it should be reinitiated once the device is ready to accept another command sequence to ensure data integrity.Current is reduced for the duration of the RESET#pulse as described in the Standby Operation sec-tion above.If RESET# is asserted during a program or erase operation, the RY/BY# pin remains Low (busy) until the internal reset operation is complete, which re-quires a time of t READY (during Automatic Algo-rithms). The system can thus monitor RY/BY# to determine when the reset operation completes,and can perform a read or write operation t RB after RY/BY# goes High. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is High), the reset operation is completed within a time of t RP . In this case, the host can per-form a read or write operation t RH after the RE-SET# pin returns High .The RESET# pin may be tied to the system reset signal. Thus, a system reset would also reset thedevice, enabling the system to read the boot-up firmware from the Flash memory.Sector Protect/Unprotect OperationsHardware sector protection can be invoked to dis-able program and erase operations in any single sector or combination of sectors. This function is typically used to protect data in the device from unauthorized or accidental attempts to program or erase the device while it is in the system (e.g.,by a virus) and is implemented using programming equipment. Sector unprotection re-enables the program and erase operations in previously pro-tected sectors.Table 1 identifies the nineteen sectors and the address range that each covers. The device is shipped with all sectors unprotected.The sector protect/unprotect operations require a high voltage (V ID ) on address pin A[9] and the CE#and/or OE# control pins, as detailed in Table 3.When implementing these operations, note that V CC must be applied to the device before applying V ID , and that V ID should be removed before remov-ing V CC from the device.元器件交易网9Rev. 1.1/Feb 02HY29F800AThe flow chart in Figure 1 illustrates the proce-dure for protecting sectors, and timing specifica-tions and waveforms are shown in the specifica-tions section of this document. Verification of pro-tection is accomplished as described in the Elec-tronic ID Mode section and shown in the flow chart.The procedure for sector unprotection is illustrated in the flow chart in Figure 2, and timing specifica-tions and waveforms are given at the end of this document. Note that to unprotect any sector, all unprotected sectors must first be protected prior to the first unprotect write cycle.Sectors can also be temporarily unprotected as described in the next section.Temporary Sector Unprotect Operation This feature allows temporary unprotection of pre-viously protected sectors to allow changing the data in-system. T emporary Sector Unprotect mode is activated by setting the RESET# pin to V ID . WhileFigure 2. Sector Unprotect Procedurein this mode, formerly protected sectors can be programmed or erased by invoking the appropri-ate commands (see Device Commands section).Once V ID is removed from RESET#, all the previ-ously protected sectors are protected again. Fig-ure 3 illustrates the algorithm.Electronic ID Mode OperationThe Electronic ID mode provides manufacturer and device identification and sector protection verifi-cation through identifier codes output on DQ[7:0]or DQ[15:0]. This mode is intended primarily for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. The Electronic ID infor-mation can also be obtained by the host through a command sequence, as described in the Device Commands section.Operation in the Electronic ID mode requires V ID on address pin A[9], with additional requirements元器件交易网10Rev. 1.1/Feb 02HY29F800A1.Any number of Flash array read cycles are permitted.2.Additional data cycles may follow. See text.3.Any number of Electronic ID read cycles are permitted.DEVICE COMMANDSDevice operations are initiated by writing desig-nated address and data command sequences into the device. A command sequence is composed of one, two or three of the following sub-segments:an unlock cycle , a command cycle and a data cycle . Table 4 summarizes the composition of the valid command sequences implemented in the HY29F800A, and these sequences are fully de-scribed in Table 5 and in the sections that follow.Writing incorrect address and data values or writ-ing them in the improper sequence resets the HY29F800A to the Read mode.Read/Reset 1, 2 CommandsThe HY29F800A automatically enters the Read mode after device power-up, after the RESET#input is asserted and upon the completion of cer-tain commands. Read/Reset commands are not required to retrieve data in these cases.A Read/Reset command must be issued in order to read array data in the following cases:n If the device is in the Electronic ID mode, a Read/Reset command must be written to re-turn to the Read mode. If the device was in the Erase Suspend mode when the device entered the Electronic ID mode, writing the Read/Re-set command returns the device to the Erase Suspend mode.Figure 3. Temporary Sector Unprotect for obtaining specific data items as listed in Table 2:n A read cycle at address 0xXXX00 retrieves the manufacturer code (Hynix = 0xAD).n A read cycle at address 0xXXX01 returns the device code:-HY29F800AT = 0xD6 in Byte mode, 0x22D6in Word mode.-HY29F800AB = 0x58 in Byte mode, 0x2258in Word mode.n A read cycle containing a sector address (Table 1) in A[18:12] and the address 0x02 in A[7:0]returns 0x01 if that sector is protected, or 0x00if it is unprotected.Note: When in the Electronic ID bus operation mode,the device returns to the Read mode when V ID is removed from the A[9] pin. The Read/Reset command is not re-quired in this case.n If DQ[5] (Exceeded Time Limit) goes High dur-ing a program or erase operation, writing the Read/Reset command returns the sectors to the Read mode (or to the Erase Suspend mode if the device was in Erase Suspend).The Read/Reset command may also be used to abort certain command sequences:元器件交易网11Rev. 1.1/Feb 02HY29F800AX = D o n ’t C a r e P A = A d d r e s s o f t h e d a t a t o b e p r o g r a m m e d R A = M e m o r y a d d r e s s o f d a t a t o b e r e a d P D = D a t a t o b e p r o g r a m m e d a t a d d r e s s P A R D = D a t a r e a d f r o m l o c a t i o n R A d u r i n g t h e r e a d o p e r a t i o n S A = S e c t o r a d d r e s s o f s e c t o r t o b e e r a s e d o r v e r i f i e d (s e e N o t e 3 a n d T a b l e 1).S T A T U S = S e c t o r p r o t e c t s t a t u s : 0x 00 = u n p r o t e c t e d , 0x 01 = p r o t e c t e d .N o t e s :1.A l l v a l u e s a r e i n h e x a d e c i m a l. D Q [15:8] a r e d o n ’t c a r e f o r u n l o c k a n d c o m m a n d c y c l e s .2.A l l b u s c y c l e s a r e w r i t e o p e r a t i o n s u n l e s s o t h e r w i s e n o t e d .3.A d d r e s s i s A [10:0] i n W o r d m o d e a n d A [10:-1] i n B y t e m o d e . A [18:11] a r e d o n ’t c a r e e x c e p t a s f o l l o w s :•F o r R A a n d P A , A [18:11] a r e t h e u p p e r a d d r e s s b i t s o f t h e b y t e t o b e r e a d o r p r o g r a m m e d .•F o r t h e s i x t h c y c l e o f S e c t o r E r a s e , S A = A [18:12] a r e t h e s e c t o r a d d r e s s o f t h e s e c t o r t o b e e r a s e d .•F o r t h e f o u r t h c y c l e o f S e c t o r P r o t e c t V e r i f y , S A = A [18:12] a r e t h e s e c t o r a d d r e s s o f t h e s e c t o r t o b e v e r i f i e d .4.T h e E r a s e S u s p e n d c o m m a n d i s v a l i d o n l y d u r i n g a s e c t o r e r a s e o p e r a t i o n . T h e s y s t e m m a y r e a d a n d p r o g r a m i n n o n -e r a s i n g s e c t o r s , o r e n t e r t h e E l e c t r o n i c I D m o d e , w h i l e i n t h e E r a s e S u s p e n d m o d e .5.T h e E r a s e R e s u m e c o m m a n d i s v a l i d o n l y d u r i n g t h e E r a s e S u s p e n d m o d e .6.T h e s e c o n d b u s c y c l e i s a r e a d c y c l e .7.T h e f o u r t h b u s c y c l e i s a r e a d c y c l e .8.E i t h e r c o m m a n d s e q u e n c e i s v a l i d . T h e c o m m a n d i s r e q u i r e d o n l y t o r e t u r n t o t h e R e a d m o d e w h e n t h e d e v i c e i s i n t h e E l e c t r o n i c I D c o m m a n d m o d e o r i f D Q [5] g o e s H i g h d u r i n g a p r o g r a m o r e r a s e o p e r a t i o n . I t i s n o t r e q u i r e d f o r n o r m a l r e a d o p e r a t i o n s .元器件交易网12Rev. 1.1/Feb 02HY29F800Aquence should be reinitiated once the reset op-eration is complete.Programming is allowed in any sequence. Only erase operations can convert a stored “0” to a “1”.Thus, a bit cannot be programmed from a “0” back to a “1”. Attempting to do so will set DQ[5] to “1”,and the Data# Polling algorithm will indicate that the operation was not successful. A Read/Reset command or a hardware reset is required to exit this state, and a succeeding read will show that the data is still “0”.Figure 4 illustrates the procedure for the Byte/Word Program operation.Chip Erase CommandThe Chip Erase command sequence consists of two unlock cycles, followed by the erase command,two additional unlock cycles and then the chip erase data cycle. During chip erase, all sectors of the device are erased except protected sectors.The command sequence starts the Automatic Erase algorithm, which preprograms and verifies the entire memory, except for protected sectors,for an all zero data pattern prior to electrical erase.The device then provides the required number of internally generated erase pulses and verifies cell erasure within the proper cell margins. The host system is not required to provide any controls or timings during these operations.Figure 4. Programming Proceduren In a Sector Erase or Chip Erase command se-quence, the Read/Reset command may be written at any time before erasing actually be-gins, including, for the Sector Erase command,between the cycles that specify the sectors to be erased (see Sector Erase command de-scription). This aborts the command and re-sets the device to the Read mode. Once era-sure begins, however, the device ignores Read/Reset commands until the operation is com-plete.n In a Program command sequence, the Read/Reset command may be written between the sequence cycles before programming actually begins. This aborts the command and resets the device to the Read mode, or to the Erase Suspend mode if the Program command se-quence is written while the device is in the Erase Suspend mode. Once programming begins, however, the device ignores Read/Re-set commands until the operation is complete.n The Read/Reset command may be written be-tween the cycles in an Electronic ID command sequence to abort that command. As described above, once in the Electronic ID mode, the Read/Reset command must be written to re-turn to the Read mode.Byte/Word Program CommandThe host processor programs the device a byte or word at a time by issuing the Program command sequence shown in Table 5. The sequence be-gins by writing two unlock cycles, followed by the Program setup command and, lastly, a data cycle specifying the program address and data. This initiates the Automatic Programming algorithm,which provides internally generated program pulses and verifies the programmed cell margin.The host is not required to provide further controls or timings during this operation. When the Auto-matic Programming algorithm is complete, the device returns to the Read mode. Several meth-ods are provided to allow the host to determine the status of the programming operation, as de-scribed in the Write Operation Status mands written to the device during execution of the Automatic Programming algorithm are ig-nored. Note that a hardware reset immediately terminates the programming operation. To ensure data integrity, the aborted program command se-元器件交易网13Rev. 1.1/Feb 02HY29F800ACommands written to the device during execution of the Automatic Erase algorithm are ignored. Note that a hardware reset immediately terminates the erase operation. To ensure data integrity, the aborted Chip Erase command sequence should be reissued once the reset operation is complete.When the Automatic Erase algorithm is finished,the device returns to the Read mode. Several methods are provided to allow the host to deter-mine the status of the erase operation, as de-scribed in the Write Operation Status section.Figure 5 illustrates the Chip Erase procedure.Sector Erase CommandThe Sector Erase command sequence consists of two unlock cycles, followed by the erase com-mand, two additional unlock cycles and then the sector erase data cycle, which specifies which sector is to be erased. As described later in this section, multiple sectors can be specified for era-sure with a single command sequence. During sector erase, all specified sectors are erased se-quentially. The data in sectors not specified for erasure, as well as the data in any protected sec-tors, even if specified for erasure, is not affected by the sector erase operation.The Sector Erase command sequence starts the Automatic Erase algorithm, which preprograms and verifies the specified unprotected sectors for an all zero data pattern prior to electrical erase.The device then provides the required number of internally generated erase pulses and verifies cell erasure within the proper cell margins. The hostFigure 5. Chip Erase Proceduresystem is not required to provide any controls or timings during these operations.After the sector erase data cycle (the sixth bus cycle) of the command sequence is issued, a sec-tor erase time-out of 50 µs, measured from the rising edge of the final WE# pulse in that bus cycle,begins. During this time, an additional sector erase data cycle, specifying the sector address of an-other sector to be erased, may be written into an internal sector erase buffer. This buffer may be loaded in any sequence, and the number of sec-tors specified may be from one sector to all sec-tors. The only restriction is that the time between these additional data cycles must be less than 50µs, otherwise erasure may begin before the last data cycle is accepted. To ensure that all data cycles are accepted, it is recommended that host processor interrupts be disabled during the time that the additional cycles are being issued and then be re-enabled afterwards.Note: The device is capable of accepting three ways of invoking Erase Commands for additional sectors during the time-out window. The preferred method, described above, is the sector erase data cycle after the initial six bus cycle command sequence. However, the device also accepts the following methods of specifying additional sectors during the sector erase time-out:n Repeat the entire six-cycle command sequence, speci-fying the additional sector in the sixth cycle.n Repeat the last three cycles of the six-cycle command sequence, specifying the additional sector in the third cycle.If all sectors scheduled for erasing are protected,the device returns to reading array data after ap-proximately 100 µs. If at least one scheduled sec-tor is not protected, the erase operation erases the unprotected sectors, and ignores the command for the scheduled sectors that are protected.The system can monitor DQ[3] to determine if the 50 µs sector erase time-out has expired, as de-scribed in the Write Operation Status section. If the time between additional sector erase data cycles can be insured to be less than the time-out, the system need not monitor DQ[3].Any command other than Sector Erase or Erase Suspend during the time-out period resets the device to reading array data. The system must then rewrite the command sequence, including any additional sector erase data cycles. Once the sec-tor erase operation itself has begun, only the Erase元器件交易网。

EN29A0QI 10A PowerSoC 步进电阻调节电源转换器与集成电导体评估板概览说明书

Page 1EN29A0QI 10A PowerSoCStep-Down DC-DC Switching Converter with Integrated Inductor EVALUATION BOARD OVERVIEWFigure 1: Evaluation Board (EVB) Features (Top View)NOTE A : The EN29A0QI Evaluation Board is shown in Figure 1 with the important features numbered. NOTE B : The following instructions will directly correlate with the numbers shown in Figure 1.Evaluation board user guide – enpirion® power solutionsEVALUATION BOARD INSTRUCTIONS 1) Input Supply (VIN) – Connect 9V to 16V supply on VIN (J1). Pay attention to input polarity and do not turn on until everything is connected correctly.2) Ground (GND) – Connect the input and output ground to GND (J2, J4).3) Output Voltage (VOUT) – Connect the load to VOUT (J3). If the instructions were followed up to this point, the device may be powered on. Wait to turn on ENABLE signal in case of using external ENABLE.4) ENABLE (ENA) – ENABLE may be tied to AVIN througha resistor or controller externally. If J6 is connected between positions 2-3, ENABLE is tied to AVIN. Placing a jumper in position 1-2 of J6 disables the device. An external signal (3.3V/1.8V logic) may be applied to TP25 with J6 in position 1-2.5) Output Voltage Settings (J8) - The output voltage may be adjusted quickly by placing a jumper one of the selections on J8. The voltages are pre-set by the resistors R12, R13, R14, R15 and R16 which correspond to 0.9V, 1.03V, 1.12V, 2.5V and 3.3V respectively. The output voltage may also be adjusted to any voltage as indicated by the equation for R B shown in Figure 2. The frequency and compensation network may need to be adjusted for best results.Figure 2: VOUT Resistor Divider & CompensationCapacitor6) Frequency Settings (J7) – The switching frequency may be adjusted quickly by placing a jumper one of the selections on J7. The frequencies are pre-set by the resistors R21, R22, R23, R24 and R25 which correspond to 0.65MHz, 0.75MHz, 0.85MHz, 1.2MHz and 2MHz respectively. The switching frequency is adjusted to match the recommended frequency for the set output voltage. Tabe 1 shows the recommended frequencies for some commonly used output voltages.Table 1: Frequency Recommendations VOUT (V) Frequency (MHz) R FREQ(kΩ)0.75 0.5 60.40.9 0.65 46.41.03 0.75 40.21.12 0.85 35.71.5 1 29.41.8 1.25 23.32.5 1.6 17.43.3 2 13.77) Power OK (POK)– This is an open drain Power OK flag, pulled up to VCC through R20. When VOUT is over 92% of regulation, POK will be pulled high.8) Soft Start Capacitor (C SS)– The soft start capacitor (C27) is 33nF by default and can be between 3.3nF to 680nF. The output rise time is controlled by C SS. The voltage rise time calculation is shown:Rise Time → t RISE [ms] = C ss [nF] x 0.03C SS = 33nF → t RISE≈ 0.99msC SS = 330nF → t RISE≈ 9.9ms9) Soft Shutdown Resistor (J5) – Placing a jumper on J5 enables soft shutdown. The soft shutdown resistor (R7) is 6kΩ by default and can be between 6kΩ to 100kΩ. The output fall time is controlled by R STOP and C SS. The voltage fall time calculation is shown:Fall Time → t STOP [µs] = 3 x C ss [nF] x R STOP[kΩ]C SS = 33nF, R STOP= 6kΩ→ t FALL≈ 594µsC SS = 330nF, R STOP= 10kΩ→ t FALL≈ 9900µs10) Optional Bulk Capacitors – Bulk capacitors may be used on the output to improve load transient response. However, the compensation network must be adjusted accordingly. A downloadable compensation calculation tool is also provided at EN29A0QI’s product page at https:///enpirion for easier calculation and optimization of the compensation components.Page 2。

EN287中文版

EN287中文版焊工的鉴定考查—熔焊第1部分：钢(包括修正A1：1997)DIN EN287-1：1992+A1：1997英文版ICS 25.160.10 代替1992年4月版描述词：焊工鉴定考查，焊接。

欧洲标准EN 287-1：1992+A1：1997具有DIN标准的地位。

逗号用作小数点符号。

国家标准前言：该标准由CEN/TC121制订。

涉及制订本标准的负责德国的团体是焊接标准委员会。

应该注意，现有标准1992年版与1994年版的国际标准ISO 9606-1相同。

一旦后者经实质修改后，它将被用作欧洲标准（即作为EN ISO 9606-1），并代替EN 287-1。

总述本标准的目的是确保焊工的鉴定考查在相同的条件下和使用同类型试件进行，而不管这样的考查在哪里举行。

通过了这里规定的考查，一个焊工便表现出他足以胜任被雇用来在此标准规定的范围内进行工业上的钢熔焊。

于是，本标准提供了由各应用领域的负责团体所颁发的焊工鉴定考查相互承认的基础。

考查人和考查团体本标准不提供焊工鉴定考查中涉及的考查人和考查团体的信息，因为他们表示在有关的法律条例，专业标准，应用法规或技术交付条件中。

当前，下述个人和团体被认为是焊工鉴定考查工作的胜任者：a) 焊接培训考查机关；b) 焊接培训机关；c) 德国焊接协会考试委员会；d) 技术检测协会；e) Amt für Arbeisschutz Hamburg；f) Staatliche Technische überwachung Hessen；g) Deutsche Bahn AG(德国铁路)h) Germanischer Lioyd；i) 由联邦政府或国家当局所委派的考查和检测团体；j) 根据法律条例、实用法规或标准委派的焊接工程师。

Continued overleaf.EN comprises 24 pages.— 1 —应当注意，法律条例，实用法规和标准可能包含关于考查人和考查团体的限制或附加条款（例如关于委派：对照DIN EN 45013）。