综合评价议价系统用户手册V2011(2012-05-25)

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Windows Server 2012 操作系统部署和服务器虚拟化Hype-V部署配置

*注：计算机型号不同，可能开机选择启动设备的快捷键不同，通常情况下均是 F12
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Microsoft OEM ROK Windows Server 2012 操作系统部署和服务器虚拟化专题实验手册 10) 系统将自动进入到区域选择界面，在这个界面将确定计算机的安装界面语言和区域设置，保持默认即可。
9)
在‘确认安装所选内容’页面，单击‘指定备用源路径’。
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Microsoft OEM ROK Windows Server 2012 操作系统部署和服务器虚拟化专题实验手册 10) 弹出‘添加角色和功能向导’的‘指定备用源路径’对话框。在‘路径’右侧的文本框中输入‘步骤一中的 DVD 驱动器盘符:\Sources\SxS\’，单击‘确定’。
11) 在‘确认安装所选内容’页面，单击‘安装’。 12) 安装成功后，单击‘关闭’。 2. Windows7-USB-DVDTools 此工具用来制作 USB 安装盘 2) 安装步骤都选择默认设置，安装完成后，会在桌面出现如下图标： 1) 找到位于 E:\LabData\Windows7-USB-DVD-Tool.exe 文件，双击运行安装。
7) 8) 9)
在‘选择功能’页面，单击‘下一步’。在‘Hyper-V’页面，单击‘下一步’。在‘创建虚拟交换机’页面，单击‘下一步’。
10) 在‘虚拟机迁移’页面，单击‘下一步’。 11) 在‘默认存储’页面，将‘虚拟机硬盘文件’和‘虚拟机配置文件’的路径改成 ‘D:\Hyper-V\’，单击‘下一步’。
microsoftoemrokwindowsserver2012操作系统部署和服务器虚拟化专题实验手册2065microsoftoemrokwindowsserver2012操作系统部署和服务器虚拟化专题实验手册2165microsoftoemrokwindowsserver2012操作系统部署和服务器虚拟化专题实验手册2265microsoftoemrokwindowsserver2012操作系统部署和服务器虚拟化专题实验手册2365microsoftoemrokwindowsserver2012操作系统部署和服务器虚拟化专题实验手册24安装集成服务可以提高速度也可以使你的鼠标在虚拟机与物理机之间自由切在windowsserver2008r2虚拟机连接窗口菜单栏中单击操作选择插入集成服务安装盘

LMK00301 评估板用户指南说明书

This user guide describes how to set up and operate the LMK00301 evaluation board kit (EVK). The LMK00301 isclock/data[LMK00301 EVALUATION BOARD USER GUIDE] Evaluation Board Quick StartTo quickly set up and operate the board with basicequipment, refer to the quick start procedure belowand test setup shown in Figure 2.1.Verify the output mode control switches,S1[1:5], match the states shown in Table 1 toreflect the default output clock interfacesconfigured on the EVK.Table 1. Default Clock Output Modes / InterfacesSW Position/Name SW State Default Clock Output ModesS1[1] / CLKoutB_Type1 0 (OFF) Bank B outputsare LVDSS1[2] / CLKoutB_Type0 1 (ON)S1[3] / CLKoutA_Type1 0 (OFF) Bank A outputsare LVPECL S1[4] / CLKoutA_Type0 0 (OFF)S1[5] / REFout_EN 1 (ON) REFout enabled 2.Connect the VCC_EXT and GND leads from theboard to a 4 V - 16 V source. This powers anonboard LDO regulator that provides 3.3 V toVCC and VCCO supplies of the IC. Both VCC &VCCO status LED should be lit green when ON.3.Set the desired clock input using the inputselection control switches, S1[6:7], per Table 2.The onboard 25 MHz crystal (Y1) is selected by default, so an external clock source is notrequired. A differential clock source can beconnected to SMAs CLKin0/0* or CLKin1/1*. Table 2. Input Selection (0=SW OFF, 1=SW ON)Selected Input Default InputModeS1[6]CLKin_Sel1StateS1[7]CLKin_Sel0StateCLKin0/0* Differentialclock0 0CLKin1/1* Differentialclock0 1OSCin 25 MHz XTALonboard1 Don’t careCLKin0/0* and CLKin1/1* paths are configured by default to receive a differential clock as the input. The SMA inputs are DC coupled to the device inputs and terminated with 100 ohms differential. Refer to the Clock Inputs section to configure the EVK for a single-ended input.4.Connect and measure any clock output SMAlabeled CLKoutX#/X#* or REFout to anoscilloscope or other test instrument using SMA cable(s). The output clock will be level-translated/buffered copy of the selected clockinput or crystal oscillator. Note: All outputclocks are AC-coupled to the SMA connectors to ensure safe use with RF instruments.Note: Leaving a driven output(s) without proper load termination can cause signal reflections on the board, which can couple onto nearby outputs and result in degraded signal quality and erroneous measurements. To minimize these effects, be sure to properly terminate any unused output path using an SMA load or solder termination resistors on the loading options near the edges of the board. Another option is to disconnect the unused output pin from the trace by removing the series 0-ohm resistor. An unused output bank may also be disabled using the output mode control switch.Signal Path and Control SwitchesThe LMK00301 supports single-ended or differential clocks on CLKin0 and CLKin1. A third input, OSCin, has an integrated crystal oscillator interface that supports a fundamental mode, AT-cut crystal or an external single-ended clock. The three-input multiplexer is pin-controlled. To achieve the maximum operating frequency and lowest additive jitter, it is recommended to use a differential clock with high input slew rate (>3 V/ns) and DC-coupling to either CLKin0 or CLKin1 port.The device provides up to 10 differential outputs split between Bank A and Bank B, where each bank has a pin-controlled output mode (LVPECL, LVDS,[LMK00301 EVALUATION BOARD USER GUIDE]HCSL, or Hi-Z). An additional output, REFout, has afixed LVCMOS buffer with output enable input.All control pins are configured with the controlswitch, S1. The input selection logic is shown inTable 2. The Bank A and Bank B output modeselection logic are shown in Table 3 and Table 4.The REFout enable logic is shown in Table 5.Table 3. Bank A Output Mode Selection (0=OFF, 1=ON)Bank A Output ModeS1[3]CLKoutA_Type1StateS1[4]CLKoutA_Type0StateLVPECL 0 0LVDS 0 1HCSL 1 0 Disabled/Hi-Z 1 1 Table 4. Bank B Output Mode Selection (0=OFF, 1=ON)Bank B Output ModeS1[2]CLKoutA_Type1StateS1[1]CLKoutA_Type0StateLVPECL 0 0LVDS 0 1HCSL 1 0 Disabled/Hi-Z 1 1 Table 5. REFout Enable Selection (0=OFF, 1=ON)REFout Enable Mode S1[5]REFout_EN State Disabled/Hi-Z 0Enabled 1 Power SuppliesThe power supply section on the EVK provides flexibility to power the device using the onboard LDO regulator(s) or direct supply input(s). A combination of 0-ohm resistor options allows the user to modify the EVK power supply configuration, if desired.By default, 3.3 V (VCC and VCCO) is supplied by one of the onboard LDO regulators, U1. To power the regulator, connect a 4 V – 16 V input voltage and ground from an external power source to the terminal block, J2, or SMA input labeled VCC_EXT.To modify the EVK with a different power supply configuration, populate the resistor options as shown in Table 6. Then, apply the appropriate voltage(s) to the EVK power input(s).If the EVK is configured for dual external input supplies, connect the 2.5 V input voltage and ground from another external power source to the SMA input labeled VCCO_EXT.Decoupling capacitors and 0-ohm resistor footprints, which can accommodate ferrite beads, can be used to isolate the EVK power input(s) from the device power pins.Table 6. EVK Power Supply Configuration OptionsSingle LDO 3.3 V (Default) Single Ext. Input3.3 VDual LDO3.3 V / 2.5 VDual Ext. Inputs3.3 V / 2.5 VVCC_EXT input Apply 4 V – 16 V Apply 3.3 V ± 5% Apply 4 V – 16 V Apply 3.3 V ± 5% VCCO_EXT input Not used Not used Not used Apply 2.5 V ± 5% U2 output (VCCO) Not used Not used 2.5 V Not usedU3 output (VCC) 3.3 V (VCC & VCCO) Not used 3.3 V Not used R131 DNP DNP DNP 0R132 0 0 DNP 0R134 DNP DNP 0 DNPR145 DNP DNP 0 DNPR153 DNP 0 DNP 0R155 0 DNP 0 DNPTo limit crystal power dissipation, a 1 k resistor is placed between the OSCout pin and the crystal.Configuring OSCin for a Single-Ended Input To configure a single-ended clock input on OSCin, remove R34 and R37 to disconnect the crystal. OSCin path is includes a 51- termination on R40.By default, Bank A outputs are configured for LVPECL mode and source-terminated with 240 ohmsuch as 91 , to maintain proper DC bias current on each output.SchematicsSee the following pages.[LMK00301 EVALUATION BOARD USER GUIDE] Figure 4. Schematic Sheet #1[LMK00301 EVALUATION BOARD USER GUIDE]Figure 5. Schematic Sheet #2[LMK00301 EVALUATION BOARD USER GUIDE] Figure 6. Schematic Sheet #3[LMK00301 EVALUATION BOARD USER GUIDE] PCB LayoutFigure 7. Top Side, Layer #1 (Not to scale)[LMK00301 EVALUATION BOARD USER GUIDE] Figure 8. Internal Ground Plane, Layer #2 (Layer Inverted, Not to scale)[LMK00301 EVALUATION BOARD USER GUIDE] Figure 9. Internal Power Plane, Layer #3 (Not to scale)[LMK00301 EVALUATION BOARD USER GUIDE] Figure 10. Bottom Side, Layer #4 (Top view, Not to scale)[LMK00301 EVALUATION BOARD USER GUIDE]Figure 11. Top Silkscreen (Not to scale)[LMK00301 EVALUATION BOARD USER GUIDE] Figure 12. Bottom Silkscreen (Top view, Not to scale)[LMK00301 EVALUATION BOARD USER GUIDE]Bill of MaterialsItem Designator Description Manufacturer Part Number Qty 1 AA1 Printed Circuit Board LMK00301EVAL 12 C1, C4, C60,C64, C65, C67,C71, C72 CAP, CERM, 10uF, 10V, +/-10%, X5R, 0805MuRata GRM21BR61A106KE19L 83 C2, C5, C61,C68 CAP, CERM, 1uF, 16V, +/-10%, X7R, 0603TDK C1608X7R1C105K 44 C3, C6, C23,C28, C29, C32,C33, C34, C35,C38, C39, C40,C41, C44, C45,C46, C47, C50,C51, C52, C53,C56, C57, C58,C59 CAP, CERM, 0.1uF, 16V, +/-10%, X7R, 0603TDK C1608X7R1C104K 255 C7, C12, C14,C17, R5, R6,R7, R8, R10,R11, R13, R14,R15, R16, R22,R27, R28, R33,R36, R37, R38,R45, R46, R47,R48, R50, R51,R53, R54, R55,R56, R132,R155, R156RES, 0 ohm, 5%, 0.1W, 0603 Vishay-Dale CRCW06030000Z0EA 346 C8, C9, C16,C20, C21, C26,C27, C62, C69 CAP, CERM, 0.01uF, 16V, +/-10%, X7R, 0402TDK C1005X7R1C103K 97 C18, C22 CAP, CERM, 33pF, 50V, +/-5%, C0G/NP0, 0603MuRata GRM1885C1H330JA01D 28 C63, C70 CAP, CERM, 2200pF, 100V,+/-5%, X7R, 0603AVX 06031C222JAT2A 2 9 C66, C73 CAP, CERM, 0.01uF, 25V, +/-5%, C0G/NP0, 0603TDK C1608C0G1E103J 2[LMK00301 EVALUATION BOARD USER GUIDE]10 CLKin0,CLKin0*,CLKin1,CLKin1*,CLKoutA0,CLKoutA0*,CLKoutA1,CLKoutA1*,CLKoutA2,CLKoutA2*,CLKoutA3,CLKoutA3*,CLKoutA4,CLKoutA4*,CLKoutB0,CLKoutB0*,CLKoutB1,CLKoutB1*,CLKoutB2,CLKoutB2*,CLKoutB3,CLKoutB3*,CLKoutB4,CLKoutB4*,OSCin, REFout,VCC_EXT,VCCO_EXT Connector, SMT, End launchSMA 50 ohmEmerson NetworkPower142-0701-806 2811 D1, D2 LED 2.8X3.2MM 565NM GRNCLR SMD LumexOpto/ComponentsInc.SML-LX2832GC 212 FID1, FID2,FID3, FID4 Fiducial mark. There is nothingto buy or mount.N/A N/A 413 J1 Low Profile Vertical Header 2x50.100"FCI 52601-G10-8LF 114 J2 CONN TERM BLK PCB5.08MM 2POS ORWeidmuller 1594540000 115 R24, R31 RES, 100 ohm, 5%, 0.1W,0603Vishay-Dale CRCW0603100RJNEA 2 16 R34 RES, 1.0k ohm, 5%, 0.1W,0603Vishay-Dale CRCW06031K00JNEA 1 17 R40 RES, 51 ohm, 5%, 0.1W, 0603 Vishay-Dale CRCW060351R0JNEA 118 R41, R42, R43,R44, R49, R52,R57, R58, R59,R60 RES, 160 ohm, 5%, 0.1W,0603Vishay-Dale CRCW0603160RJNEA 1019 R133, R154 RES, 270 ohm, 5%, 0.1W,0603Vishay-Dale CRCW0603270RJNEA 220 R135, R136,R137, R140,R141, R142,R143 RES, 2.0k ohm, 5%, 0.1W,0603Vishay-Dale CRCW06032K00JNEA 721 R138, R157 RES, 51k ohm, 5%, 0.1W, 0603 Vishay-Dale CRCW060351K0JNEA 222 R139 RES, 1.30k ohm, 1%, 0.1W,0603Vishay-Dale CRCW06031K30FKEA 1[LMK00301 EVALUATION BOARD USER GUIDE]23 R144, R159 RES, 866 ohm, 1%, 0.1W,0603Vishay-Dale CRCW0603866RFKEA 224 R158 RES, 2.00k ohm, 1%, 0.1W,0603Vishay-Dale CRCW06032K00FKEA 1 25 S1 SWITCH DIP ROCKER 8POSSMDTyco GDR08S04 1 26 SO1, SO2, SO3,SO40.875" Standoff VOLTREX SPCS-14 427 U1 High-Performance DifferentialFanout Buffer NationalSemiconductorLMK00301 128 U2, U3 Micropower 800mA Low Noise'Ceramic Stable' AdjustableVoltage Regulator for 1V to 5VApplications, 8-pin LLP NationalSemiconductorLP3878SD-ADJ 229 Y1 CRYSTAL 25.000 MHZ 18PFSMD AbraconCorporationABLS-25.000MHZ-B4-F-T130 C10, C11, C13,C15, C19, C24,C30, C31, C36,C37, C42, C43,C48, C49, C54,C55DNP 031 C25 DNP 032 R1, R2, R3, R4,R9, R12, R17,R18, R19, R20DNP 033 R21, R23, R25,R26, R30, R32,R35, R39, R65,R66, R67, R68,R69, R70, R79,R80, R81, R82,R83, R84, R93,R94, R95, R96,R97, R98, R107,R108, R109,R110, R111,R112, R121,R122, R123,R124, R125,R126DNP 034 R29, R131,R134, R145,R153DNP 0[LMK00301 EVALUATION BOARD USER GUIDE]35 R61, R62, R63,DNP 0 R64, R71, R72,R73, R74, R75,R76, R77, R78,R85, R86, R87,R88, R89, R90,R91, R92, R99,R100, R101,R102, R103,R104, R105,R106, R113,R114, R115,R116, R117,R118, R119,R120, R127,R128, R129,R130DNP 0 36 R146, R147,R148, R149,R150, R151,R15237 Y2 DNP 038 VCC_EXT Banana plug, Red Emerson 108-0302-001 139 GND Banana plug, Black Emerson 108-0303-001 1IMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries(TI)reserve the right to make corrections,modifications,enhancements,improvements, and other changes to its products and services at any time and to discontinue any product or service without notice.Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty.Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty.Except where mandated by government requirements,testing of all parameters of each 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CTP综合交易平台教程

CTP综合交易平台教程基本介绍一、系统简介交易托管系统 API 是一个基于 C++的类库, 通过使用和扩展类库提供的接口来实现相关交易功能，包括报单与报价的录入、报单与报价的撤销、报单与报价的挂起、报单与报价的激活、报单与报价的修改、报单与报价的查询、成交单查询、投资者查询、投资者持仓查询、合约查询、交易日获取等。

支持 MS VC 6.0，MS 2003 编译器。

需要打开多线程编译选项/MT。

二、体系结构交易员 API 使用建立在 TCP 协议之上 FTD 协议与交易托管系统进行通讯，交易托管系统负责投资者的交易业务处理。

2.1.通讯模式FTD 协议中的所有通讯都基于某个通讯模式。

通讯模式实际上就是通讯双方协同工作的方式。

FTD 涉及的通讯模式共有三种：l 对话通讯模式l 私有通讯模式l 广播通讯模式对话通讯模式是指由会员端主动发起的通讯请求。

该请求被交易所端接收和处理，并给予响应。

例如报单、查询等。

这种通讯模式与普通的客户/服务器模式相同。

私有通讯模式是指交易所端主动，向某个特定的会员发出的信息。

例如成交回报等。

广播通讯模式是指交易所端主动，向市场中的所有会员都发出相同的信息。

例如公告、市场公共信息等。

通讯模式和网络的连接不一定存在简单的一对一的关系。

也就是说，一个网络连接中可能传送多种不同通讯模式的报文，一种通讯模式的报文也可以在多个不同的连接中传送。

无论哪种通讯模式，其通讯过程都如图 1 所示本接口暂时没有使用广播通信方式。

2.2.数据流交易托管系统支持对话通讯模式、私有通讯模式、广播通讯模式：对话通讯模式下支持对话数据流和查询数据流：对话数据流是一个双向数据流，交易托管系统发送交易请求，交易系统反馈应答。

交易系统不维护对话流的状态。

系统故障时，对话数据流会重置，通讯途中的数据可能会丢失。

查询数据流是一个双向数据流，交易托管系统发送查询请求，交易系统反馈应答。

交易系统不维护查询流的状态。

议价操作手册

“议价”操作手册：
一、本操作手册适用于“湖北省基本药物及常用低价药品集中采购系统”中议价药品（除常用低价药外）；
二、医疗机构和企业需对挂网药品（常用低价药除外）进行议价的，线下签订议价合同后，由医疗机构将议价结果输入至系统，配送企业进行确认后，线上完成药品交易。

可议价的药品有：补充药品（定点生产除外）、直接挂网-临床用量小（基药）、直接挂网-妇儿急救（基药）。

三、常用低价药议价见其它操作手册
四、议价结果输入至系统的具体方法
1.医疗机构/村卫生室客户端：
如何输入议价结果?
进入采购管理-新建采购单页面，在新建采购单(需求单)后，进入到新增采购明细的页面，在“实际采购价”可修改的情况下，输入当前行药品的实际采购价格。

输入完成“实际采购价”和“采购数量”后，点击“加入采购单”或者“制单完成”即可。

如何查看历史议价结果（交易价格）？
直接点击“查看历史采购价”来查看历史采购价数据。

2.配送企业客户端：
如何查看医疗机构输入的议价结果信息？并确认议价结果？
进入“订单确认”页面（见下图），页面中“实际采购价（医院输入）”为该药品的议价结果信息（也就是实际交易价格）。

若“实际采购价（医院输入）”中的价格与线下签订的议价合同一致，点击“确认”；若不一致，点击“无法配送”同时输入“无法配送原因”。

广东省基本药物集中采购综合评价议价系统用户手册V2011

广东省医药采购平台2011年基本药物集中采购综合评价议价系统用户手册V2011广东省医药采购采购中心2012年2月7日目录版本历史 (ii)第1章说明 (3)第2章系统需求 (4)第3章登录与退出系统 (6)3.1登录前的准备（适于新用户） (6)3.1.1安装驱动程序 (6)3.1.2数字证书查验 (8)3.1.3修改数字证书的密码 (9)3.1.4备Key与主Key等同使用 (11)3.2使用数字证书登录 (11)3.3设置用户名和密码 (13)3.4使用用户名密码登录 (13)3.5退出系统 (13)3.6登录异常的处理 (14)第4章签名控件的安装和检查 (15)第5章用户管理 (16)5.1采购中心管理被授权人 (16)5.2被授权人管理普通用户 (16)5.2.1添加用户 (16)5.2.2给新增用户授权 (17)5.2.3删除用户 (18)第6章产品管理 (20)6.1查看已报名产品 (21)6.2查看被取消报名的产品 (21)6.3查看产品库及初审情况 (22)6.4查看综合评价 (22)6.5查看代表品及限价 (23)6.6查看产品分组 (23)第7章进口产品报名操作的特殊性 (25)7.1进口产品网上报名 (25)7.2查看已报名的进口产品 (26)7.3取消已报名的进口产品 (26)第8章报价 (29)8.1报价前的准备工作 (29)8.2报价操作 (29)第9章议价价格确认 (31)附录A 报价期间计算机相关疑难问题解答 (33)版本历史1. 最后更新：2011年12月28日第一版2. 最后更新：2011年12月29日简化签名控件的安装。

3. 最后更新：2012-02-07增加查看产品分组功能。

第1章说明本手册仅对投标企业用户在基本药物集中采购综合评价议价系统进行操作的流程进行说明，并不是整个投标活动的流程说明。

第2章系统需求为保证正常使用综合评价议价系统，请按以下清单检查您的计算机是否符合要求，特别是在报价前应再认真检查一遍。

VSC8514評估板用戶指南说明书

VSC8514User Guide VSC8514 Evaluation BoardMarch 2014Contents1Revision History (1)1.1Revision 1.0 (1)2Introduction (2)3General Description (3)3.1Key Features (3)3.1.1Copper Port RJ45 Connections (3)3.1.2Zarlink ZL30343 SyncE G.8262/SETS (3)3.1.3External RefClk Option (4)3.1.4Recovered Clocks (4)4Quick Start (5)4.1Connecting the Power Supply (5)4.2PC Software Installation (5)4.3Connecting to the Board to the PC (5)4.3.1Changing the IP Address of the Board (5)4.4Using the Control Software (6)4.4.1Board Initialization (7)4.4.2Copper Media Operation (Auto-negotiation Enabled) (7)4.4.3Sync-E Operation (8)4.5Useful Registers (8)4.5.1Ethernet Packet Generator (8)4.5.2Copper PHY Error Counters (8)4.5.3Near-End Loopback (8)4.5.4Far-End Loopback (8)4.5.5QSGMII SerDes Loopback (8)5Additional Information (9)1Revision HistoryThe revision history describes the changes that were implemented in this document. The changes arelisted by revision, starting with the most current publication.1.1Revision 1.0Revision 1.0 of this datasheet was published in March 2014. This was the first publication of thedocument.2IntroductionThe VSC8514 device is a low-power, quad-port Gigabit Ethernet transceiver with copper mediainterfaces. The device includes an integrated quad two-wire serial multiplexer (MUX) to control powerover Ethernet (PoE) modules. It features low electromagnetic interference (EMI) line drivers andintegrated line side termination resistors that conserve both power and board space. Dual recoveredclock outputs are available to support Synchronous Ethernet (Sync-E) applications, each withprogrammable squelch options.This document describes the architecture and usage of the VSC8514 Evaluation Board (VSC8514EV). TheQuick Start section describes how to install and run the graphical user interface (GUI) to fully control theevaluation board.Figure 1 • VSC8514 Evaluation BoardAdditional VSC8514 collateral for both the VSC8514 device and VSC8514EV, including schematics,layout, GUI, and application notes can be found on the VSC8514 product web page at: https://www./products/product.php?number=VSC8514.3General DescriptionThe evaluation board, shown in Figure 1, provides the user a way to evaluate the VSC8514 device inmultiple configurations. Four RJ-45 connectors are provided for copper media interfaces. The MACinterface is exposed via SMA connectors.For access to all of the features of the device, an external microcontroller is used to configure the on-board clock chip via a two wire serial bus and the VSC8514 via the MDIO bus. The GUI enables the userto read and write device registers.3.1Key Features3.1.1Copper Port RJ45 ConnectionsPHY ports 2 and 3 use the UDE RTA 1648BAK1A with integrated magnetic while PHY ports 0 and 1 usegeneric RJ45 connectors with discrete Pulse H5008NL magnetics.SGMII/QSGMII MAC SMAThe QSGMII differential input port is available through SMA connectors J1 and J2, while the output portis available through SMA connectors J4 and J5. Both of them are AC coupled.Switch Block ControlSW1 controls COMA_MODE, CLK_SQUELCH_IN and REFCLKSEL_[1:0]. The default configuration is withall switches set to low as shown in the figure below.Figure 2 • SW1 Switch Control3.1.2Zarlink ZL30343 SyncE G.8262/SETSThe Silabs F311 micro-controller is pre-programmed to configure the Zarlink ZL30343 to provide a 125MHz differential LVPECL clock to the VSC8514 REFCLK input, either based on the 20 MHz on-boardcrystal, or RCVRDCLK1 from the VSC8514 (Sync-E mode). When RCVRDCLK1 is enabled to output aproper 125 MHz clock, the ZL30343 will generate a 125 MHz output clock synchronized to theRCVRDCLK1 and will switch from HOLDOVER mode to LOCK mode as indicated by LEDs D33 and D34 asshown in the figure below.The left side of the illustration shows the HoldOver mode and the right side shows the Lock mode.Figure 3 • ZL30343 LED Indication3.1.3External RefClk OptionThe user may choose to provide an external PHY REFCLK via SMA connections to J21 and J23 (as shownin Figure 3 above). To route the SMA signals to the device the user must reorient the zero ohm resistors,R151, and R152.3.1.4Recovered ClocksThere are two recovered clocks available from the VSC8514, through J22 and J24. In the defaultconfiguration, CLK_SQUELCH_IN is pulled down, which disables the clock squelching and RCVRDCLK1 isconnected to the Zarlink device while RCVRDCLK2 is connected to SMA connector J24. RCVRDCLK1 andRCVRDCLK2 connections can be reconfigured by replacing the zero ohm resistors, R19, and R22,respectively.Network Interface Microcontroller CardA “Rabbit” microcontroller card is included to facilitate a software interface to the registers on theVSC8514. The controller card has a hard coded static IP address. Refer to the label on the card for thevalue. This address is required by the user to initiate communications via the board and the GUI.10.9.70.193The factory programmed Rabbit board IP address is: .1. 2. 3. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 4Quick Start This section shows the quick start for VSC8514.4.1Connecting the Power SupplyThe evaluation board uses 5 VDC to power the on-board regulators creating the 3.3 V, 2.5 V, and 1.0 V rails which drive the devices as well as modules. The evaluation board can be powered using the power pack which provides the 5 VDC. Simply plug the AC adaptor into a wall socket and the barrel end into J67 (see the upper right corner of Figure 1). Immediately the user should see several LEDs turn on.The user may alternately connect the board to a bench style power supply by connecting the red banana plug to 5 VDC and the black banana plug to ground. If the supply provides 3 A the board should come alive as described above.4.2PC Software InstallationDownload the ZIP file to the PC’s root directory, normally C:\.Extract to C:\Double click the icon to launch the GUI (It is acceptable to drag the icon to the desktop)4.3Connecting to the Board to the PCThe Rabbit board can interface with a PC either through a direct connection to the PC or if configured properly through a local area network. The latter option requires the user to configure the Rabbit’s IP address so as to properly reside on the user’s network.The IP address of the board should be written on the Rabbit network interface daughter board card. The default value should be 10.9.70.193. You will need to use this IP address to initially access the board for operation or to change its IP address.4.3.1Changing the IP Address of the BoardDetermine and write down the new unique IP address you wish to change the board to.Directly connect an Ethernet cable from a PC to the Rabbit board.: Some older PCs do not support auto-crossover on the Ethernet connection so a cross-over NOTE cable may be unch a DOS command window by clicking on the Start->Run button and typing “cmd”.Within the DOS command window type “Telnet”.In the Telnet window, connect to the Rabbit board’s address using the open command by typing open 10.9.70.193, as this is the factory default address.You should have a prompt and be able to type help to get a list of commands available on the Rabbit.a.) If you are unable to connect, then most likely you will need to change the IP address of the connected PC to have the first 3 octets similar to the board by following the subsequent steps.b.) On the PC under Windows -> Control Panel ->Network Connections -> Local Area Connection, right mouse click for Properties. Under the General tab highlight Internet Protocol (TCP/IP) and click on Properties. From there enter the new PC IP address such as 10.9.70.yyy where yyy is a unique value and NOT the same as the Rabbit board. Once complete, return to step 4.From the Telnet window, update the IP address by typing set ip <new IP address> <Enter>, where <new IP address> is in the form of xxx.xxx.xxx.xxx.After hitting <Enter> the IP address will change and the Rabbit will save the value and reboot which may take approximately 1 minute.The Telnet session will disconnect from the board.Change your PC IP address to the same IP network as the Rabbit board.Telnet to the Rabbit e the following commands to complete configuration of the Rabbit board configuration:a) set netmask xxx.xxx.xxx.xxx b) set gateway xxx.xxx.xxx.xxx c) save envPlease record and inform Microsemi of the new IP address of the board when you return so that11. 12. Please record and inform Microsemi of the new IP address of the board when you return so that Microsemi can connect to and reconfigure the board.Re-label the Rabbit board with the new IP.4.4Using the Control SoftwareConnect the VSC8514EV Rabbit microcontroller’s RJ-45 directly to the PC or through a network switch if properly configured. Apply 5 VDC to the EVB.Launch the GUI by double clicking the GUI shortcut located in C:\EliseGUI_4_67 or on the desktop if it has been moved there. The GUI connection window shown in the figure below should appear.Figure 4 • GUI Connection WindowTo make a connection to the EVB, click “Rabbit” and enter the IP address of the EVB, then click on “Connect”. The display next to the IP address window should change to “Connected”. If it does not, check the IP address, or your network configuration until the connection with the EVB can be successfully established.Double click on “MII Registers” and the window shown in the following figure should appear:1. Double click on “MII Registers” and the window shown in the following figure should appear:Figure 5 • MII Registers GUI WindowBe sure the device is up and running by reading MII Register 0. It should read back 0 × 1040. Reading back all 0’s or all 1’s indicates a problem. A checked box means the bit is set to “1,” if unchecked it is “0.”4.4.1Board InitializationOnce the evaluation board connectivity has been established and confirmed, the PHY should be initialized. Initialization can be accomplished by running an init-script sequence, such as performed by the pre- and post-reset functions of the PHY API standalone app.While the init-script sequence may not be required for specific operational modes, an init-script sequence is highly recommended to ensure correct performance over the greatest set of user scenarios for the PHY. After initialization is performed, refer to the PHY datasheet section on configuring the PHY and PHY Interfaces for the desired application.4.4.2Copper Media Operation (Auto-negotiation Enabled)A single register write and some external coax cables enables 1 G Ethernet traffic to be received by the VSC8514 RJ-45 port(s), routed through the VSC8514 and externally looped back via coax cables through the QSGMII interface and transmitted back to the traffic source on the same copper port(s).The following steps are used to setup an external QSGMII loopback:Set up the copper traffic source (i.e., IXIA or Smartbits)1. 2. 3. 4. 5. 6. 7. Set up the copper traffic source (i.e., IXIA or Smartbits)Connect Ethernet cable(s) to a single or multiple RJ-45 ports.Connect two matched coax cables, J1 - J4 and J2 - J5.Write using the "Micro Page Registers" window: 19'd 0 × 400F.Write using the "Micro Page Registers" window: 18'd 0 × 80E0.When "Micro Page" 18'd is read back, bit 15 will clear.Linkup bit is in MII Reg 1, bit 2 (MII 1.2), read twice to update.Traffic should be the following:4.4.3Sync-E OperationTo enable 12 MHz Sync-E operation on this evaluation board a few register writes are required. Write 0 × 8101 on register 23’d of the “Micro Page Registers” to enable RCVRDCLK1 with PHY0 as the clock source when PHY0’s link is up in a non-EEE mode and not 1000BT master or 10BT. To select a different port as the clock source or enable a recovered clock for EEE mode, refer to register 23 G in the datasheet for the programming detail. Set MII Reg.9 bit 12 to enable manual slave configuration then issue an auto negotiation restart through reg.0 bit 9.4.5Useful Registers 4.5.1Ethernet Packet GeneratorExtMII 29E is the Ethernet Packet Generator register. Refer to the datasheet for configuration options.A good CRC packet counter is in ExtMII 18.13:0. A read of the register reads back the good CRC packets and then clears the register so the subsequent reads will be 0 if no traffic has been received. If traffic has been received since the last read, bit 15 will be set.4.5.2Copper PHY Error CountersIdle errors = MII 10.7:0RX errors = MII 19.7:0False carrier = MII 20.7:0Disconnects = MII 21.7:0CRC errors = ExtMII 23.7:04.5.3Near-End LoopbackWhen the near-end loopback test feature is enabled, the transmitted data is looped back in the PCS block on the receive data signals. To enable the loopback, set register bit.0.14 to 1.4.5.4Far-End LoopbackWhen the far-end loopback test feature is enabled, incoming data from a link partner on the Copper interface to be transmitted back to the link partner on the Copper interface. To enable the loopback, set register bit.23.3 to 1.4.5.5QSGMII SerDes LoopbackThere are 3 different types of loopback that occurs in the SerDes block:Input loopback: loops serial data from TDP/N onto RDP/N by writing 0 × 9022 to reg.18G Facility loopback: loops de-serialized data from TDP/N back to the serialized data onto RDP/N by writing 0 × 9022 to reg.18G Equipment loopback: similar to far-end loop but occurs in the SerDes block, by writing 0 × 9042 to reg.18G5Additional InformationFor any additional information or questions regarding the devices mentioned in this document, contactyour local sales representative.Microsemi HeadquartersOne Enterprise, Aliso Viejo,CA 92656 USAWithin the USA: +1 (800) 713-4113Outside the USA: +1 (949) 380-6100Sales: +1 (949) 380-6136Fax: +1 (949) 215-4996Email:***************************© Microsemi. All rights reserved. Microsemi and the Microsemi logo are trademarks of Microsemi Corporation. All other trademarks and service marks are the property of their respective owners.Microsemi makes no warranty, representation, or guarantee regarding the information contained herein or the suitability of its products and services for any particular purpose, nor does Microsemi assume any liability whatsoever arising out of the application or use of any product or circuit. The products sold hereunder and any other products sold by Microsemi have been subject to limited testing and should not be used in conjunction with mission-critical equipment or applications. Any performance specifications are believed to be reliable but are not verified, and Buyer must conduct and complete all performance and other testing of the products, alone and together with, or installed in, any end-products. Buyer shall not rely on any data and performance specifications or parameters provided by Microsemi. It is the Buyer's responsibility to independently determine suitability of any products and to test and verify the same. The information provided by Microsemi hereunder is provided "as is, where is" and with all faults, and the entire risk associated with such information is entirely with the Buyer. Microsemi does not grant, explicitly or implicitly, to any party any patent rights, licenses, or any other IP rights, whether with regard to such information itself or anything described by such information. Information provided in this document is proprietary to Microsemi, and Microsemi reserves the right to make any changes to the information in this document or to any products and services at any time without notice.Microsemi, a wholly owned subsidiary of Microchip Technology Inc. (Nasdaq: MCHP), offers a comprehensive portfolio of semiconductor and system solutions for aerospace & defense, communications, data center and industrial markets. Products include high-performance and radiation-hardened analog mixed-signal integrated circuits, FPGAs, SoCs and ASICs; power management products; timing and synchronization devices and precise time solutions, setting the world's standard for time; voice processing devices; RF solutions; discrete components; enterprise storage and communication solutions; security technologies and scalable anti-tamper products; Ethernet solutions; Power-over-Ethernet ICs and midspans; as well as custom design capabilities and services. Microsemi is headquartered in Aliso Viejo, California, and has approximately 4,800 employees globally. Learn more at www. .VPPD-03695。

供应商询比价竞价操作手册

（对于多标的操作取消勾选当价格修改自动计算总价）。
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山东临工工程机械有限公司
备注：报价截止之前可对报价和提交资料信息进行修改，操作方法和询比报价操作一致（点击“修改”完成询比报价的修改）。操作菜单：询比价项目询价单处理修改报价，通过点击“修改报价”查看自己的报价、备注，下载上传的附件，此处看到的也是采购单位在开标以后看到的情况
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登录系统后，就可以看到待处理工作界面。目前按实际业务分为：资质文
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件到期提示、业务通知提示、询价项目待办工作、竞价项目待办工作、中标公告。登录电子采购系统看到：待办工作、功能菜单
三、询比价项目 3.1 询比待办工作
询比价项目询价单处理修改报价通过点击修改报价查看自己的报价备注下载上传的附件此处看到的也是采购单位在开标以后看到的情况33导入询比数据进行报价操作多标的物报价可以通过导入的方式进行报价操作点击导入投标数据界面如下点击下载投标数据文件下载保存询比excel数据询比报价和磋商报价可使用同一表格在询比报价基础上进行修改上传进行磋商打开填写相应扩展信息和必填到价格信息后保存关闭excel表格点击浏览找到填写文件点击上传电子交易平台开始上传询比excel数据系统会提示导入成功或错误提示修改后再次上传
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一、系统概述：
电子采购系统是基于互联网建立的用于采购的工具，利用该系统实现网上的询比价、竞价的采购过程：供应商在线注册（供应商代码为登录用户名）、提交企业资料（企业资料修改参照《供应商注册帮助》），经山东临工采购本部的供应商管理人员审核确认，成为山东临工采购单位的合格供应商；采购人员在线发布询比、竞价等采购信息，符合条件的供应商可以查看标书、在线投标，采购单位在线议标、发布中标公告，该系统将山东临工的采购部门与供应商更有效的联系起来。希望供应商能够尽快学习操作手册，并熟悉该采购平台功能，便于以后的业务顺利开展。操作主流程请到最后一页进行打印查看。

NB2XXXA EMI TSOP6 EVB 通用评估板用户手册说明书

EMITSOP6EVBEMI TSOP6 EVB Universal Evaluation Board User's ManualBoard DescriptionThe EMI TSOP6 EVB universal Evaluation Board was designed to provide a flexible and convenient platform to quickly evaluate, characterize and verify the performance and operation of all twelve NB2XXXA EMI devices, and all of their possible configurations. This user’s manual provides detailed information on board contents, layout and its use. It should be used in conjunction with the appropriate NB2XXXA datasheet: (). See Table 1.Board Features•Accommodates the Electrical Characterization of the NB2XXXA, Reduced EMI Series in the TSOP −6 Package•Multiple Configurations − Refer to NB2XXXA Configurations Tables 1 and 2•26 W Series Termination Resistor Installed on MODOUT•15 pF Output Load Capacitor Installed on MODOUT •Selectable Jumpers for SELECT Pin Logic LevelsFigure 1. NB2XXXA TSOP −6 PinoutTwelve EMI products share the same TSOP −6 (TSOT −23−6)package, but have minor pin configuration differences. See Table 2.123654V SS (GND)MODOUT V DDIn or OutXOXI / CLKINFigure 2. Evaluation BoardEVAL BOARD USER’S MANUALTable 1. NB2XXX PIN FUNCTION (see datasheet)EMI Devicefin (MHz)XTAL CLKIN (External)PD SSON Mod Eqn Freq.REFOUT NB2579A13 − 30Y Y N Y f in÷ 640$1%N NB2669A 6 − 13N Y Y N f in÷ 256$1%N NB2760A 6 − 13Y Y Y N f in÷ 256$0.75%N NB2762A 6 − 13Y Y Y N f in÷ 256−1.25%N NB2769A 6 − 13Y Y Y N f in÷ 256$1%N NB2779A13 − 30Y Y Y N f in÷ 640$1%N NB2780A30 − 50Y Y Y N f in÷ 1280$0.75%N NB2869A 6 − 13Y Y N N f in÷ 256$1%Y NB2870A13 − 30Y Y N N f in÷640$0.75%Y NB2872A15 − 30Y Y N N f in÷ 640−1.25%Y NB2879A15 − 30Y Y N N f in÷ 640$1%Y NB2969A 6 − 13Y Y N N f in÷ 256$1%Y, REFOUT ÷2 Table 2. NB2XXX PIN ASSIGNMENT (see datasheet)EMI DevicePin 1Pin 2Pin 3Pin 4Pin 5Pin 6See Table 4 NB2579A I XO XI / CLKIN V DD MODOUT V SS (GND)R1 = 0 WNB2669A I NC CLKIN V DD MODOUT V SS (GND)R1 = 0 WNB2760A I XO XI / CLKIN V DD MODOUT V SS (GND)R1 = 0 WNB2762A I XO XI / CLKIN V DD MODOUT V SS (GND)R1 = 0 WNB2769A I XO XI / CLKIN V DD MODOUT V SS (GND)R1 = 0 WNB2779A I XO XI / CLKIN V DD MODOUT V SS (GND)R1 = 0 WNB2780A I XO XI / CLKIN V DD MODOUT V SS (GND)R1 = 0 WNB2869A O XO XI / CLKIN V DD MODOUT V SS (GND)R1 = 26 WNB2870A O XO XI / CLKIN V DD MODOUT V SS (GND)C1NB2872A O XO XI / CLKIN V DD MODOUT V SS (GND)C1NB2879A O XO XI / CLKIN V DD MODOUT V SS (GND)C1NB2969A O XO XI / CLKIN V DD MODOUT V SS (GND)C1LAB SETUP PROCEDURELab Setup and Measurement Procedure Equipment Used•Agilent Signal Generator #81110A (or Crystal)•Real −Time Oscilloscope, Frequency Counter or Spectrum Analyzer•Agilent #6624A DC Power Supply •Digital V oltmeterPower Supply ConnectionsThe NB2XXXA has a positive supply pin, V DD , and a negative supply pin, GND.Power supply “anvil” terminals are provided for V DD and GND. Use of “minigrabber” banana plug cables work well for connections to the power supply.Table 3. POWER SUPPLY CONFIGURATIONSDevice PinSingle Power SupplyV DD V DD = +3.3 V GNDGND = 0 V+3.3 VV DDFigure 3. Power Supply ConfigurationFigure 4. Input / Output ConfigurationIn or OutNB2XXXALab Test Set−up ProcedureTo monitor the MODOUT output on an oscilloscope, spectrum analyzer or frequency counter:1.Connect a power supply to the evaluation board.(see Figure 3)Connect V DD to +3.3 VConnect GND to 0 V2.Connect an external clock reference to the CLKINPin 3 or install a crystal and appropriate (seeCLKIN) crystal load capacitors to Pins 2 and 3.3.Connect the MODOUT output to the measurementinstrument.4.For the MODOUT output, the NB2XXXA boardprovides a series 26 W source termination resistorand a load capacitor pad for each output; 15 pF isinstalled.Board LayoutThe evaluation board is constructed with FR4 material and 50 W trace impedance, designed to minimize noise and crosstalk.Layer StackL1Signal (top)L2GroundL3V DD (positive power supply)L4Blank (bottom)Pin 1 − IN / OUT ConfigurationPin 1 of the EMI TSOP6 EVB universal evaluation board can be configured to serve as an input or output, depending on device.See Tables 1 and 2.An SMA connector is provided to access Pin 1.If Pin 1 is an input, a 0 W resistor may be used at R1.Table 4. PIN 1 INPUT/OUTPUTDevice Pin #1R1C1 (or C3)See Table 2Input0 W OpenSee Table 2Output26 W15 pF If Pin 1 is an output, C1 can be used to install an output load capacitor, ie. a 15 pF capacitor. C1 and C3 can be used to parallel two output load capacitors. Also, a 26 W series termination resistor should be installed at R1.When Pin 1 is an input, the select header pins, HI and LO, can manually control the Pin 1 logic level via the appropriate jumper/shunt. A connection from each header must then be made to the Pin 1 metal trace. When either HI or LO are jumpered, Pin 1 is forced to V DD (logic High) or GND (logic Low).MODOUT Output Series ResistorAn R2 resistor pad is provided to series terminate the MODOUT output and is installed with a 26 W resistor. This series resistor complements an internal 24 W resistor to match the 50 W trace impedance.MODOUT Output Load CapacitorAn output load capacitor pad is provided to load the MODOUT output and is installed with a 15 pF capacitor. C4 and C5 can be used to parallel two output load capacitors for various combinations of capacitive loads, if needed. CLKINAn SMA connector is provided for CLKIN if an external clock source is used on Pin 3. The metal trace at the crystal pad is intentionally open for crystal use, and must be shorted for a connection to Pin 3 for external clock use. The unused component pad labeled C6 (used for the crystal load capacitor) may be used for a 50 W resistor to ground to terminate a signal generator.NB2XXXA Output LoadingV DDFigure 5. Output Loading for Test / EvaluationSeries Termination ResistorClock output traces over one inch should use series termination. To series terminate a 50 W trace (a commonly used trace impedance), place a 26 W resistor in series with the clock line, as close to the clock output pin as possible.The nominal impedance of the clock output is 24 W .Figure 1. NB2XXXA Evaluation Board SchematicExternal Clock SourceTable 5. NB2XXXA EVALUATION BOARD BILL OF MATERIALSComponentDescriptionQty SMA 1 − 3Connector SMA Connector1−3C2Capacitor0.1 m F, 10%, KEMET, C0603C104K5RAC, Installed 1C6 − C7Capacitor (Crystal Load)27 pF, Not Installed 2C1, C3, C4,C5Capacitor 15 m F, C5 Installed 1−4Jumper Header 100 mil, Berg4Jumper2R1 − R2Resistor26 W or 0 W , R2 Installed with 26 W 2C6Resistor (optional)50 W , 0.1%, 0.25 W 1Power Supply ConnectorAnvil − Keystone #50162U1NB2XXXATSOP −6 device (Installed by User)1X1Crystal (See Crystal Chart)Fundamental Mode, Parallel Resonant, Ecliptek 1Pin Recepticle Through −Hole Crystal Connector 2CapacitorV DD to GND Bypass Capacitors10 m F − 22 m F 0.01 m F − 0.1 m F11Table 6.Crystal Frequency(MHz)Ecliptek Part #ESR (W MAX)6.000ECX−6074−6.000M125 8.000ECX−6075−8.000M70 10.000ECX−6078−10.000M5012.000ECX−6081−12.000M5013.500ECX−6082−13.500M5014.31818ECX−6083−14.31818M5015.000ECX−6084−15.000M5016.000ECX−6087−16.000M50 16.660ECX−6090−16.660M5018.750ECX−6125−18.750M5019.440ECX−6091−19.440M5019.531ECX−6126−19.531M5020.000ECX−6094−20.000M50 20.1416ECX−6127−20.1416M50 20.480ECX−6099−20.480M5024.000ECX−6102−24.000M4025.000ECX−6105−25.000M4026.5625ECX−6110−26.5625M4026.6000ECX−6128−26.6000M5027.000ECX−6115−27.000M4028.000ECX−6118−28.000M40 30.000ECX−6119−30.000M40 32.000ECX−6120−32.000M40Table 7.Crystal Parameter Specification Nominal Frequency See Chart Frequency Tolerance at 25°C/Stability over OTR±15 ppm / ±20 ppm Operating Temperature Range0°C to +70°CLoad Capacitance (C L)18 pFEquivalent Series Resistance(W) (Maximum)See ChartMode of Operation and CrystalCutAT−Cut Fundamental Storage Temperature−40°C to +85°CDrive Level100 m Watts Correlation1 mW Maximum Aging (at 25°C)±3 ppm / 1st year,±15 ppm / 10 yearMaximumInsulation Resistance500 M W Minimum,100 V Shunt Capacitance (pF(Maximum)5 pF Maximum Package E2S (HC−49/UP SMD)ADDITIONAL INFORMATIONTECHNICAL PUBLICATIONS :Technical Library: /design/resources/technical−documentation onsemi Website: ONLINE SUPPORT : /supportFor additional information, please contact your local Sales Representative at /support/sales。

Aeneas R2023T Evaluation Platform 说明书

Aeneas R2023T Evaluation Platform使用手册产品型号：R2023T手册版本：V1.00目录目录 (2)1 Aeneas R2023T Evaluation Platform概述 (3)1.1 平台简介 (3)1.2 平台清单 (3)1.3 平台技术指标 (4)1.3.1 GY7051A USB-I2C Adapter (4)1.3.2 R2023T Demo Board (4)1.4 Demo Board线路 (5)2 接口描述 (5)2.1 PIN 脚描述 (5)2.2 I/O的直流电气特性 (6)3 USB-I2C适配器硬件驱动安装 (6)4 I2C Tool 软件安装 (9)5 平台硬件操作说明 (10)5.1 平台器件连接 (10)5.2 Demo Board供电 (10)6 平台软件操作说明 (11)6.1 软件运行说明 (11)6.2 软件功能介绍 (11)6.2.1 软件参数描述 (11)6.2.2 软件按钮操作 (13)7 接口函数与用户二次开发 (13)8 USB-I2CAdapter工作原理 (14)8.1 I2C 操作过程简述 (14)8.2 接收数据（读操作） (14)8.3 发送数据（写操作） (15)9 R2023T 寄存器设置 (15)9.1时间计数器(0~2h) (16)9.2 周计数器(3h) (19)9.3 日期计数器(4-6h) (19)9.4 振荡调整寄存器(7h) (20)9.5 Alarm_W 寄存器(8-Ah) (20)9.6 Alarm_W 寄存器(B-Ch) (21)9.7 控制寄存器1(Eh) (22)9.8控制寄存器2(Fh) (23)10 附录 (23)1 Aeneas R2023T Evaluation Platform 概述1.1 平台简介该平台用于RICOH R2023T 实时时钟芯片的测试，R2023T 包括一个外围晶体振荡器、时钟日期计数器和2个中断预警电路，该平台可以测试RTC 所有功能及性能指标，比如时钟精度。

LM26001评估板用户指南说明书

User's GuideSNVA153B–May2006–Revised April2013AN-1454LM26001Evaluation Board1IntroductionThe LM26001evaluation board is designed to demonstrate the capabilities of the LM26001switchingregulator.The LM26001board,schematic shown in Figure1,is configured to provide an output of3.3V at up to1.5A from an input range of3.5V to38V(a minimum of4.5V is required for startup).The nominal operatingfrequency is305kHz and can be synchronized from+30%to-20%of nominal using the SYNC connection post.The evaluation board is designed to operate at ambient temperatures up to75°C.Typical evaluation board waveforms and performance curves are shown in Figure2through Figure7.Figure8and Figure9show the pcb trace layout.To aid in the design and evaluation of dc/dc buckconverters based on the LM26001regulator,the evaluation board can be re-configured for different output voltages and operating frequencies.Test points are also provided to enable easy connection andmonitoring of critical signals.Table2shows the Bill of Materials(BOM)for a second example circuit for1.5V output and480kHzswitching frequency.This design operates from an input voltage of3.5V to38V and enters pulse skipping mode at approximately24Vin,depending on loading.For more information about device function and circuit design,see the LM26001/LM26001Q1.5ASwitching Regulator with High Efficiency Sleep Mode Data Sheet(SNVS430).2Jumper SettingsThe FPWM jumper is used to disable the sleep mode function.For normal operation,select‘off’,which connects FPWM to GND.For FPWM operation(sleep mode disabled),select‘on’.The Vbias jumperconnects the VBIAS pin to Vout.When Vout is greater than3V,the VBIAS function will be activated for improved efficiency.To disable VBIAS,or if Vout is set to less than3V,set the jumper to‘GND’.3Optional ComponentsBefore changing the default components,see the device-specific data sheet for information regarding the component selection.Output voltage and frequency are easily adjustable with single resistors,R1and R3,respectively.However,large changes to the default settings may require other changes to the inductor,outputcapacitor,and compensation network.Several optional component pads have been provided for application flexibility.The C7pad is provided for an additional ceramic output capacitor.This capacitor can be used to lower the total ESR at the output.D2blocks reverse current to the input supply during low input voltage and light load conditions.This diode may not be necessary in all applications and can be replaced with a jumper.C10is a phase lead capacitor that can be installed to increase phase and gain margin.For more detailed information,see the compensation section of the device-specific data sheet.All trademarks are the property of their respective owners.1 SNVA153B–May2006–Revised April2013AN-1454LM26001Evaluation Board Submit Documentation FeedbackCopyright©2006–2013,Texas Instruments Incorporated** Component not installedPowering Up 4Powering UpBefore powering up the LM26001evaluation board,all external connections should be verified.The power supply input must be turned off and connected with proper polarity to the VIN and GND posts.The load should be connected between the VOUT post and GND post.Both the VIN and VOUT connections should use the GND post closest to the VIN post.Output voltage can be monitored with a DVM or oscilloscope at the VOUT post.The second GND post,close to the IC,is provided primarily for small signal measurements,such as soft-start voltage,or PGOOD.This GND post should also be used when applying optional external signals such as EN and SYNC.Once all connections have been verified,input power can be applied.The input voltage must be setbetween 4.5V and 38V.The load can be on or off at startup.If the EN post is left open,the output voltage will ramp up when VIN is appliedFigure 1.Evaluation Board Schematic2AN-1454LM26001Evaluation BoardSNVA153B–May 2006–Revised April 2013Submit Documentation FeedbackCopyright ©2006–2013,Texas Instruments Incorporated Powering Up Table1.LM26001Bill of Materials(BOM)for V=3.3V,1.5A,305kHzORef No Value Footprint SupplierC1 3.3µF50V X7R ceramic1210TDKC247µF50V low ESR electrolytic PanasonicC310µF10V B ceramic1206MurataC40.1µF50V COG ceramic1206MurataC510nF50V X7R ceramic0603MurataC6100µF8V12mohm SP PanasonicC7not installed1206-C8 4.7nF50V COG ceramic0603MurataC947pF50V COG ceramic0603MurataC10not installed0603-D160V3A NSQ03A06SMC NIECD260V2A EC21QS06SMA NIECL122µH3.5A SLF12565T-220M3R5TDKR156kΩ1%0603-R233kΩ1%0603-R3120kΩ1%0603-R4200kΩ5%0603-R515kΩ1%0603-R610kΩ5%0603-3 SNVA153B–May2006–Revised April2013AN-1454LM26001Evaluation Board Submit Documentation FeedbackCopyright©2006–2013,Texas Instruments Incorporated2 ms/DIVPerformance Characteristics 5Performance CharacteristicsUnless otherwise specified,VIN=12V,TA=25°C.Figure2.Start-Up Waveforms(IOUT=1A)Figure3.PWM Waveforms(IOUT=1A)OUTFigure5.Load Transient Response(IOUT=0.25A to1.5A step)4AN-1454LM26001Evaluation Board SNVA153B–May2006–Revised April2013Submit Documentation FeedbackCopyright©2006–2013,Texas Instruments Incorporated1101001k10kI OUT (mA)505560657075808590E F F I C I E N C Y (%)510152025303540V IN (V)020406080100120140160I O U T (m A)PCB Layout Diagram(s)Figure 6.Efficiency vs I OUTFigure 7.Sleep Mode Threshold Load Current vs Input(V BIAS =V OUT )Voltage6PCB Layout Diagram(s)Figure 8.Top Side Layout5SNVA153B–May 2006–Revised April 2013AN-1454LM26001Evaluation BoardSubmit Documentation FeedbackCopyright ©2006–2013,Texas Instruments IncorporatedPCB Layout Diagram(s)Figure9.Bottom Side Layout6AN-1454LM26001Evaluation Board SNVA153B–May2006–Revised April2013Submit Documentation FeedbackCopyright©2006–2013,Texas Instruments Incorporated PCB Layout Diagram(s) Table2.LM26001Bill of Materials(BOM)for V=1.5V,1.5A,480kHzORef No Value Footprint SupplierC1 3.3µF50V X7R ceramic1210TDKC247µF50V electrolytic PanasonicC310µF10V B ceramic1206MurataC40.1µF50V COG ceramic1206MurataC510nF50V X7R ceramic0603MurataC6100µF8V12mohm SP PanasonicC710µF6.3V X7R ceramic1206MurataC8 6.8nF16V COG ceramic0603MurataC968pF25V COG ceramic0603MurataC10not installed0603-D160V3A NSQ03A06SMC NIECD260V2A EC21QS06SMA NIECL1 3.3µH4.1A RLF7030T-3R3M4R1TDKR18.2kΩ1%0603-R239kΩ1%0603-R375kΩ1%0603-R4200kΩ5%0603-R520kΩ1%0603-R610kΩ5%0603-7 SNVA153B–May2006–Revised April2013AN-1454LM26001Evaluation Board Submit Documentation FeedbackCopyright©2006–2013,Texas Instruments IncorporatedIMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries(TI)reserve the right to make corrections,enhancements,improvements and other changes to its semiconductor products and services per JESD46,latest issue,and to discontinue any product or service per JESD48,latest issue.Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.All semiconductor products(also referred to herein as“components”)are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.TI warrants performance of its components to the specifications applicable at the time of sale,in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products.Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty.Except where mandated by applicable law,testing of all parameters of each component is not necessarily performed.TI assumes no liability for applications assistance or the design of Buyers’products.Buyers are responsible for their products and applications using TI components.To minimize the risks associated with Buyers’products and applications,Buyers should provide adequate design and operating safeguards.TI does not warrant or represent that any license,either express or implied,is granted under any patent right,copyright,mask work right,or other intellectual property right relating to any combination,machine,or process in which TI components or services are rmation published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement e of such information may require a license from a third party under the patents or other intellectual property of the third party,or a license from TI under the patents or other intellectual property of TI.Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties,conditions,limitations,and notices.TI is not responsible or liable for such altered rmation of third parties may be subject to additional restrictions.Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.Buyer acknowledges and agrees that it is solely responsible for compliance with all legal,regulatory and safety-related requirements concerning its products,and any use of TI components in its applications,notwithstanding any applications-related information or support that may be provided by TI.Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures,monitor failures and their consequences,lessen the likelihood of failures that might cause harm and take appropriate remedial actions.Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in safety-critical applications.In some cases,TI components may be promoted specifically to facilitate safety-related applications.With such components,TI’s goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements.Nonetheless,such components are subject to these terms.No TI components are authorized for use in FDA Class III(or similar life-critical medical equipment)unless authorized officers of the parties have executed a special agreement specifically governing such use.Only those TI components which TI has specifically designated as military grade or“enhanced plastic”are designed and intended for use in military/aerospace applications or environments.Buyer acknowledges and agrees that any military or aerospace use of TI components which have not been so designated is solely at the Buyer's risk,and that Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use.TI has specifically designated certain components as meeting ISO/TS16949requirements,mainly for automotive use.In any case of use of non-designated products,TI will not be responsible for any failure to meet ISO/TS16949.Products ApplicationsAudio /audio Automotive and Transportation /automotiveAmplifiers Communications and Telecom /communicationsData Converters Computers and Peripherals /computersDLP®Products Consumer Electronics /consumer-appsDSP Energy and Lighting /energyClocks and Timers /clocks Industrial /industrialInterface Medical /medicalLogic Security /securityPower Mgmt Space,Avionics and Defense /space-avionics-defense Microcontrollers Video and Imaging /videoRFID OMAP Applications Processors /omap TI E2E Community Wireless Connectivity /wirelessconnectivityMailing Address:Texas Instruments,Post Office Box655303,Dallas,Texas75265Copyright©2013,Texas Instruments Incorporated。

迪普产品配置文档-基础篇(2012-11-05)

配置了关键字过滤功能，但无法过滤？
• 在配置行为审计的前提下，添加关键字过滤参数

35
35
UAG审计及流控
问题与排查
旁路模式，当设备异常重启或断电后，为何网络产生风暴？
• 中高端的GA、GE、TS设备，前三对儿接口默认自带断电保护，如镜像连接设备0、 1接口，设备正常运行下，0、1口为旁路且独立，当设备异常断电后，会启动断掉保护机制，即0、1直通。建议使用不同接口对实现旁路，或SW上VLAN隔离
UAG 旁路部署模式
旁路部署方式非在线部署
Internet 路由器
镜像内部网络交换机
对镜像流量进行用户行为审计

25
25
UAG审计及流控
调研信息
组网模式：在线模式、旁路模式、网关模式 PFP断电保护主机：是否使用，使用接口插卡类型（电、光）开启安全策略：根据用户需求，如行为审计、流量分析、带宽限速等 UMC统一管理中心：是否安装
32
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UAG审计及流控
配置步骤（7）
创建其他安全策略修改管理员密码修改管理地址，需同步修改日志输出“源IP” 添加管理默认路由
修改SNMP参数修改日志保存时间（系统日志、业务日志、操作日志）以上策略是否开启根据需求而定，配置方法参考用户手册

上下行链路接口类型（光、电）及速率、双工状态部署链路数量中、高端UAG，自带前三对儿电口断电保护功能

26
26
UAG审计及流控
配置步骤（1）
确认组网模式
•
•
透明桥接模式下几乎支持UAG所有功能，流控、审计、限速、web认证等
桥地址切忌与其他接口网段冲突，包括带外管理口

AA系统指导手册20110505

AA系统指导手册系统版本：R1.0文档编号：CHI -NJBL-A3南京北路自动化系统有限责任公司文档修订记录内部使用文档内容简介《AA系统指导手册》填写主要内容简介。

本文档专供用户、本公司职员以及经本公司许可的人员使用，未经公司书面同意，任何单位或个人不得以任何方式复制、翻印、改编、摘编、转载、翻译、注释、整理、出版或传播手册的全部或部分内容。

南京北路自动化系统有限责任公司位于南京江宁经济技术开发区，是南京市高新技术企业，现有高级工程师、工程师及其他专业技术人员200余名。

是专业从事煤矿通信、自动化、信息化产品的研发、生产、销售及服务的高科技公司。

公司拥有ISO9001:2008质量管理体系认证，坚持“质量第一、持续改进、用户至上、至诚服务”的质量方针，得到了广大客户的信赖和支持。

目前公司产品覆盖全国10多个省、自治区，并在多个煤炭主产区设有售后服务机构。

公司以满足客户需求为己任，不断生产高性价比的产品，为客户创造价值。

南京北路自动化系统有限责任公司联系地址：南京市江宁开发区菲尼克斯路99号邮政编码：211106电话号码：(025)52187543传真：(025)52185703邮件地址：njbestway@客户服务电话：400-611-5166客户支持网站：目录1概述 (1)2详细的指导 (1)2.1一级标题 (1)2.2二级标题 (1)2.2.1 三级标题 (1)2.3列表项目符号和列表编号 (2)2.4正文和图表 (2)2.5图范例 (3)2.6表范例 (4)3附录 (5)4参考资料 (5)插图目录图2-1 PHS系统的结构 (3)图2-2 洛阳各网关接通率对比图 (3)图2-3 边框设置示意图 (4)图2-4 宽度大小设置示意图 (4)列表目录表2-1 界面组件说明 (4)1概述本部分描述所要阐述的内容的总体介绍。

客户评价系统评价器使用手册(单独评)

第一章系统登录1．1 运行客户端程序运行“客户评价综合管理系统”光盘，双击运行EVMS.Client.exe客户端程序，显示如图所示登录界面：1．2 服务器连接设置单击按钮，显示如下设置窗口。

数据服务器IP：数据接收、处理、分析、统计服务程序所在机器IP地址。

数据服务器端口：客户端与服务程序通信端口。

升级服务器IP：客户端更新版本所访问的机器地址。

显视方案：客户端提供三种外观显示方案绿色、黄色、蓝色。

1．3 登录在上面的登录页面输入正确的用户名和密码,初始登入账号为：admin密码：admin 单击按钮。

登录成功后系统的初始窗口如下所示：第二章系统菜单栏操作说明2.1概述本章介绍的是系统菜单栏的操作说明，在以后章节此部分将不作详细说明。

系统的公有部分主要包括三大部分：功能选择菜单机构选择树查询工具栏2.2业务查询功能选择主菜单①②③④⑤⑥⑦⑧⑨⑩○11【说明】①机构选择：选择要查看的机构，弹出如图所示窗口。

○A○b○c○A模糊搜索：用户访问机构树的快速方式。

在文本输入区输入机构的名称首字母，系统会自动搜索符合条件的机构。

在文本输入区输入机构的汉字名称，系统会自动搜索符合条件的机构。

在文本输入区输入机构的编号，系统会自动搜索符合条件的机构。

○b纵向滚动条，如果树太高，无法显示全部时会出现。

拖动可查看全部机构树。

○c点击机构名，表示当前选中了此机构。

②员工选择：选择要统计的员工，弹出如图所示窗口。

○A○b○c○A模糊搜索：用户访问员工列表的快速方式。

在文本输入区输入员工的名称首字母，系统会自动搜索符合条件的员工。

在文本输入区输入员工的汉字名称，系统会自动搜索符合条件的员工。

在文本输入区输入员工的编号，系统会自动搜索符合条件的员工。

○b纵向滚动条，如果列表太长，无法显示全部时会出现。

拖动可查看全部员工列表。

○c点击员工名，表示当前选中了此员工。

③业务选择：选择要统计的业务，弹出如图所示窗口。

○A○b○c○A模糊搜索：用户访问业务列表的快速方式。

混凝土供应商管理平台操作手册报价管理操作流程V

供应商管理平台_报价管理操作手册
目录
1文档内容简介
本操作手册主要是供应商管理平台_报价管理所涉及的系统操作。

主要包括：
-创建报价信息；
-；
2版本控制
3系统操作说明
登陆路径：
每个供应商在中联都有个对应的代码为用户名，输入密码即可看的以下屏幕：
3.1创建报价信息
3.1.2系统操作步骤
1）点击“报价管理”，再点击“创建报价信息”即可弹出以下界面（图），将会显示填写物料的信息，包括物料编码、名称、材质、产品毛重报价、净重报价材料单报价、运费报价等；点击【更多】按钮，可以一次添加多个物料的报价，填写完所有信息，点击【保存】按钮，保存所填信息。

2）图点击“报价管理”，再点击“我的物料报价”即可弹出以下界面（图），显示所报所有物料的报价信息，选择下拉框，选择‘全部’、‘已核’‘未核’，进行物料的筛选。

图图。

资产评估项目管理系统使用说明书 .doc

谢谢你的观赏资产评估项目管理系统使用说明书国家知识产权局State Intellectual Property Office of the Republic of China中国资产评估协会CHINA Appraisal Society中电亿商网络技术有限责任公司&Gnet实验室CEBP Network Technology Co.,Ltd & Gnet Research laboratory Copyright：2009─2012目录一、系统简介4二、系统模块图5三、安装应用软件53.1.运行网络桌面53.2.安装应用软件6四、系统界面架构74.1功能菜单74.2快速启动栏 74.3任务列表74.4新闻列表84.5项目信息8五、快速入门85.1.系统设置85.1.1基本信息设置85.1.2评估程序设置95.1.3复核设置105.1.4项目状态设置105.1.5计划设置115.1.6模版设置125.1.7公告设置145.1.8客户信息设置145.1.9组织结构165.1.9.1组织结构 165.1.9.1.1更新部门165.1.9.1.2更新人员165.1.9.1.3新建部门175.1.9.1.4删除部门175.1.9.1.5新建人员175.1.9.1.6清除用户195.1.9.1.7部门信息修改195.1.9.1.8人员信息修改195.1.9.1.9部门转换195.1.9.2用户权限 205.1.9.3用户审批 215.2项目管理225.2.1我的项目225.2.1.1新建项目245.2.1.2修改项目245.2.1.3删除项目255.2.1.4项目权限分配265.2.1.5项目状态275.2.2归档项目295.2.3.项目查询统计295.2.4任务分配295.2.5人员动态305.3常用工具315.3.1无形资产评估查询315.3.2日程管理325.3.3日程统计335.3.4个人日程查询335.3.5快速查询345.3.6常用网址34六、软硬件环境需求34一、系统简介《资产评估项目管理系统》是在Gnet技术框架体系下采用Gnet的核心技术――Gnet网络套件技术，以C/S网络结构，在保持原有系统功能的基础上，可承受随时的需求变化，并集成多种应用和定制高度灵活的功能，完全可与同体系下的不同专业应用系统无缝连接，可以自上而下的统一、标准、安全、快速的布置并自动完成更新和升级。

G-SRM统谈分签供应商操作指引

在投标截止后，将结果公示至门户后，可以在‘投标明细’查看入围淘汰状况
8.供应商进行跟标
在最后一轮报价后，计算出中标供方，供应商进行跟标确认。
9.招标结果查看
招标结果公示后，供应商可以到招标结果页面查看招标结果。（结果公示后，供应商会收到邮件通知）
Thank you!
22
5.3供应商回复不参与原因
如果供应商不参与，请回复不参与原因
6.1供应商对投标/招标单进行报价
如果开始投标阶段，点击‘创建投标’今天投标(每轮投标前，都能收到投标通知邮件)
6.2供应商进行报价
开始对有报价权限的物料进行报价，点击确认进行报价确认
G-SRM
14
6.3供应商报价成功
成功报价
G-SRM
51供应商回复参与招标议价如果供应商确认参不点击回复是否参不进行回复52供应商上传相关附件如果供应商确认参不必须上传相关附件进行提交53供应商回复不参与原因如果供应商丌参不请回复丌参不原因61供应商对投标招标单进行报价如果开始投标阶段点击创建投标今天投标每轮投标前都能收到投标通知邮件gsrm1462供应商进行报价开始对有报价权限的物料进行报价点击确认进行报价确认gsrm1563供应商报价成功成功报价gsrm1664供应商点击项目标号查看投标信息点击项目标号可以报价单进行查看gsrm1765供应商查看投标明细信息查看报价单gsrm1866如果供应商对报价不满意可以撤回投标如果对本轮次报价丌满意可以点撤回最近投标进行撤回7
2.进入登录信息输入页面
供应录成功后，进入原有供应商门户，如需进行招投标，请点击‘集采招标/议价’，进入‘招投标’界面（如果没有反应，请将浏览器弹出阻止设置为允许，参考后面
浏览器设置-谷歌
登录GSRM系统（截图以UAT 系统为例）后，设置允许弹出式窗口

国家发展改革委评估机构管理系统用户使用手册

国家开展改革委评估机构治理系统操作指南中国工程咨询协会2009-4-8一、系统介绍〔一〕系统功能简介国家开展改革委评估机构治理系统?〔以下简称评估治理系统〕，能够辅助国家开展改革委评估机构用户〔以下简称用户〕完成资格申请电子文件的评估工作，并可通过系统对上报信息进程、内容进行审查，操作简便。

请用户认真阅读使用手册。

〔二〕运行环境1、硬件环境Cpu：P4 1.5G内存：256M硬盘空间：10G2、软件环境操作系统：WindowsXP、Windows2003扫瞄器版本：IEV6.0SP2以上扫瞄器版本OFFICE编辑系统：MicroSoftOffice2003以上版本屏幕分辨率：1024*768〔三〕打印功能的要求为用户能够使用业务治理系统中的打印功能，需要将业务治理系统的效劳器对应的网站地址添加到IE的受信任站点中。

具体设置步骤详见注重事项中的打印控件设置。

〔四〕系统讲明评估材料只采纳在线填报方式。

二、评估系统申报的步骤(一)登录系统1.访咨询中国工程咨询网，在左上角?托付投资咨询评估?中点击?国家开展改革委评估机构治理系统?链接后进进治理系统，或在扫瞄器地址栏内录进(://203.207.195.67:8088/login.jsp)。

2.输进用户名，密码〔使用登陆?中国工程咨询业务治理系统?时单位设定的用户名、密码〕，点击按钮，登录系统。

当输进用户名和密码后，要是在中点选对勾，系统会自动保持该用户登录密码，用户在该客户端再次登录系统时，密码将会自动经历，无须每次都重新输进。

点击往除所填写的内容以重新输进。

要是用户遗忘密码，能够点击评估治理系统登录页面上的按钮，系统进进猎取遗忘密码功能页面假设出现遗忘用户名和无法寻回密码的情况，可任选一种以下的解决方式。

1、与初审单位联系，由初审单位确认后与软件公司联系取得用户名密码。

2、复印法人证书副本，联系人身份证，并写下联系方式，发到************。

核价系统操作手册供应商

料费分离核价系统系统使用说明书内部用户二00九年九月三十日目录1系统配置..........................................................系统登录前的配置要求...........................................硬件配置...................................................系统软件...................................................网络配置...................................................登录....................................................... 2料费分离..........................................................查看项目列表...................................................查看流程 ......................................................填写明细 ......................................................提交流程 ......................................................查看发布邮件................................................... 3非料费分离........................................................查看项目列表...................................................查看流程 ......................................................填写报价 ......................................................提交流程 ......................................................查看发布邮件................................................... 4料费分离查询...................................................... 3核价查询.......................................................... 1系统配置1.1系统登录前的配置要求1.1.1硬件配置CPU：Pentium（奔腾）300MHz以上内存：512M以上显示器：14寸以上彩显，屏幕分辨率 1024*768以上1.1.2系统软件操作系统：Windows xpIE（Internet Explorer）版本：或、建议不要使用版本（IE版本查询：打开IE－>帮助－>关于Internet Explorer－>版本）1.1.3网络配置建议使用ADSL（俗称宽带网）或VPN连接互联网1.1.4登录2料费分离2.1查看项目列表目的：查询料费分离项目。

DIR9001评估板用户指引

1.2.9 外部时钟输入外部时钟可以通过移除已焊接的 XTAL 而连接在 CN002（未焊接）上。允许用户通过其他时钟源确认 DIR9001 的操作。
4 DIR9001评估板
SLAU225-2007年7月提交文档反馈
2 电路图、印刷电路板和材料清单
电路图、印刷电路板和材料清单
本节介绍 DEM-DIR9001 印刷电路板、DEM-DIR9001 电路图和材料清单
SLAU225-2007年7月提交文档反馈
DIR9001评估板
1
描述
1.1 电路方框图
光纤输入同轴输入
功能控制时钟控制
状态指示器
复位
1.2 操作和设置
图 1 – DEM-DIR9001 电路方框图
1.2.1 电源输入 +5V 电源输入在 CN051 处连接+5V 电源，在 HDR051 连接器处连接 5V 跳线。对于所有的内部操作，+3.3V 电源通过板上的 REG-IC 产生。不需要外部+3.3V。 +3.3 V 电源输入在 CN052 处连接+3.3V 电源，在 HDR051 连接器处连接 3.3V 跳线。所有的+3.3V 通过 CN052 提供。
表 2.SW002：PSCK0、PSCK1 系统时钟频率选择
PSCK[1:0]设置
PSCK1
PSCK0
SCKO
L
L
128fs
L
H
256fs
H
L
384fs
H
H
512fs
PLL 源输出时钟 BCKO 64fs 64fs 64fs 64fs
LRCKO fs fs fs fs
1.2.5 操作模式控制 SW004 是 DIR9001 的基本操作模式控制。

{分销管理}竞价平台系统核心分销商使用手册

{分销管理}竞价平台系统核心分销商使用手册竞价平台系统核心分销商使用手册2008-1-3目录1引言41．1编写目的41.1.1目的41.1.2预期读者41.1.3背景41.1.4定义51.1.5系统特点52用途52.1功能52.2.1精度72.2.2时间特性72.2.3灵活性73运行环境83.1硬设备83.2支持软件84操作流程84．1创建帐户84.1.1帐户查看84．2创建员工帐号124.2.1员工管理124.3政策公告发布164.3.1公告查看164.3.2政策管理204.3.3政策审核234.4买入管理244.4.1查询预订244.4.2为我的订单付款284.4.3为我公司的订单付款324.4.4我的退改签订单324.4.5根据PNR号生成订单344.4.6根据PNR内容354.4.7政策查看354.5出票管理364.5.1待出票订单364.5.2退改签订单374.6收付款管理394.6.1买入已付款订单394.6.2卖出待退款订单414.6.3收付款明细424.6.4买入报表434.6.5卖出报表444.6.6业务提成444.6.7买卖报表454.6.8买入分析464.6.9卖出分析474.6.10一周卖出分析48 4.7订单查询494.8常旅客管理524.8.1查询常旅客524.8.2添加常旅客524.8.3修改常旅客534.8.4删除常旅客545、系统设置565.1.1员工管理565.1.2单位信息维护595.1.3密码修改596、常见问题601引言欢迎您使用竞价平台系统，它是由成都佰特科技公司推出的基于WEB的测试管理工具，无论是通过Internet还是通过Customer你都可以以基于Web的方式来访问竞价平台系统。

机票订单流程是非常复杂的，它需要各大航空公司和数千个代理商。

通常情况下，机票预订管理需要多样式的硬件平台、多重的配置（计算机，操作系统，浏览器）和多种的应用程序版本。