LATTICE timing_closure_notes

Timing Closure Notes for FAE Training - 11/1/2011
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Lattice Semiconductor Confidential
AGENDA
Recap of What‟s Working in Closing Timing for Large Device Timing Preference Affected Timing Updated Tips and Tricks Introduction to FPGA Design Guide Q/A
0.420ns SLICE_54.Q0 to SLICE_87.C0 c1_30
Timing Closure Notes for FAE Training - 11/1/2011
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Lattice Semiconductor Confidential
CLOCK DOMAIN TRANSFER
Timing Closure Notes
Robert Xu
Oct. 2011
AGENDA
Recap of What‟s Working in Closing Timing for Large Device Timing Preference Affected Timing Updated Tips and Tricks Introduction to FPGA Design Guide Q/A
• Clocks/DSPs/DDR/PCS/PLL/DLL/Flops/Slices STOP and think when
– Post map slice utilization by default > 80-85% – Clock in the design exceeding the number of primary clock available. – Block RAM/DSP blocks are exceeding 80%.
Timing Closure Notes for FAE Training - 11/1/2011
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Lattice Semiconductor Confidential
GOOD ESTIMATE OF THE TIMING PICTURE
Synthesis/Map
– Go through synthesis timing report (*.srr) and post map trce report *.tw1 file, to make sure that the synthesis/map tools yields reasonable Logic levels. – Explore the synthesis/map options to see if better results can be achieved. – Check in the tw1 file about preference coverage
CONSTRAINTS COVERAGE
Constraint Coverage Report: Timing summary (Setup) Timing errors: 0 Score: 0 Cumulative negative slack: 0
Constraints cover 3172 paths, 3 nets, and 622 connections (99.8% coverage)
– Can I block a failing path?
• Asynchronous Path (Reset, etc.)
– Can I multicycle a path?
• Are the two clocks related? • Does combinatorial data need to be ready in 1 clock? Cross Domain
STOP and Think When
– tw1 file does meet all the timing.
– Use tw1 pass timing as “necessary but not sufficient condition” – Many steps can be done using TW1 • Unconstrained path • Clock Domain Transfer • Constraints coverage
Timing Closure Notes for FAE Training - 11/1/2011
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Lattice Semiconductor Confidential
GOOD ESTIMATE OF THE RESOURCE UTILIZATION
Synthesis/Map
– Go through *.srr and *.mrp file first, make sure that proper resources are allocated or inferred. – Compare the *.mrp resource utilization with the targeted device, check if the resource usage are balanced
The design is routable but did not achieve timing
The design is not routable
•
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If Routed, use timing tricks
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Timing Closure Notes for FAE Training - 11/1/2011
– Pay attention to every preferences
– Check constraints coverage – If too many timing path errors and the timing score is high, go back to RTL.
Something else to Check Outside of *.twr
1. 2. 3. RTL Software Tools/Silicon The Good Correlation or “Conditioning” of the RTL to Better Fit Vendor‟s Software and Silicon
Most designers concentrate on RTL, prefer a push button flow Some designers are less comfortable dealing with the RTL for timing Some designers are against #3 for code portability For timing closure for Lattice‟s low cost FPGAs, # 3 is crucial and most effective Software algorithm Issues are real Issues, more often “Heuristic” usually takes long time to tune and resolve. Spend more time on #3 is also a practical approach for AE/FAE. •
Timing Closure Notes for FAE Training - 11/1/2011
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Lattice Semiconductor Confidential
DOING THINGS RIGHT BEFORE GOING INTO PAR
Until now, if you still don‟t have good timing picture, consider the following:
Timing Closure Notes for FAE Training - 11/1/2011 Page: 4 Lattice Semiconductor Confidential
JUDGEMENT ON THE PROBLEM
The design is routable and achieved timing
Fix your RTL
Pipeline Whenever Possible Change arithmetic calculation from serial to parallel Optimize the state machine Trade/off between distributed memory/Block Memory Trade/off between DSP block/Carry-Chain More registering/pipelining opportunity. Check again using *.tw1
– Cross domain constraints – Cross domain analysis
Timing Closure Notes for FAE Training - 11/1/2011
Timing Closure Notes for FAE Training - 11/1/2011
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Lattice Semiconductor Confidential
REVIEW OF THE TIMING CONSTRAINTS
Read Trace Report *.twr1/twr File
To Check Unconstraint Path:
To Check Unconstraint Path: select check unconstrained path and full name Blocked path is considered as unconstrained