集成电路设计-07-时序逻辑设计

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Characterizing Timing
tD D Q D
Q
Q
Clk
Clk
tC -
Q
tC -
Q
Register
Latch
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约束（System Timing Constraints）
Inputs Combinational Logic Outputs
集成电路设计
第七章 时序逻辑电路设计
Designing Sequential Logic Circuits
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纲要


基本概念 组合逻辑与时序逻辑电路 有限状态机（FSM） Latch versus Register 锁存器 寄存器 动态锁存器/寄存器 时钟控制寄存器C2MOS 流水线 非双稳态时序电路 时序问题
Logic
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时间定义（Timing Definitions ）
CLK
t
t su D t hold
Register D Q
DATA STABLE t c- q DATA STABLE
CLK
t
Q
t

tsu Setup 建起时间——时钟翻转之前数据必须有效的时间； thold 维持时间——时钟触发之后数据仍然有效的时间； tc-q 传播延迟时间——CLK到Q
Current State T (clock period) clock
Next State
约束1： 最小时钟周期：T tc-q + tplogic + tsu
一个CLK周期必须容纳任何一级电路的最大延迟时间 tplogic
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约束2

寄存器维持时间：thold tcd-register + tcd-logic thold tcd-register 寄存器最小传播延迟 tcd-logic逻辑电路最小传播延迟

Dynamic storage


store state on parasitic capacitors only hold state for short periods of time (milliseconds) require periodic refresh usually simpler, so higher speed and lower power
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Latches vs Flipflops

Latches


level sensitive circuit that passes inputs to Q when the clock is high (or low) - transparent mode input sampled on the falling edge of the clock is held stable when clock is low (or high) - hold mode edge sensitive circuits that sample the inputs on a clock transition positive edge-triggered: 0 1 negative edge-triggered: 1 0 built using latches (e.g., master-slave flipflops)
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Positive Feedback: Bi-Stability
cascaded inverters
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VTC
V o1
1 o V
Vi2
1 o V 5 2 i V
V o2
V i1
A
V i2 = V o1 1
If the gain in the transient region is l stable operation points. C is a meta-stable operation point.
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多路开关型锁存器 （Mux-Based Latches）
Negative latch (transparent when CLK= 0) Positive latch (transparent when CLK= 1)
Vi1
Vi2

改变输出


cutting the feedback loop (mux based latch) overpowering the feedback loop (as used in SRAMs)
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Writing into a Static Latch
o V 5 2 i V
C
B V i1 = V o2
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Meta-Stability
= =
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Gain should be larger than 1 in the transition region
=
=
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Bistable Circuits （flip-flops）
Use the clock as a decoupling signal, that distinguishes between the transparent and opaque states
CLK
CLK
Q CLK
D CLK
弱输出
D
D
CLK
Converting into a MUX
Forcing the state (can implement as NMOS-only)
Mealy versus Moore state machines

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Moore machine
FF—Flip-Flop
X
y
Combinational Logic
Y
FF CLK
Z
output depends only on the current state Z = f (y)
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Static vs Dynamic Storage

Static storage


preserve state as long as the power is on have positive feedback (regeneration) with an internal connection between the output and the input useful when updates are infrequent (clock gating)
potential implementation advantages in speed and size； initial state
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Mealy machine
X Combinational Circuits y FF Y Z
CLK
both the input and the current state is used to determine the output Z = f (x, y) Y = f (x, y)
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Finite State Machine （FSM)
Inputs
Combinational Logic
Q D
Outputs
Current State
Next State
clock
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External inputs and states as the inputs Outputs，and Next state Clock，edge sensitive（positive or negative）
类型
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Latch-Based Design— for sequential
• P latch is transparent when f = 1
f
• N latch is transparent when f = 0
P Latch
Logic
N Latch
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——Sequential Logic

Sequential Logic

Asynchronous Circuits Synchronous Circuits
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Due to the time delay problems (races, hazards, … etc.) people rarely design sequential circuits in asynchronous approach. Synchronous circuits need a system clock to strobe the whole system. It is easier to control the inputs and states. The speed may be slower in the synchronous circuits.