高速POF收发器A High-Speed POF Receiver with 1 mm Integrated Photodiode

A High-Speed POF Receiver with1mm Integrated Photodiodein180nm CMOSFilip T avernier(1),Michiel Steyaert(1)(1)Katholieke Universiteit Leuven,ESA T-MICAS,Kasteelpark Arenberg10,3001Heverlee,Belgium, Bfilip.tavernier@esat.kuleuven.beAbstract The design and measurement of an optical receiver is presented.To minimize cost,it is com-pletely integrated on silicon in a CMOS process.In spite of the large parasitic photodiode capacitance, transient measurements are shown up to800Mbit/s.IntroductionNowadays,a growing interest in low-cost opti-cal communication systems for consumer appli-cations can be noticed.Plastic opticalfibers (POF)are preferred in this market because the fiber,associated connectors and installation are all inexpensive compared to a solution with glass fiber.This is due to the large core diameter of POF which is typically1mm.T o collect all light, the photodiode should have a light sensitive area which is at least as large as the cross section of POF.T ypically,an external photodiode is used because it can have a large area while showing only a low parasitic capacitance due to a dedi-cated processing1.Cost and size can however be reduced while the reliability is increased by implementing the photodiode on the same sub-strate as the analog front-end.For an application where a multi-mode glassfiber is used,a photodi-ode of0.06mm has been integrated together with the receiver circuitry in130nm CMOS2.Afirst step towards a POF-compliant integrated optical receiver has been realized in a600nm BiCMOS process3.The diameter of the integrated photo-diode is0.5mm which is still not large enough to collect all light leaving a1mm POF.To re-duce the parasitic photodiode capacitance,pro-cess modifications have been applied.The re-ported bitrate is300Mbit/s.The receiver that is presented in this paper is,to the author’s knowl-edge,thefirst one to integrate a photodiode with a diameter of1mm together with the analog front-end in a nanometer-scale CMOS process without any process modification.It can operate up to a bitrate of600Mbit/s at a supply voltage of only 1.124V with an according low power consump-tion of39.34mW.This is more than2times faster than the current state-of-the-art POF-compliant optical receivers with integrated photodiode3.If the supply voltage is increased to1.424V,the re-ceiver can even be operated up to800Mbit/s. TopologyThe circuit diagram of the presented optical re-ceiver is shown in Fig.1.Modulated light im-pinges on the integrated photodiode which con-verts the light power to an electrical current.The circuit equivalent of this photodiode is a current source,which is modulated by the light,in paral-lel with the parasitic photodiode capacitance.The current of the photodiode is amplified and con-verted to a voltage by the transimpedance ampli-fier(TIA).The DC-component of the photocurrent is compensated by means of a dedicated feed-back loop.This loop is needed to guarantee a correct biasing of all transistors for every optical input power level.For light with a wavelength of660nm,a typical wavelength to be used with POF,the optical bandwidth of a silicon integrated photodiode is not higher than70MHz4.Therefore an adaptive equalizer is added to the presented analog front-end.In this way,the maximum at-tainable bitrate is increased significantly.DesignThe integrated photodiode has a diameter of 1mm.Due to the huge corresponding area of the junction and the relatively high doping concentra-tions of the used180nm CMOS process,the par-asitic photodiode capacitance C d is64pF.A high reverse voltage over the junction could lower this value but in order not to decrease the reliability, the choice is made to limit the reverse voltage to 1.8V,the nominal supply voltage of the pared to a photodiode with a diameter of0.5mm3,the area is4times larger in this de-sign whereas the capacitance is almost30times higher.The measured responsivity is0.21A/W for a wavelength of660nm.In order to combine a high transimpedance gain (Z T IA)and a high bandwidth(BW T IA)with such an immense capacitance at the input,the gain of the voltage amplifier within the TIA(A v)should be as high as possible.This can be concluded from the following equations:Z T IA=R fBW T IA=A v2πR f C dECOC 2010, 19-23 September, 2010, Torino, Italy978-1-4244-8535-2/10/$26.00 ©2010 IEEEP2.04Fig.1:Schematic of the proposed POF receiver existing from a photodiode,a TIA with DC-current compensation and an equalizer.As shown in Fig.1,the voltage amplification is realized by means of three amplification stages. Thefirst stage is a push-pull stage to maximize the gain and to reduce the input referred noise of the other stages.The drawback of such a topol-ogy is its high input pared to a common-source amplifier the gain is twice as high whereas the input capacitance is almost4 times higher.However,for thefirst stage this is not really a problem as the input capacitance is completely dominated by the photodiode capaci-tance of64pF.The second and the third stage are common-source amplifiers with an active load. To guarantee an optimal biasing of these active loads,their gate voltages are generated internally by means of low-passfilters as shown in Fig.1. An inverting voltage amplification is realized at the output of the third stage.The feedback network is composed by an nMOS and a pMOS transistor in parallel.They are operated in their linear region where they act as a resistor with an equivalent resistance of R f.Thefirst advantage of this feed-back network is the possibility to alter the resis-tance by changing the gate voltage.The second advantage is the small physical size and accord-ing low parasitic capacitance to the substrate for a large resistance.This parasitic capacitance is typically a problem when using a polysilicon re-sistor as feedback network5.Both an nMOS and a pMOS are used to obtain a symmetrical sig-nal swing for large input signals or when the tran-simpedance gain is set high.A seperate path for the DC-current of the pho-todiode is provided in order not to disturb the cor-rect biasing of the transistors,especially of those in the last amplification stage.For frequencies below the cut-off frequency of the low-passfil-ter(R DC,C DC,n,C DC,p),the transconductance of M DC,n and M DC,p appears in parallel with the normal feedback path:Z T IA,DC=R f//1g m,MDC,n+g m,MDC,pThe transimpedance gain is therefore significantly lower at DC than it is in the frequency band of interest,namely above the cut-off frequency of the low-passfilter.The voltage buffer(M V B,n, M V B,p)is added to make the amplification be-tween the drain and gate of M DC,n and M DC,p non-inverting which is necessary for a correct op-eration of this feedback loop.The equalizer extends the relatively low band-width of the photodiode.Instead of making use of frequency dependent source degeneration2,it is implemented here by means of a common-source amplifier with three active inductors in parallel as load.The roll-up frequency characteristic of the gain of the equalizer is adjusted to match the roll-off frequency behaviour of the photodiode so aflat combined frequency response is obtained.As can be seen in Fig.1,the circuit is com-pletely self-biased which means that no external voltages or currents are needed,except for the supply voltage.For a supply voltage of1.124V, all transistors are biased in weak inversion.This minimizes the power consumption2.To be able to operate at a higher bitrate,the supply voltage can be increased to1.424V.The transistors are then biased in strong inversion.Measurement ResultsThe complete receiver is integrated in180nm standard CMOS.The chip photograph is shown in Fig.2.The power consumption is only39.34mW at a supply voltage of1.124V.The die size is 2.4x1.5mm2.Fig.2:Chip photograph of the presented optical re-ceiver.The transient behaviour of the receiver is veri-fied with an optical input signal.This light with a wavelength of 660nm is generated by a commer-cially available gigabit POF tranceiver.A pseudo-random bit sequence (PRBS)with a length of 27−1is used as data pattern whereas a POF with a core diameter of 1mm is applied to guide the light towards the integrated photodiode.A mea-sured eye diagram of the output of the receiver at 400Mbit/s is shown in Fig.3.The measured peak-to-peak jitter,normalized to the bit interval,is represented in Fig.4.It can be noticed that the higher the bitrate is,the larger the portion of jitter in the total bit interval becomes.Moreover,this portion varies with the amount of optical input power.As can be seen in Fig.4,the peak per-formance of the presented receiver is between -14dBm and -10dBm optical input power as in that region the jitter is the smallest.The receiver is also measured at a supply volt-age of 1.424V .The results of this are summarized in Fig.4.It can be noticed that the jitter at a cer-tain bitrate and input power is lower than at a sup-ply voltage of 1.124V .Moreover,measurements are shown up to 800Mbit/s with a peak-to-peak jitter lower than half the bitperiod.Fig.3:Measured eye diagram at a bitrate of 400Mbit/s for -13.6dBm optical inputpower.Fig.4:Contour plot of the measured peak-to-peak jit-ter,normalized to the respective bit interval,for a sup-ply voltage of 1.124V.Fig.5:Contour plot of the measured peak-to-peak jit-ter,normalized to the respective bit interval,for a sup-ply voltage of 1.424V .ConclusionA POF-compliant optical receiver with 1mm inte-grated photodiode in 180nm CMOS is presented.The achieved bitrate is 600Mbit/s at a supply volt-age of 1.124V and a power consumption of only 39.34mW.This bitrate is about 2times higher than the current state-of-the art POF-compliant optical receivers with integrated photodiode.If the supply voltage is increased to 1.424V ,the bitrate can be increased to 800Mbit/s.References 1K.Schr¨odinger et al.,IEEE Journal of Solid-State Circuits,37,874(2002).2F .Tavernier et al.,IEEE Journal of Solid-State Circuits,44,2856(2009).3M.Fortsch et al.,IEEE Sensors Journal,6,385(2006).4S.Radovanovic et al.,Proc.EDSSC’03,T3.6(2003).5J.Knorr et al.,IEEE Transactions on Circuits and Systems I,50,1192(2003).。