FPGA可编程逻辑器件芯片XC2V80-5FG456C中文规格书

Chapter 1:Configuration Overviewwidth. Table1-5 shows an example bitstream with an inserted bus width detection pattern.When observing the pattern on the FPGA data pin, the bits are bit swapped, as describedin “Parallel Bus Bit Order.”The bitstream data in Table1-5 shows the 32-bit configuration word for an unswappedbitstream. For a swapped bitstream format, the LSB and MSB order for the individual bytesare swapped. For example, the Sync word at the FPGA pins in the D[31:00] bit order wouldbe: 0x5599AA66. For swapped and unswapped formats see “Configuration Data FileFormats.”.Table 1-5:Bus Width Detection PatternD[24:31]D[16:23]D[8:15]D[0:7]Comments0xFF0xFF0xFF0xFF0x000x000x000xBB Bus Width Pattern0x110x220x000x44Bus Width Pattern0xFF0xFF0xFF0xFF0xFF0xFF0xFF0xFF0xAA0x990x550x66Sync Word……………Bus width auto detection is transparent to most users, because all configuration bitstreams(BIT or RBT files) generated by the Xilinx ISE® Bitstream Generator (BitGen) softwareinclude the Bus Width Auto Detection pattern. These patterns are ignored by theconfiguration logic if the Mode pins are set to Master Serial, Slave Serial, JTAG, or SPImode.For the x8 bus, the configuration bus width detection logic first finds 0xBB on the D[0:7]pins, followed by 0x11. For the x16 bus, the configuration bus width detection logic firstfinds 0xBB on D[0:7] followed by 0x22. For the x32 bus, the configuration bus widthdetection logic first finds 0xBB, on D[0:7], followed by 0x44.If the immediate byte after 0xBB is not 0x11, 0x22, or 0x44, the bus width state machine isreset to search for the next 0xBB until a valid sequence is found. Then it switches to theappropriate external bus width and starts looking for the Sync word.Sync WordA special Sync word is used to allow configuration logic to align at a 32-bit word boundary.No packet processed by the FPGA until the Sync word is found. The bus width must bedetected successfully for parallel configuration modes before the Sync word can bedetected. Table1-6 shows the Sync word in an unswapped bitstream format.Table 1-6:Sync Word31:2423:1615:87:00xAA0x990x550x66Generating PROM FilesGenerating PROM FilesPROM files are generated from bitstream files with the PROMGen utility. Users can accessPROMGen directly from the command line or indirectly through the iMPACT FileGeneration Mode. For PROMGen syntax, refer to the Development System Reference Guide.For information on iMPACT, refer to the ISE® Software Documentation). PROM files serveto reformat bitstream files for PROM programming and combine bitstream files for serialdaisy chains (see “PROM Files for Serial Daisy Chains”).PROM Files for Serial Daisy ChainsConfiguration data for serial daisy chains requires special formatting because separate BITfiles cannot simply be concatenated together to program the daisy chain. The specialformatting is performed by PROMGen (or iMPACT) when generating a PROM file frommultiple bitstreams. To generate the PROM file, specify multiple bitstreams using thePROMGen -n, -u, and -d options or the iMPACT File Generation Wizard. Refer tosoftware documentation for details.PROMGen reformats the configuration bitstreams by nesting downstream configurationdata into configuration packets for upstream devices. Attempting to program the chain bysending multiple bitstreams to the first device causes the first device to configure and thenignore the subsequent data.PROM Files for SelectMAP ConfigurationThe MCS file format is most commonly used to program Xilinx configuration PROMs thatin turn program a single FPGA in SelectMAP mode. For custom configuration solutions,the BIN and HEX files are the easiest PROM file formats to use due to their raw data format.In some cases, additional formatting is required; refer to XAPP502, Using a Microprocessorto Configure Xilinx FPGAs via Slave Serial or SelectMAP Mode for details.If multiple configuration bitstreams for a SelectMAP configuration reside on a singlememory device, the bitstreams must not be combined into a serial daisy chain PROM file.Instead, the target memory device should be programmed with multiple BIN or HEX files.If a single PROM file with multiple, separate data streams is needed, one can be generatedin iMPACT by targeting a Parallel PROM, then selecting the appropriate number of datastreams. This can also be accomplished through the PROMGen command line. Refer toPROMGen software documentation for details.For Platform Flash XL-based SelectMAP configuration, use the iMPACT software togenerate an MCS PROM file. Select the Xilinx XCF128X device as the target PROM devicetype for creating the file. See UG438, Platform Flash XL User Guid e, for PROM filegeneration instructions.PROM Files for SPI/BPI ConfigurationThe -d and -u options in PROMGen or the iMPACT File Generation Wizard are used tocreate PROM files for third-party Flash devices. The output format supported by yourthird-party programmer should be chosen. Some BPI devices require endian-swapping tobe enabled when programming the PROM file. Refer to the Flash vendor's documentation.Bit SwappingBit swapping is the swapping of the bits within a byte. The MCS, EXO, and TEK PROM fileformats are always bit swapped. The HEX file format can be bit swapped or not bit4.The PROM in this diagram represents one or more Xilinx PROMs. Multiple PROMscan be cascaded to increase the overall configuration storage capacity.5.The BIT file must be reformatted into a PROM file before it can be stored on thePROM. Refer to the “Generating PROM Files” section.6.On some Xilinx PROMs, the reset polarity is programmable. RESET should beconfigured as active Low when using this setup.7.For ganged serial configuration, all devices must be identical (same IDCODE) andmust be configured with the same bitstream.8.The CCLK net requires Thevenin parallel termination. See “Board Layout forConfiguration Clock (CCLK),” page73.9.Ganged serial configuration is specific to the Platform Flash XCFS and XCFP PROMonly.10.Fallback and Multiboot are not supported in ganged serial configuration.There are a number of important considerations for ganged serial configuration:∙Startup Sequencing (GTS)GTS should be released before DONE or during the same cycle as DONE to ensure all devices are operational when all DONE pins have been released.∙Disable the Active DONE Driver for All DevicesFor ganged serial configuration, the active DONE driver must be disabled for all devices if the DONE pins are tied together, because there can be variations in the startup sequencing of each device. A pull-up resistor is therefore required on the common DONE signal.-g DriveDone:no (BitGen option, all devices)∙Connect all DONE pins if using a Master DeviceIt is important to connect the DONE pins for all devices in ganged serial configuration if one FPGA is used as the Master device. Failing to connect the DONE pins can cause configuration to fail for individual devices in this case. If all devices are set for Slave serial mode, the DONE pins can be disconnected (if the external CCLK sourcecontinues toggling until all DONE pins go High).For debugging purposes, it is often helpful to have a way of disconnecting individual DONE pins from the common DONE signal.∙DONE Pin Rise TimeAfter all DONE pins are released, the DONE pin should rise from logic 0 to logic 1 in one CCLK cycle. If additional time is required for the DONE signal to rise, the BitGen donepipe option can be set for all devices in the serial daisy chain.∙Configuration Clock (CCLK) as Clock Signal for Board LayoutThe CCLK signal is relatively slow, but the edge rates on the Virtex-5 input buffers are very fast. Even minor signal integrity problems on the CCLK signal can cause the configuration to fail. (Typical failure mode: DONE Low and INIT_B High.) Therefore, design practices that focus on signal integrity, including signal integrity simulation with IBIS, are recommended.∙Signal FanoutDesigners must focus on good signal integrity when using ganged serialconfiguration. Signal integrity simulation is recommended.∙PROM Files for Ganged Serial ConfigurationBoard Layout for Configuration Clock (CCLK)。