Requirement of a 5'-linear sequence on minus strands for plus-strand synthesis of a satellite RNA
Native Instruments MASCHINE MK3 用户手册说明书
The information in this document is subject to change without notice and does not represent a commitment on the part of Native Instruments GmbH. The software described by this docu-ment is subject to a License Agreement and may not be copied to other media. No part of this publication may be copied, reproduced or otherwise transmitted or recorded, for any purpose, without prior written permission by Native Instruments GmbH, hereinafter referred to as Native Instruments.“Native Instruments”, “NI” and associated logos are (registered) trademarks of Native Instru-ments GmbH.ASIO, VST, HALion and Cubase are registered trademarks of Steinberg Media Technologies GmbH.All other product and company names are trademarks™ or registered® trademarks of their re-spective holders. Use of them does not imply any affiliation with or endorsement by them.Document authored by: David Gover and Nico Sidi.Software version: 2.8 (02/2019)Hardware version: MASCHINE MK3Special thanks to the Beta Test Team, who were invaluable not just in tracking down bugs, but in making this a better product.NATIVE INSTRUMENTS GmbH Schlesische Str. 29-30D-10997 Berlin Germanywww.native-instruments.de NATIVE INSTRUMENTS North America, Inc. 6725 Sunset Boulevard5th FloorLos Angeles, CA 90028USANATIVE INSTRUMENTS K.K.YO Building 3FJingumae 6-7-15, Shibuya-ku, Tokyo 150-0001Japanwww.native-instruments.co.jp NATIVE INSTRUMENTS UK Limited 18 Phipp StreetLondon EC2A 4NUUKNATIVE INSTRUMENTS FRANCE SARL 113 Rue Saint-Maur75011 ParisFrance SHENZHEN NATIVE INSTRUMENTS COMPANY Limited 5F, Shenzhen Zimao Center111 Taizi Road, Nanshan District, Shenzhen, GuangdongChina© NATIVE INSTRUMENTS GmbH, 2019. All rights reserved.Table of Contents1Welcome to MASCHINE (25)1.1MASCHINE Documentation (26)1.2Document Conventions (27)1.3New Features in MASCHINE 2.8 (29)1.4New Features in MASCHINE 2.7.10 (31)1.5New Features in MASCHINE 2.7.8 (31)1.6New Features in MASCHINE 2.7.7 (32)1.7New Features in MASCHINE 2.7.4 (33)1.8New Features in MASCHINE 2.7.3 (36)2Quick Reference (38)2.1Using Your Controller (38)2.1.1Controller Modes and Mode Pinning (38)2.1.2Controlling the Software Views from Your Controller (40)2.2MASCHINE Project Overview (43)2.2.1Sound Content (44)2.2.2Arrangement (45)2.3MASCHINE Hardware Overview (48)2.3.1MASCHINE Hardware Overview (48)2.3.1.1Control Section (50)2.3.1.2Edit Section (53)2.3.1.3Performance Section (54)2.3.1.4Group Section (56)2.3.1.5Transport Section (56)2.3.1.6Pad Section (58)2.3.1.7Rear Panel (63)2.4MASCHINE Software Overview (65)2.4.1Header (66)2.4.2Browser (68)2.4.3Arranger (70)2.4.4Control Area (73)2.4.5Pattern Editor (74)3Basic Concepts (76)3.1Important Names and Concepts (76)3.2Adjusting the MASCHINE User Interface (79)3.2.1Adjusting the Size of the Interface (79)3.2.2Switching between Ideas View and Song View (80)3.2.3Showing/Hiding the Browser (81)3.2.4Showing/Hiding the Control Lane (81)3.3Common Operations (82)3.3.1Using the 4-Directional Push Encoder (82)3.3.2Pinning a Mode on the Controller (83)3.3.3Adjusting Volume, Swing, and Tempo (84)3.3.4Undo/Redo (87)3.3.5List Overlay for Selectors (89)3.3.6Zoom and Scroll Overlays (90)3.3.7Focusing on a Group or a Sound (91)3.3.8Switching Between the Master, Group, and Sound Level (96)3.3.9Navigating Channel Properties, Plug-ins, and Parameter Pages in the Control Area.973.3.9.1Extended Navigate Mode on Your Controller (102)3.3.10Navigating the Software Using the Controller (105)3.3.11Using Two or More Hardware Controllers (106)3.3.12Touch Auto-Write Option (108)3.4Native Kontrol Standard (110)3.5Stand-Alone and Plug-in Mode (111)3.5.1Differences between Stand-Alone and Plug-in Mode (112)3.5.2Switching Instances (113)3.5.3Controlling Various Instances with Different Controllers (114)3.6Host Integration (114)3.6.1Setting up Host Integration (115)3.6.1.1Setting up Ableton Live (macOS) (115)3.6.1.2Setting up Ableton Live (Windows) (116)3.6.1.3Setting up Apple Logic Pro X (116)3.6.2Integration with Ableton Live (117)3.6.3Integration with Apple Logic Pro X (119)3.7Preferences (120)3.7.1Preferences – General Page (121)3.7.2Preferences – Audio Page (126)3.7.3Preferences – MIDI Page (130)3.7.4Preferences – Default Page (133)3.7.5Preferences – Library Page (137)3.7.6Preferences – Plug-ins Page (145)3.7.7Preferences – Hardware Page (150)3.7.8Preferences – Colors Page (154)3.8Integrating MASCHINE into a MIDI Setup (156)3.8.1Connecting External MIDI Equipment (156)3.8.2Sync to External MIDI Clock (157)3.8.3Send MIDI Clock (158)3.9Syncing MASCHINE using Ableton Link (159)3.9.1Connecting to a Network (159)3.9.2Joining and Leaving a Link Session (159)3.10Using a Pedal with the MASCHINE Controller (160)3.11File Management on the MASCHINE Controller (161)4Browser (163)4.1Browser Basics (163)4.1.1The MASCHINE Library (163)4.1.2Browsing the Library vs. Browsing Your Hard Disks (164)4.2Searching and Loading Files from the Library (165)4.2.1Overview of the Library Pane (165)4.2.2Selecting or Loading a Product and Selecting a Bank from the Browser (170)4.2.2.1[MK3] Browsing by Product Category Using the Controller (174)4.2.2.2[MK3] Browsing by Product Vendor Using the Controller (174)4.2.3Selecting a Product Category, a Product, a Bank, and a Sub-Bank (175)4.2.3.1Selecting a Product Category, a Product, a Bank, and a Sub-Bank on theController (179)4.2.4Selecting a File Type (180)4.2.5Choosing Between Factory and User Content (181)4.2.6Selecting Type and Character Tags (182)4.2.7List and Tag Overlays in the Browser (186)4.2.8Performing a Text Search (188)4.2.9Loading a File from the Result List (188)4.3Additional Browsing Tools (193)4.3.1Loading the Selected Files Automatically (193)4.3.2Auditioning Instrument Presets (195)4.3.3Auditioning Samples (196)4.3.4Loading Groups with Patterns (197)4.3.5Loading Groups with Routing (198)4.3.6Displaying File Information (198)4.4Using Favorites in the Browser (199)4.5Editing the Files’ Tags and Properties (203)4.5.1Attribute Editor Basics (203)4.5.2The Bank Page (205)4.5.3The Types and Characters Pages (205)4.5.4The Properties Page (208)4.6Loading and Importing Files from Your File System (209)4.6.1Overview of the FILES Pane (209)4.6.2Using Favorites (211)4.6.3Using the Location Bar (212)4.6.4Navigating to Recent Locations (213)4.6.5Using the Result List (214)4.6.6Importing Files to the MASCHINE Library (217)4.7Locating Missing Samples (219)4.8Using Quick Browse (221)5Managing Sounds, Groups, and Your Project (225)5.1Overview of the Sounds, Groups, and Master (225)5.1.1The Sound, Group, and Master Channels (226)5.1.2Similarities and Differences in Handling Sounds and Groups (227)5.1.3Selecting Multiple Sounds or Groups (228)5.2Managing Sounds (233)5.2.1Loading Sounds (235)5.2.2Pre-listening to Sounds (236)5.2.3Renaming Sound Slots (237)5.2.4Changing the Sound’s Color (237)5.2.5Saving Sounds (239)5.2.6Copying and Pasting Sounds (241)5.2.7Moving Sounds (244)5.2.8Resetting Sound Slots (245)5.3Managing Groups (247)5.3.1Creating Groups (248)5.3.2Loading Groups (249)5.3.3Renaming Groups (251)5.3.4Changing the Group’s Color (251)5.3.5Saving Groups (253)5.3.6Copying and Pasting Groups (255)5.3.7Reordering Groups (258)5.3.8Deleting Groups (259)5.4Exporting MASCHINE Objects and Audio (260)5.4.1Saving a Group with its Samples (261)5.4.2Saving a Project with its Samples (262)5.4.3Exporting Audio (264)5.5Importing Third-Party File Formats (270)5.5.1Loading REX Files into Sound Slots (270)5.5.2Importing MPC Programs to Groups (271)6Playing on the Controller (275)6.1Adjusting the Pads (275)6.1.1The Pad View in the Software (275)6.1.2Choosing a Pad Input Mode (277)6.1.3Adjusting the Base Key (280)6.1.4Using Choke Groups (282)6.1.5Using Link Groups (284)6.2Adjusting the Key, Choke, and Link Parameters for Multiple Sounds (286)6.3Playing Tools (287)6.3.1Mute and Solo (288)6.3.2Choke All Notes (292)6.3.3Groove (293)6.3.4Level, Tempo, Tune, and Groove Shortcuts on Your Controller (295)6.3.5Tap Tempo (299)6.4Performance Features (300)6.4.1Overview of the Perform Features (300)6.4.2Selecting a Scale and Creating Chords (303)6.4.3Scale and Chord Parameters (303)6.4.4Creating Arpeggios and Repeated Notes (316)6.4.5Swing on Note Repeat / Arp Output (321)6.5Using Lock Snapshots (322)6.5.1Creating a Lock Snapshot (322)6.5.2Using Extended Lock (323)6.5.3Updating a Lock Snapshot (323)6.5.4Recalling a Lock Snapshot (324)6.5.5Morphing Between Lock Snapshots (324)6.5.6Deleting a Lock Snapshot (325)6.5.7Triggering Lock Snapshots via MIDI (326)6.6Using the Smart Strip (327)6.6.1Pitch Mode (328)6.6.2Modulation Mode (328)6.6.3Perform Mode (328)6.6.4Notes Mode (329)7Working with Plug-ins (330)7.1Plug-in Overview (330)7.1.1Plug-in Basics (330)7.1.2First Plug-in Slot of Sounds: Choosing the Sound’s Role (334)7.1.3Loading, Removing, and Replacing a Plug-in (335)7.1.3.1Browser Plug-in Slot Selection (341)7.1.4Adjusting the Plug-in Parameters (344)7.1.5Bypassing Plug-in Slots (344)7.1.6Using Side-Chain (346)7.1.7Moving Plug-ins (346)7.1.8Alternative: the Plug-in Strip (348)7.1.9Saving and Recalling Plug-in Presets (348)7.1.9.1Saving Plug-in Presets (349)7.1.9.2Recalling Plug-in Presets (350)7.1.9.3Removing a Default Plug-in Preset (351)7.2The Sampler Plug-in (352)7.2.1Page 1: Voice Settings / Engine (354)7.2.2Page 2: Pitch / Envelope (356)7.2.3Page 3: FX / Filter (359)7.2.4Page 4: Modulation (361)7.2.5Page 5: LFO (363)7.2.6Page 6: Velocity / Modwheel (365)7.3Using Native Instruments and External Plug-ins (367)7.3.1Opening/Closing Plug-in Windows (367)7.3.2Using the VST/AU Plug-in Parameters (370)7.3.3Setting Up Your Own Parameter Pages (371)7.3.4Using VST/AU Plug-in Presets (376)7.3.5Multiple-Output Plug-ins and Multitimbral Plug-ins (378)8Using the Audio Plug-in (380)8.1Loading a Loop into the Audio Plug-in (384)8.2Editing Audio in the Audio Plug-in (385)8.3Using Loop Mode (386)8.4Using Gate Mode (388)9Using the Drumsynths (390)9.1Drumsynths – General Handling (391)9.1.1Engines: Many Different Drums per Drumsynth (391)9.1.2Common Parameter Organization (391)9.1.3Shared Parameters (394)9.1.4Various Velocity Responses (394)9.1.5Pitch Range, Tuning, and MIDI Notes (394)9.2The Kicks (395)9.2.1Kick – Sub (397)9.2.2Kick – Tronic (399)9.2.3Kick – Dusty (402)9.2.4Kick – Grit (403)9.2.5Kick – Rasper (406)9.2.6Kick – Snappy (407)9.2.7Kick – Bold (409)9.2.8Kick – Maple (411)9.2.9Kick – Push (412)9.3The Snares (414)9.3.1Snare – Volt (416)9.3.2Snare – Bit (418)9.3.3Snare – Pow (420)9.3.4Snare – Sharp (421)9.3.5Snare – Airy (423)9.3.6Snare – Vintage (425)9.3.7Snare – Chrome (427)9.3.8Snare – Iron (429)9.3.9Snare – Clap (431)9.3.10Snare – Breaker (433)9.4The Hi-hats (435)9.4.1Hi-hat – Silver (436)9.4.2Hi-hat – Circuit (438)9.4.3Hi-hat – Memory (440)9.4.4Hi-hat – Hybrid (442)9.4.5Creating a Pattern with Closed and Open Hi-hats (444)9.5The Toms (445)9.5.1Tom – Tronic (447)9.5.2Tom – Fractal (449)9.5.3Tom – Floor (453)9.5.4Tom – High (455)9.6The Percussions (456)9.6.1Percussion – Fractal (458)9.6.2Percussion – Kettle (461)9.6.3Percussion – Shaker (463)9.7The Cymbals (467)9.7.1Cymbal – Crash (469)9.7.2Cymbal – Ride (471)10Using the Bass Synth (474)10.1Bass Synth – General Handling (475)10.1.1Parameter Organization (475)10.1.2Bass Synth Parameters (477)11Working with Patterns (479)11.1Pattern Basics (479)11.1.1Pattern Editor Overview (480)11.1.2Navigating the Event Area (486)11.1.3Following the Playback Position in the Pattern (488)11.1.4Jumping to Another Playback Position in the Pattern (489)11.1.5Group View and Keyboard View (491)11.1.6Adjusting the Arrange Grid and the Pattern Length (493)11.1.7Adjusting the Step Grid and the Nudge Grid (497)11.2Recording Patterns in Real Time (501)11.2.1Recording Your Patterns Live (501)11.2.2The Record Prepare Mode (504)11.2.3Using the Metronome (505)11.2.4Recording with Count-in (506)11.2.5Quantizing while Recording (508)11.3Recording Patterns with the Step Sequencer (508)11.3.1Step Mode Basics (508)11.3.2Editing Events in Step Mode (511)11.3.3Recording Modulation in Step Mode (513)11.4Editing Events (514)11.4.1Editing Events with the Mouse: an Overview (514)11.4.2Creating Events/Notes (517)11.4.3Selecting Events/Notes (518)11.4.4Editing Selected Events/Notes (526)11.4.5Deleting Events/Notes (532)11.4.6Cut, Copy, and Paste Events/Notes (535)11.4.7Quantizing Events/Notes (538)11.4.8Quantization While Playing (540)11.4.9Doubling a Pattern (541)11.4.10Adding Variation to Patterns (541)11.5Recording and Editing Modulation (546)11.5.1Which Parameters Are Modulatable? (547)11.5.2Recording Modulation (548)11.5.3Creating and Editing Modulation in the Control Lane (550)11.6Creating MIDI Tracks from Scratch in MASCHINE (555)11.7Managing Patterns (557)11.7.1The Pattern Manager and Pattern Mode (558)11.7.2Selecting Patterns and Pattern Banks (560)11.7.3Creating Patterns (563)11.7.4Deleting Patterns (565)11.7.5Creating and Deleting Pattern Banks (566)11.7.6Naming Patterns (568)11.7.7Changing the Pattern’s Color (570)11.7.8Duplicating, Copying, and Pasting Patterns (571)11.7.9Moving Patterns (574)11.7.10Adjusting Pattern Length in Fine Increments (575)11.8Importing/Exporting Audio and MIDI to/from Patterns (576)11.8.1Exporting Audio from Patterns (576)11.8.2Exporting MIDI from Patterns (577)11.8.3Importing MIDI to Patterns (580)12Audio Routing, Remote Control, and Macro Controls (589)12.1Audio Routing in MASCHINE (590)12.1.1Sending External Audio to Sounds (591)12.1.2Configuring the Main Output of Sounds and Groups (596)12.1.3Setting Up Auxiliary Outputs for Sounds and Groups (601)12.1.4Configuring the Master and Cue Outputs of MASCHINE (605)12.1.5Mono Audio Inputs (610)12.1.5.1Configuring External Inputs for Sounds in Mix View (611)12.2Using MIDI Control and Host Automation (614)12.2.1Triggering Sounds via MIDI Notes (615)12.2.2Triggering Scenes via MIDI (622)12.2.3Controlling Parameters via MIDI and Host Automation (623)12.2.4Selecting VST/AU Plug-in Presets via MIDI Program Change (631)12.2.5Sending MIDI from Sounds (632)12.3Creating Custom Sets of Parameters with the Macro Controls (636)12.3.1Macro Control Overview (637)12.3.2Assigning Macro Controls Using the Software (638)12.3.3Assigning Macro Controls Using the Controller (644)13Controlling Your Mix (646)13.1Mix View Basics (646)13.1.1Switching between Arrange View and Mix View (646)13.1.2Mix View Elements (647)13.2The Mixer (649)13.2.1Displaying Groups vs. Displaying Sounds (650)13.2.2Adjusting the Mixer Layout (652)13.2.3Selecting Channel Strips (653)13.2.4Managing Your Channels in the Mixer (654)13.2.5Adjusting Settings in the Channel Strips (656)13.2.6Using the Cue Bus (660)13.3The Plug-in Chain (662)13.4The Plug-in Strip (663)13.4.1The Plug-in Header (665)13.4.2Panels for Drumsynths and Internal Effects (667)13.4.3Panel for the Sampler (668)13.4.4Custom Panels for Native Instruments Plug-ins (671)13.4.5Undocking a Plug-in Panel (Native Instruments and External Plug-ins Only) (675)13.5Controlling Your Mix from the Controller (677)13.5.1Navigating Your Channels in Mix Mode (678)13.5.2Adjusting the Level and Pan in Mix Mode (679)13.5.3Mute and Solo in Mix Mode (680)13.5.4Plug-in Icons in Mix Mode (680)14Using Effects (681)14.1Applying Effects to a Sound, a Group or the Master (681)14.1.1Adding an Effect (681)14.1.2Other Operations on Effects (690)14.1.3Using the Side-Chain Input (692)14.2Applying Effects to External Audio (695)14.2.1Step 1: Configure MASCHINE Audio Inputs (695)14.2.2Step 2: Set up a Sound to Receive the External Input (698)14.2.3Step 3: Load an Effect to Process an Input (700)14.3Creating a Send Effect (701)14.3.1Step 1: Set Up a Sound or Group as Send Effect (702)14.3.2Step 2: Route Audio to the Send Effect (706)14.3.3 A Few Notes on Send Effects (708)14.4Creating Multi-Effects (709)15Effect Reference (712)15.1Dynamics (713)15.1.1Compressor (713)15.1.2Gate (717)15.1.3Transient Master (721)15.1.4Limiter (723)15.1.5Maximizer (727)15.2Filtering Effects (730)15.2.1EQ (730)15.2.2Filter (733)15.2.3Cabinet (737)15.3Modulation Effects (738)15.3.1Chorus (738)15.3.2Flanger (740)15.3.3FM (742)15.3.4Freq Shifter (743)15.3.5Phaser (745)15.4Spatial and Reverb Effects (747)15.4.1Ice (747)15.4.2Metaverb (749)15.4.3Reflex (750)15.4.4Reverb (Legacy) (752)15.4.5Reverb (754)15.4.5.1Reverb Room (754)15.4.5.2Reverb Hall (757)15.4.5.3Plate Reverb (760)15.5Delays (762)15.5.1Beat Delay (762)15.5.2Grain Delay (765)15.5.3Grain Stretch (767)15.5.4Resochord (769)15.6Distortion Effects (771)15.6.1Distortion (771)15.6.2Lofi (774)15.6.3Saturator (775)15.7Perform FX (779)15.7.1Filter (780)15.7.2Flanger (782)15.7.3Burst Echo (785)15.7.4Reso Echo (787)15.7.5Ring (790)15.7.6Stutter (792)15.7.7Tremolo (795)15.7.8Scratcher (798)16Working with the Arranger (801)16.1Arranger Basics (801)16.1.1Navigating Song View (804)16.1.2Following the Playback Position in Your Project (806)16.1.3Performing with Scenes and Sections using the Pads (807)16.2Using Ideas View (811)16.2.1Scene Overview (811)16.2.2Creating Scenes (813)16.2.3Assigning and Removing Patterns (813)16.2.4Selecting Scenes (817)16.2.5Deleting Scenes (818)16.2.6Creating and Deleting Scene Banks (820)16.2.7Clearing Scenes (820)16.2.8Duplicating Scenes (821)16.2.9Reordering Scenes (822)16.2.10Making Scenes Unique (824)16.2.11Appending Scenes to Arrangement (825)16.2.12Naming Scenes (826)16.2.13Changing the Color of a Scene (827)16.3Using Song View (828)16.3.1Section Management Overview (828)16.3.2Creating Sections (833)16.3.3Assigning a Scene to a Section (834)16.3.4Selecting Sections and Section Banks (835)16.3.5Reorganizing Sections (839)16.3.6Adjusting the Length of a Section (840)16.3.6.1Adjusting the Length of a Section Using the Software (841)16.3.6.2Adjusting the Length of a Section Using the Controller (843)16.3.7Clearing a Pattern in Song View (843)16.3.8Duplicating Sections (844)16.3.8.1Making Sections Unique (845)16.3.9Removing Sections (846)16.3.10Renaming Scenes (848)16.3.11Clearing Sections (849)16.3.12Creating and Deleting Section Banks (850)16.3.13Working with Patterns in Song view (850)16.3.13.1Creating a Pattern in Song View (850)16.3.13.2Selecting a Pattern in Song View (850)16.3.13.3Clearing a Pattern in Song View (851)16.3.13.4Renaming a Pattern in Song View (851)16.3.13.5Coloring a Pattern in Song View (851)16.3.13.6Removing a Pattern in Song View (852)16.3.13.7Duplicating a Pattern in Song View (852)16.3.14Enabling Auto Length (852)16.3.15Looping (853)16.3.15.1Setting the Loop Range in the Software (854)16.4Playing with Sections (855)16.4.1Jumping to another Playback Position in Your Project (855)16.5Triggering Sections or Scenes via MIDI (856)16.6The Arrange Grid (858)16.7Quick Grid (860)17Sampling and Sample Mapping (862)17.1Opening the Sample Editor (862)17.2Recording Audio (863)17.2.1Opening the Record Page (863)17.2.2Selecting the Source and the Recording Mode (865)17.2.3Arming, Starting, and Stopping the Recording (868)17.2.5Using the Footswitch for Recording Audio (871)17.2.6Checking Your Recordings (872)17.2.7Location and Name of Your Recorded Samples (876)17.3Editing a Sample (876)17.3.1Using the Edit Page (877)17.3.2Audio Editing Functions (882)17.4Slicing a Sample (890)17.4.1Opening the Slice Page (891)17.4.2Adjusting the Slicing Settings (893)17.4.3Live Slicing (898)17.4.3.1Live Slicing Using the Controller (898)17.4.3.2Delete All Slices (899)17.4.4Manually Adjusting Your Slices (899)17.4.5Applying the Slicing (906)17.5Mapping Samples to Zones (912)17.5.1Opening the Zone Page (912)17.5.2Zone Page Overview (913)17.5.3Selecting and Managing Zones in the Zone List (915)17.5.4Selecting and Editing Zones in the Map View (920)17.5.5Editing Zones in the Sample View (924)17.5.6Adjusting the Zone Settings (927)17.5.7Adding Samples to the Sample Map (934)18Appendix: Tips for Playing Live (937)18.1Preparations (937)18.1.1Focus on the Hardware (937)18.1.2Customize the Pads of the Hardware (937)18.1.3Check Your CPU Power Before Playing (937)18.1.4Name and Color Your Groups, Patterns, Sounds and Scenes (938)18.1.5Consider Using a Limiter on Your Master (938)18.1.6Hook Up Your Other Gear and Sync It with MIDI Clock (938)18.1.7Improvise (938)18.2Basic Techniques (938)18.2.1Use Mute and Solo (938)18.2.2Use Scene Mode and Tweak the Loop Range (939)18.2.3Create Variations of Your Drum Patterns in the Step Sequencer (939)18.2.4Use Note Repeat (939)18.2.5Set Up Your Own Multi-effect Groups and Automate Them (939)18.3Special Tricks (940)18.3.1Changing Pattern Length for Variation (940)18.3.2Using Loops to Cycle Through Samples (940)18.3.3Using Loops to Cycle Through Samples (940)18.3.4Load Long Audio Files and Play with the Start Point (940)19Troubleshooting (941)19.1Knowledge Base (941)19.2Technical Support (941)19.3Registration Support (942)19.4User Forum (942)20Glossary (943)Index (951)1Welcome to MASCHINEThank you for buying MASCHINE!MASCHINE is a groove production studio that implements the familiar working style of classi-cal groove boxes along with the advantages of a computer based system. MASCHINE is ideal for making music live, as well as in the studio. It’s the hands-on aspect of a dedicated instru-ment, the MASCHINE hardware controller, united with the advanced editing features of the MASCHINE software.Creating beats is often not very intuitive with a computer, but using the MASCHINE hardware controller to do it makes it easy and fun. You can tap in freely with the pads or use Note Re-peat to jam along. Alternatively, build your beats using the step sequencer just as in classic drum machines.Patterns can be intuitively combined and rearranged on the fly to form larger ideas. You can try out several different versions of a song without ever having to stop the music.Since you can integrate it into any sequencer that supports VST, AU, or AAX plug-ins, you can reap the benefits in almost any software setup, or use it as a stand-alone application. You can sample your own material, slice loops and rearrange them easily.However, MASCHINE is a lot more than an ordinary groovebox or sampler: it comes with an inspiring 7-gigabyte library, and a sophisticated, yet easy to use tag-based Browser to give you instant access to the sounds you are looking for.What’s more, MASCHINE provides lots of options for manipulating your sounds via internal ef-fects and other sound-shaping possibilities. You can also control external MIDI hardware and 3rd-party software with the MASCHINE hardware controller, while customizing the functions of the pads, knobs and buttons according to your needs utilizing the included Controller Editor application. We hope you enjoy this fantastic instrument as much as we do. Now let’s get go-ing!—The MASCHINE team at Native Instruments.MASCHINE Documentation1.1MASCHINE DocumentationNative Instruments provide many information sources regarding MASCHINE. The main docu-ments should be read in the following sequence:1.MASCHINE Getting Started: This document provides a practical approach to MASCHINE viaa set of tutorials covering easy and more advanced tasks in order to help you familiarizeyourself with MASCHINE.2.MASCHINE Manual (this document): The MASCHINE Manual provides you with a compre-hensive description of all MASCHINE software and hardware features.Additional documentation sources provide you with details on more specific topics:▪Controller Editor Manual: Besides using your MASCHINE hardware controller together withits dedicated MASCHINE software, you can also use it as a powerful and highly versatileMIDI controller to pilot any other MIDI-capable application or device. This is made possibleby the Controller Editor software, an application that allows you to precisely define all MIDIassignments for your MASCHINE controller. The Controller Editor was installed during theMASCHINE installation procedure. For more information on this, please refer to the Con-troller Editor Manual available as a PDF file via the Help menu of Controller Editor.▪Online Support Videos: You can find a number of support videos on The Official Native In-struments Support Channel under the following URL: https:///NIsupport-EN. We recommend that you follow along with these instructions while the respective ap-plication is running on your computer.Other Online Resources:If you are experiencing problems related to your Native Instruments product that the supplied documentation does not cover, there are several ways of getting help:▪Knowledge Base▪User Forum▪Technical Support▪Registration SupportYou will find more information on these subjects in the chapter Troubleshooting.1.2Document ConventionsThis section introduces you to the signage and text highlighting used in this manual. This man-ual uses particular formatting to point out special facts and to warn you of potential issues. The icons introducing these notes let you see what kind of information is to be expected:This document uses particular formatting to point out special facts and to warn you of poten-tial issues. The icons introducing the following notes let you see what kind of information can be expected:Furthermore, the following formatting is used:▪Text appearing in (drop-down) menus (such as Open…, Save as… etc.) in the software and paths to locations on your hard disk or other storage devices is printed in italics.▪Text appearing elsewhere (labels of buttons, controls, text next to checkboxes etc.) in the software is printed in blue. Whenever you see this formatting applied, you will find the same text appearing somewhere on the screen.▪Text appearing on the displays of the controller is printed in light grey. Whenever you see this formatting applied, you will find the same text on a controller display.▪Text appearing on labels of the hardware controller is printed in orange. Whenever you see this formatting applied, you will find the same text on the controller.▪Important names and concepts are printed in bold.▪References to keys on your computer’s keyboard you’ll find put in square brackets (e.g.,“Press [Shift] + [Enter]”).►Single instructions are introduced by this play button type arrow.→Results of actions are introduced by this smaller arrow.Naming ConventionThroughout the documentation we will refer to MASCHINE controller (or just controller) as the hardware controller and MASCHINE software as the software installed on your computer.The term “effect” will sometimes be abbreviated as “FX” when referring to elements in the MA-SCHINE software and hardware. These terms have the same meaning.Button Combinations and Shortcuts on Your ControllerMost instructions will use the “+” sign to indicate buttons (or buttons and pads) that must be pressed simultaneously, starting with the button indicated first. E.g., an instruction such as:“Press SHIFT + PLAY”means:1.Press and hold SHIFT.2.While holding SHIFT, press PLAY and release it.3.Release SHIFT.Unlabeled Buttons on the ControllerThe buttons and knobs above and below the displays on your MASCHINE controller do not have labels.。
美国伦布科技 Agilent 16800 Series Portable Logic Analyze
Agilent 16800 SeriesPortable Logic AnalyzersData SheetQuickly debug, validate,and optimize your digitalsystem – at a price thatfits your budget.Features and benefits•250 ps resolution (4 GHz) timingzoom to find elusive timing problemsquickly, without double probing•15” display, with available touchscreen, allows you to see more dataand navigate quicklymeasurements and displays of yourlogic analyzer and oscilloscope datalet you effectively track downproblems across the analog anddigital portions of your design•Eight models with34/68/102/136/204 channels,up to 32M memory depth andmodels with a pattern generatorprovide the measurement flexibilityfor any budget•Application support for every aspectof today’s complex designs – FPGAdynamic probe, digital VSA (vectorsignal analysis) and broad processorand bus support2Selection Guide for 16800 Series Portable Logic AnalyzersModels with a built-in pattern generator give you more measurement flexibility1Pattern generator available with 16821A, 16822A and 16823A.Choose from eight models to get the measurement capability for your specific applicationProbes are ordered separately. Please specify probes when ordering to ensure the correct connection between your logic analyzer, pattern generator, and the device under test.Agilent 16800 Series portable logic analyzers offer the performance, applications, and usability your digital development team needs to quickly debug, validate, and optimize your digital system – at a price that fits your budget.The logic analyzer’s timing and state acquisition gives you the power to:•Accurately measure precise timing relationships using4GHz (250ps) timing zoomwith 64K depth•Find anomalies separated in time with memory depthsupgradeable to 32M•Buy what you need today and upgrade in the future. 16800Series logic analyzers comewith independent upgrades for memory depth and state speed •Sample synchronous buses accurately and confidentlyusing eye finder. Eye finderautomatically adjuststhreshold and setup andhold to give you the highestconfidence in measurementson high-speed buses•Track problems from symptom to root cause across severalmeasurement modes byviewing time-correlated datain waveform/chart, listing,inverse assembly, source code, or compare display •Set up triggers quickly andconfidently with intuitive,simple, quick, and advancedtriggering. This capabilitycombines new triggerfunctionality with an intuitiveuser interface•Access the signals that holdthe key to your system’sproblems with the industry’swidest range of probingaccessories with capacitiveloading down to 0.7 pF•Monitor and correlate multiplebuses with split analyzercapability, which providessingle and multi-bus support(timing, state, timing/state orstate/state configurations)Accurately measure precisetiming relationships16800 Series logic analyzers letyou make accurate high-speedtiming measurements with 4GHz(250ps) high-speed timing zoom. Aparallel acquisition architectureprovides high-speed timingmeasurements simultaneouslythrough the same probe used forstate or timing measurements.Timing zoom stays active all thetime with no tradeoffs. View dataat high resolution over longerperiods of time with 64-K-deeptiming zoom.Figure 1. With eight models to choose from, you can get alogic analyzer with measurement capabilities that meetyour needs.3Automate measurement setup and quickly gain diagnostic clues16800 Series logic analyzers make it easy for you to get up and running quickly by automating your measurement setup process. In addition, the logic analyzer’s setup/hold window (or sampling position) and threshold voltage settings are automatically determined so you can capture data on high-speed buses with the highest accuracy. Auto Threshold and Sample Position mode allow you to...•Obtain accurate and reliable measurements•Save time during measurement setup•Gain diagnostic clues and identify problem signalsquickly•Scan all signals and buses simultaneously or just a few•View results as a composite display or as individual signals•See skew between signals and buses•Find and fix inappropriate clock thresholds•Measure data valid windows•Identify signal integrityproblems related to rise times,fall times, data valid windowwidths Identify problem signals overhundreds of channels simultaneouslyAs timing and voltage marginscontinue to shrink, confidencein signal integrity becomes anincreasingly vital requirementin the design validation process.Eye scan lets you acquire signalintegrity information on allthe buses in your design, undera wide variety of operatingconditions, in a matter ofminutes. Identify problem signalsquickly for further investigationwith an oscilloscope. Results canbe viewed for each individualsignal or as a composite ofmultiple signals or buses.Extend the life of your equipmentEasily upgrade your 16800 Serieslogic analyzer. “Turn on”additional memory depth andstate speed when you need more.Purchase the capability youneed now, then upgrade as yourneeds evolve.Figure 2. Identify problem signals quickly by viewing eye diagrams across all buses and signals simultaneously.4578910A Built-in Pattern Generator Gives You Digital Stimulus and Responsein a Single InstrumentSelected 16800 Series models (16821A, 16822A and 16823A)also include a 48-channel pattern generator to drive down risk early in product development. With a pattern generator you can:•Substitute for missing boards,integrated circuits (ICs) or buses instead of waiting for missing pieces •Write software to createinfrequently encountered test conditions and verify that the code works – before complete hardware is available •Generate patterns necessary to put a circuit in a desired state,operate the circuit at full speed or step the circuit through a series of states •Create a circuit initialization sequence Agilent 16800 Series portable logic analyzers with a pattern generator offer a variety offeatures that make it easier for you to create digital stimulus tests.Vectors up to 48 bits wideVectors are defined as a “row” of labeled data values, with each data value from one to 48 bits wide. Each vector is output on the rising edge of the clock.Create stimulus patterns for the widest buses in your system.Depth up to 16 M vectorsWith the pattern generator, you can load and run up to 16Mvectors of stimulus. Depth on this scale is most useful when coupled with powerful stimulus generated by electronic design automation tools, such as SynaptiCAD’sWaveFormer and VeriLogger.These tools create stimulus using a combination of graphicallydrawn signals, timing parameters that constrain edges, clock signals,and timing and Boolean equations for describing complex signal behavior. The stimulus also can be created from design simulation waveforms. The SynaptiCAD tools allow you to convert .VCD files into .PGB files directly, offering you an integrated solution that saves you time.Synchronized clock outputYou can output data synchronized to either an internal or external clock. The external clock is input via a clock pod, and has nominimum frequency (other than a 2ns minimum high time).The internal clock is selectable between 1MHz and 300MHz in 1-MHz steps. A Clock Out signal is available from the clock pod and can be used as an edge strobe with a variable delay of up to 8ns.Initialize (INIT) block for repetitive runsWhen running repetitively, the vectors in the initialize (init)sequence are output only once,while the main sequence isoutput as a continually repeating sequence. This “init” sequence is very useful when the circuit or subsystem needs to be initialized.The repetitive run capability is especially helpful whenoperating the pattern generator independent of the logic analyzer.“Send Arm out to…” coordinates activity with the logic analyzerVerify how your system responds to a specific stimulus sequence by arming the logic analyzer from the pattern generator. A “Send Arm out to…” instruction acts as a trigger arming event for the logic analyzer or other test equipment to begin measurements. Arm setup and trigger setup of the logic analyzer determines the action initiated by “Send Arm out to…”.Figure 3. Models with a built-in pattern generator give you more measurement flexibility.“Wait for External Event…” forinput patternThe clock pod also accepts a 3-bit input pattern. These inputs are level-sensed so that any number of “Wait for External Event”instructions can be inserted into a stimulus program. Up to four pattern conditions can be defined from the OR-ing of the eight possible 3-bit input patterns. A “Wait for External Event” also can be defined to wait for an Arm. This Arm signal can come from the logic analyzer. “Wait for External Event…” allows you to executea specific stimulus sequence only when the defined external event occurs.Simplify creation of stimulus programs with user-defined macros and loops User macros permit you to define a pattern sequence once, then insert the macro by name wherever it is needed. Passing parameters to the macro will allow you to create a more generic macro. For each call to the macro you can specify unique values for the parameters.Loops enable you to repeat a defined block of vectors for a specified number of times. Loops and macros can be nested, except that a macro cannot be nested within another macro. At compile time, loops and macros are expanded in memory to alinear sequence.Convenient data entry andediting featureYou can conveniently enterpatterns in hex, octal, binary,decimal, and signed decimal(two’s complement) bases. Tosimplify data entry, you can viewthe data associated with anindividual label with multipleradixes. Delete, Insert, and Copycommands are provided for easyediting. Fast and convenientPattern Fills give the programmeruseful test patterns with a fewkey strokes. Fixed, Count, Rotate,Toggle, and Random patterns areavailable to help you quicklycreate a test pattern, suchas “walking ones.” Patternparameters, such as step size andrepeat frequency, can be specifiedin the pattern setup.ASCII input file format: your designtool connectionThe pattern generator supportsan ASCII file format to facilitateconnectivity to other tools in yourdesign environment. Because theASCII format does not support theinstructions listed earlier, theycannot be edited into the ASCIIfile. User macros and loops alsoare not supported, so the vectorsneed to be fully expanded in theASCII file. Many design tools willgenerate ASCII files and outputthe vectors in this linear sequence.Data must be in hex format, andeach label must represent a set ofcontiguous output channels.ConfigurationThe pattern generator operateswith the clock pods, data pods,and lead sets described later inthis document. At least one clockpod and one data pod must beselected to configure a functionalsystem. You can select from avariety of pods to provide thesignal source needed for your logicdevices. The data pods, clock podsand data cables use standardconnectors. The electricalcharacteristics of the data cablesare described for users withspecialized applications who wantto avoid the use of a data pod.Direct connection to yourtarget systemYou can connect the patterngenerator pods directly to astandard connector on your targetsystem. Use a 3M brand #2520Series or similar connector. Theclock or data pods will plug rightin. Short, flat cable jumpers canbe used if the clearance aroundthe connector is limited. Use a 3M#3365/20, or equivalent, ribboncable; a 3M #4620 Series orequivalent connector on thepattern generator pod end of thecable, and a 3M #3421 Series orequivalent connector at yourtarget system end of the cable.Probing accessoriesThe probe tips of theAgilent10474A, 10347A, 10498A,and E8142A lead sets plugdirectly into any 0.1-inch gridwith 0.026-inch to 0.033-inchdiameter round pins or 0.025-inchsquare pins. These probe tipswork with the Agilent5090-4356surface mount grabbers andwith the Agilent5959-0288through-hole grabbers, providingcompatibility with industrystandard pins.A Built-in Pattern Generator Gives You Digital Stimulus and Response in a Single Instrument3-STATE IN TTLPattern generator cable pin outsData cable (Pod end)Clock cable (Pod end)2122Unleash the Complementary Power of a Logic Analyzer and an Oscilloscope Seamless scope integrationwith View ScopeEasily make time-correlatedmeasurements between Agilentlogic analyzers and oscilloscopes.The time-correlated logic analyzerand oscilloscope waveforms areintegrated into a single logicanalyzer waveform display foreasy viewing and analysis. Youcan also trigger the oscilloscopefrom the logic analyzer (or viceversa), automatically de-skew thewaveforms and maintain markertracking between the twoinstruments. Perform thefollowing more effectively:•Validate signal integrity•Track down problems caused by signal integrity•Validate correct operation of A/D and D/A converters •Validate correct logical and timing relationships betweenthe analog and digital portions of a designConnectionThe Agilent logic analyzer and oscilloscope can be physically connected with standard BNC and LAN connections. Two BNC cables are connected for cross triggering, and the LAN connection is used to transfer data between the instruments. The View Scope correlation software is standard in the logic analyzer’s application software version 3.50 or higher. The View Scope software includes:•Ability to import some or all of the captured oscilloscopewaveforms•Auto scaling of the scopewaveforms for the best fit inthe logic analyzer displayFigure 4. View Scope seamlessly integrates your scopeand logic analyzer waveforms into a single display.2324Acquisition and analysis tools provide rapid insight into your toughest debug problemsYou have unique measurement and analysis needs. When you want to understand what your target is doing and why, you need acquisition and analysis tools that rapidly consolidate data into displays that provide insight into your system’s behavior.Figure 5. Perform in-depth time, frequency and modulation domain analysis on your digital baseband and IF signals with Agilent’s 89600 Vector Signal Analysis software.Save time analyzing your unique design with a turnkey setup Agilent Technologies and our partners provide an extensive range of bus and processor analysis probes. They provide non-intrusive, full-speed,real-time analysis to accelerate your debugging process.•Save time making bus-and processor-specificmeasurements withapplication specific analysisprobes that quickly andreliably connect to yourdevice under test•Display processor mnemonicsor bus cycle decode•Get support for acomprehensive list ofindustry-standard processorsand buses252627ProgrammabilityYou can write programs to control the logic analyzer application from remote computers on the local area network using COM or ASCII. The COM automation serveris part of the logic analyzer application. This software allows you to write programs to control the logic analyzer. All measurement functionality is controllable via the COM interface.The B4608A Remote ProgrammingInterface (RPI) lets you remotelycontrol a 16800 Series logicanalyzer by issuing ASCIIcommands to the TCP socketon port 6500. This interface isdesigned to be as similar aspossible to the RPI on 16700Series logic analysis systems,so that you can reuse existingprograms.The remote programminginterface works through the COMautomation objects, methods,and properties provided forcontrolling the logic analyzerapplication. RPI commands areimplemented as Visual Basicmodules that execute COMautomation commands, translatetheir results, and return propervalues for the RPI. You can use theB4606A advanced customizationenvironment to customize andadd RPI commands.Figure 6. 16800 Series programming overview2816800 Series Interfaces2930Figure 9. 16800 Series back panelFull profile PCI card expansion slotExternal display portParallel portSerial port10/100 Base T LAN 2.0 USB ports (4)Clock inTrigger out Trigger in Keyboard Mouse AC power Figure 8. 16800 Series front panelOn/Off power switch 15 inch built-in color LCD display, Touch Screen available General purpose knob Run/stop keys Touch screen on/off (if ordered)16800 Series Physical CharacteristicsDimensionsPower 16801A 115/230 V, 48-66 Hz, 605 W max 16802A 115/230 V, 48-66 Hz, 605 W max 16803A 115/230 V, 48-66 Hz, 605 W max 16804A 115/230 V, 48-66 Hz, 775 W max 16806A 115/230 V, 48-66 Hz, 775 W max 16821A 115/230 V, 48-66 Hz, 775 W max 16822A 115/230 V, 48-66 Hz, 775 W max 16823A 115/230 V, 48-66 Hz, 775 W max Weight Max net Max shipping 16801A 12.9 kg 19.7 kg (28.5 lbs)(43.5 lbs)16802A 13.2 kg 19.9 kg (28.9 lbs)(43.9 lbs)16803A 13.7 kg 20.5 kg (30.3 lbs)(45.3 lbs)16804A 14.2 kg 21.0 kg (31.3 lbs)(46.3 lbs)16806A 14.6 kg 21.4 kg (32.1 lbs)(47.1 lbs)16821A 14.2 kg 20.9 kg (31.2 lbs)(46.2 lbs)16822A 14.2 kg 21.1 kg (31.6 lbs)(46.6 lbs)16823A14.5 kg 21.3 kg (32.0 lbs)(47.0 lbs)Instrument operating environment Temperature 0˚ C to 50˚ C (32˚ F to 122˚ F)Altitude To 3000 m (10,000 ft)Humidity8 to 80% relative humidity at 40˚ C (104˚ F)Figure 7. 16800 Series exterior dimensionsFigure 10. 16800 Series side view330.32(13.005)Dimensions: mm (inches)28.822(11.347)443.23(17.450)Agilent 1184A TestmobileThe Agilent 1184A testmobile gives you a convenient means of organizing and transporting your logic analyzer and accessories.The testmobile includes the following:•Drawer for accessories(probes, cables, power cords)•Keyboard tray with adjustable tilt and height•Mouse extension on keyboard tray for either right or lefthand operation•on uneven surfaces••Load limits:Total: 136.4 kg (300.0 lb.)Figure 11. Agilent 1184A testmobile cartFigure 12. Agilent 1184A testmobile cart dimensions3132Stationary shelfThis light-duty fixed shelf isdesigned to support 16800 Series logic analyzers. The shelf can be used in all standard Agilent racks. The stationary shelf is mounted securely into placeusing the supplied hardware and is designed to sit at the bottom of the EIA increment. Features of the stationary shelf include:•Snap-in design for easy installation •Smooth edgesRack accessoriesSliding shelfThe sliding shelf provides a flat surface with full product accessibility. It can be used in all Agilent racks to support 16800Series logic analyzers. The shelf and slides are preassembled for easy installation. Features of the sliding shelf include:•Snap-in design for easy installation •Smooth edgesConsider purchasing the steel ballast (C2790AC) to use with the sliding shelf. The ballast provides anti-tip capability when the shelf is extended.Figure 15. Sliding shelf (J1526AC)Figure 14. Stationary shelf (J1520AC)Figure 13. Sliding shelf installed in rackEach 16800 Series portable logicanalyzer comes with one PS/2keyboard, one PS/2 mouse,accessory pouch, power cord and1-year warranty standard.Selecting a logic analyzer to meet your application and budget is as easy as 1, 2, 3333435。
Chapter4翻译
He + N → O + H
14 7 17 8 1 1
1 1
H + Li → 2 He
7 3 4 2
1 1
H + C → N +γ
12 6 13 7
Since the neutron is a neutral (中性的) particle it does not experience electrostatic repulsion (静电排斥) and can readily penetrate (穿透) a target nucleus (靶核). Neutrons are thus especially useful as projectiles to induce reactions. Several examples : The conversion of mercury (汞) into gold, the alchemist (炼金术士)'s dream, is described by因
应率 我们可以进行一套假想的实验来阐明截面的概念。如Fig, 4.2图(a)截面积为1㎝的试管仅有一个靶核。一个入射粒子 被平行于试管的X轴注入,但它的准确位置是不确定的。很 明显碰撞的几率,标为σ以及微分截面,是目标面积比上试 管的面积的值,为1。
In a time of one second, the number of them (projectiles) that pass through the target volume is nv, and since the chance of collision (碰撞) of each with one target atom is σ , the number of collisions is nvNσ. We can thus define the reaction rate (反应率) per unit volume, 一秒钟的时间内,通过给定体积的入射粒子数是nv, 一秒钟的时间内,通过给定体积的入射粒子数是 , 一个靶原子的碰撞几率是σ,碰撞数是nvNσ。我们 一个靶原子的碰撞几率是 ,碰撞数是 。 可以确定每单位体积内的反应率, 可以确定每单位体积内的反应率, R=nvNσ R = nvNσ
Allwinner R8 Datasheet
REVISION HISTORYDECLARATIONTABLE OF CONTENTS5.3. DC Electrical Characteristics2.6.Memory Subsystem&Touch G-SENSORSPI1_CLK UART3_RX42 DDR3_D743 VCC3_DRAM79 AGND80 VRPSDC0_CMD 111PF3PE9 CSI_D6LCD_D10 141PD10PC19 163 VCC4function 0);3)Type: signal directionPC7 Input PC8 InputPE4 Input PE5 InputSignal Name DescriptionOthersVRP Reference voltageV IH High-Level Input Voltage V IL Low-Level Input VoltageFigure 5-1. Power Up Sequence5.5.2.Power Up Reset Sequence RequirementsThe device has a system reset signal to reset the board. When asserted, the following steps give an example of power up reset sequence supported by the R8 device.•AVCC ,VDD_CPU and VCC_DRAM can be powered up simultaneously.•VDD_INT can be powered up after VDD_CPU is powered up, the time difference is T1ms.•VCC can be powered up after VDD_INT is powered up, the time difference is T2ms.Figure 5-2. Power Up Reset Sequence5.5.3.Resume Power Up Sequence from Super Standby ModeTo resume a power up sequence when the device is in Super Standby mode:•VCC_DRAM and AVCC remains powered up always.•VDD_CPU can be powered up firstly.•VDD_INT can be powered up after VDD_CPU is powered up, the time difference is T1ms.•VCC can be powered up after VDD_INT is powered up, the time difference is T2ms.Figure 5-3. Exit Super Standby and Resume Power Up Sequence5.5.4.Power Down Sequence RequirementsTo reduce power consumption,the R8 can be partially powered down.The section lists the power down requirements in each mode.In Super Standby mode,•VCC_DRAM and AVCC must be kept powered up.•VDD_CPU,VDD_INT and VCC are powered down simultaneously.•VCC voltage fall time is more longer than VDD_INT.VDD_CPUVDD_CPU6.PIN ASSIGNMENT6.2.PACKAGE DIMENSIONThe following diagram shows the package dimension of R8.。
MIPS芯片架构说明
MIPS32™ Architecture For Programmers Volume I: Introduction to the MIPS32™ArchitectureDocument Number: MD00082Revision 2.00June 8, 2003MIPS Technologies, Inc.1225 Charleston RoadMountain View, CA 94043-1353Copyright © 2001-2003 MIPS Technologies Inc. All rights reserved.Copyright ©2001-2003 MIPS Technologies, Inc. All rights reserved.Unpublished rights (if any) reserved under the copyright laws of the United States of America and other countries.This document contains information that is proprietary to MIPS Technologies, Inc. ("MIPS Technologies"). Any copying,reproducing,modifying or use of this information(in whole or in part)that is not expressly permitted in writing by MIPS Technologies or an authorized third party is strictly prohibited. At a minimum, this information is protected under unfair competition and copyright laws. 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All rights reserved.Table of ContentsChapter 1 About This Book (1)1.1 Typographical Conventions (1)1.1.1 Italic Text (1)1.1.2 Bold Text (1)1.1.3 Courier Text (1)1.2 UNPREDICTABLE and UNDEFINED (2)1.2.1 UNPREDICTABLE (2)1.2.2 UNDEFINED (2)1.3 Special Symbols in Pseudocode Notation (2)1.4 For More Information (4)Chapter 2 The MIPS Architecture: An Introduction (7)2.1 MIPS32 and MIPS64 Overview (7)2.1.1 Historical Perspective (7)2.1.2 Architectural Evolution (7)2.1.3 Architectural Changes Relative to the MIPS I through MIPS V Architectures (9)2.2 Compliance and Subsetting (9)2.3 Components of the MIPS Architecture (10)2.3.1 MIPS Instruction Set Architecture (ISA) (10)2.3.2 MIPS Privileged Resource Architecture (PRA) (10)2.3.3 MIPS Application Specific Extensions (ASEs) (10)2.3.4 MIPS User Defined Instructions (UDIs) (11)2.4 Architecture Versus Implementation (11)2.5 Relationship between the MIPS32 and MIPS64 Architectures (11)2.6 Instructions, Sorted by ISA (12)2.6.1 List of MIPS32 Instructions (12)2.6.2 List of MIPS64 Instructions (13)2.7 Pipeline Architecture (13)2.7.1 Pipeline Stages and Execution Rates (13)2.7.2 Parallel Pipeline (14)2.7.3 Superpipeline (14)2.7.4 Superscalar Pipeline (14)2.8 Load/Store Architecture (15)2.9 Programming Model (15)2.9.1 CPU Data Formats (16)2.9.2 FPU Data Formats (16)2.9.3 Coprocessors (CP0-CP3) (16)2.9.4 CPU Registers (16)2.9.5 FPU Registers (18)2.9.6 Byte Ordering and Endianness (21)2.9.7 Memory Access Types (25)2.9.8 Implementation-Specific Access Types (26)2.9.9 Cache Coherence Algorithms and Access Types (26)2.9.10 Mixing Access Types (26)Chapter 3 Application Specific Extensions (27)3.1 Description of ASEs (27)3.2 List of Application Specific Instructions (28)3.2.1 The MIPS16e Application Specific Extension to the MIPS32Architecture (28)3.2.2 The MDMX Application Specific Extension to the MIPS64 Architecture (28)3.2.3 The MIPS-3D Application Specific Extension to the MIPS64 Architecture (28)MIPS32™ Architecture For Programmers Volume I, Revision 2.00i Copyright © 2001-2003 MIPS Technologies Inc. All rights reserved.3.2.4 The SmartMIPS Application Specific Extension to the MIPS32 Architecture (28)Chapter 4 Overview of the CPU Instruction Set (29)4.1 CPU Instructions, Grouped By Function (29)4.1.1 CPU Load and Store Instructions (29)4.1.2 Computational Instructions (32)4.1.3 Jump and Branch Instructions (35)4.1.4 Miscellaneous Instructions (37)4.1.5 Coprocessor Instructions (40)4.2 CPU Instruction Formats (41)Chapter 5 Overview of the FPU Instruction Set (43)5.1 Binary Compatibility (43)5.2 Enabling the Floating Point Coprocessor (44)5.3 IEEE Standard 754 (44)5.4 FPU Data Types (44)5.4.1 Floating Point Formats (44)5.4.2 Fixed Point Formats (48)5.5 Floating Point Register Types (48)5.5.1 FPU Register Models (49)5.5.2 Binary Data Transfers (32-Bit and 64-Bit) (49)5.5.3 FPRs and Formatted Operand Layout (50)5.6 Floating Point Control Registers (FCRs) (50)5.6.1 Floating Point Implementation Register (FIR, CP1 Control Register 0) (51)5.6.2 Floating Point Control and Status Register (FCSR, CP1 Control Register 31) (53)5.6.3 Floating Point Condition Codes Register (FCCR, CP1 Control Register 25) (55)5.6.4 Floating Point Exceptions Register (FEXR, CP1 Control Register 26) (56)5.6.5 Floating Point Enables Register (FENR, CP1 Control Register 28) (56)5.7 Formats of Values Used in FP Registers (57)5.8 FPU Exceptions (58)5.8.1 Exception Conditions (59)5.9 FPU Instructions (62)5.9.1 Data Transfer Instructions (62)5.9.2 Arithmetic Instructions (63)5.9.3 Conversion Instructions (65)5.9.4 Formatted Operand-Value Move Instructions (66)5.9.5 Conditional Branch Instructions (67)5.9.6 Miscellaneous Instructions (68)5.10 Valid Operands for FPU Instructions (68)5.11 FPU Instruction Formats (70)5.11.1 Implementation Note (71)Appendix A Instruction Bit Encodings (75)A.1 Instruction Encodings and Instruction Classes (75)A.2 Instruction Bit Encoding Tables (75)A.3 Floating Point Unit Instruction Format Encodings (82)Appendix B Revision History (85)ii MIPS32™ Architecture For Programmers Volume I, Revision 2.00 Copyright © 2001-2003 MIPS Technologies Inc. All rights reserved.Figure 2-1: Relationship between the MIPS32 and MIPS64 Architectures (11)Figure 2-2: One-Deep Single-Completion Instruction Pipeline (13)Figure 2-3: Four-Deep Single-Completion Pipeline (14)Figure 2-4: Four-Deep Superpipeline (14)Figure 2-5: Four-Way Superscalar Pipeline (15)Figure 2-6: CPU Registers (18)Figure 2-7: FPU Registers for a 32-bit FPU (20)Figure 2-8: FPU Registers for a 64-bit FPU if Status FR is 1 (21)Figure 2-9: FPU Registers for a 64-bit FPU if Status FR is 0 (22)Figure 2-10: Big-Endian Byte Ordering (23)Figure 2-11: Little-Endian Byte Ordering (23)Figure 2-12: Big-Endian Data in Doubleword Format (24)Figure 2-13: Little-Endian Data in Doubleword Format (24)Figure 2-14: Big-Endian Misaligned Word Addressing (25)Figure 2-15: Little-Endian Misaligned Word Addressing (25)Figure 3-1: MIPS ISAs and ASEs (27)Figure 3-2: User-Mode MIPS ISAs and Optional ASEs (27)Figure 4-1: Immediate (I-Type) CPU Instruction Format (42)Figure 4-2: Jump (J-Type) CPU Instruction Format (42)Figure 4-3: Register (R-Type) CPU Instruction Format (42)Figure 5-1: Single-Precisions Floating Point Format (S) (45)Figure 5-2: Double-Precisions Floating Point Format (D) (45)Figure 5-3: Paired Single Floating Point Format (PS) (46)Figure 5-4: Word Fixed Point Format (W) (48)Figure 5-5: Longword Fixed Point Format (L) (48)Figure 5-6: FPU Word Load and Move-to Operations (49)Figure 5-7: FPU Doubleword Load and Move-to Operations (50)Figure 5-8: Single Floating Point or Word Fixed Point Operand in an FPR (50)Figure 5-9: Double Floating Point or Longword Fixed Point Operand in an FPR (50)Figure 5-10: Paired-Single Floating Point Operand in an FPR (50)Figure 5-11: FIR Register Format (51)Figure 5-12: FCSR Register Format (53)Figure 5-13: FCCR Register Format (55)Figure 5-14: FEXR Register Format (56)Figure 5-15: FENR Register Format (56)Figure 5-16: Effect of FPU Operations on the Format of Values Held in FPRs (58)Figure 5-17: I-Type (Immediate) FPU Instruction Format (71)Figure 5-18: R-Type (Register) FPU Instruction Format (71)Figure 5-19: Register-Immediate FPU Instruction Format (71)Figure 5-20: Condition Code, Immediate FPU Instruction Format (71)Figure 5-21: Formatted FPU Compare Instruction Format (71)Figure 5-22: FP RegisterMove, Conditional Instruction Format (71)Figure 5-23: Four-Register Formatted Arithmetic FPU Instruction Format (72)Figure 5-24: Register Index FPU Instruction Format (72)Figure 5-25: Register Index Hint FPU Instruction Format (72)Figure 5-26: Condition Code, Register Integer FPU Instruction Format (72)Figure A-1: Sample Bit Encoding Table (76)MIPS32™ Architecture For Programmers Volume I, Revision 2.00iii Copyright © 2001-2003 MIPS Technologies Inc. All rights reserved.Table 1-1: Symbols Used in Instruction Operation Statements (2)Table 2-1: MIPS32 Instructions (12)Table 2-2: MIPS64 Instructions (13)Table 2-3: Unaligned Load and Store Instructions (24)Table 4-1: Load and Store Operations Using Register + Offset Addressing Mode (30)Table 4-2: Aligned CPU Load/Store Instructions (30)Table 4-3: Unaligned CPU Load and Store Instructions (31)Table 4-4: Atomic Update CPU Load and Store Instructions (31)Table 4-5: Coprocessor Load and Store Instructions (31)Table 4-6: FPU Load and Store Instructions Using Register+Register Addressing (32)Table 4-7: ALU Instructions With an Immediate Operand (33)Table 4-8: Three-Operand ALU Instructions (33)Table 4-9: Two-Operand ALU Instructions (34)Table 4-10: Shift Instructions (34)Table 4-11: Multiply/Divide Instructions (35)Table 4-12: Unconditional Jump Within a 256 Megabyte Region (36)Table 4-13: PC-Relative Conditional Branch Instructions Comparing Two Registers (36)Table 4-14: PC-Relative Conditional Branch Instructions Comparing With Zero (37)Table 4-15: Deprecated Branch Likely Instructions (37)Table 4-16: Serialization Instruction (38)Table 4-17: System Call and Breakpoint Instructions (38)Table 4-18: Trap-on-Condition Instructions Comparing Two Registers (38)Table 4-19: Trap-on-Condition Instructions Comparing an Immediate Value (38)Table 4-20: CPU Conditional Move Instructions (39)Table 4-21: Prefetch Instructions (39)Table 4-22: NOP Instructions (40)Table 4-23: Coprocessor Definition and Use in the MIPS Architecture (40)Table 4-24: CPU Instruction Format Fields (42)Table 5-1: Parameters of Floating Point Data Types (45)Table 5-2: Value of Single or Double Floating Point DataType Encoding (46)Table 5-3: Value Supplied When a New Quiet NaN Is Created (47)Table 5-4: FIR Register Field Descriptions (51)Table 5-5: FCSR Register Field Descriptions (53)Table 5-6: Cause, Enable, and Flag Bit Definitions (55)Table 5-7: Rounding Mode Definitions (55)Table 5-8: FCCR Register Field Descriptions (56)Table 5-9: FEXR Register Field Descriptions (56)Table 5-10: FENR Register Field Descriptions (57)Table 5-11: Default Result for IEEE Exceptions Not Trapped Precisely (60)Table 5-12: FPU Data Transfer Instructions (62)Table 5-13: FPU Loads and Stores Using Register+Offset Address Mode (63)Table 5-14: FPU Loads and Using Register+Register Address Mode (63)Table 5-15: FPU Move To and From Instructions (63)Table 5-16: FPU IEEE Arithmetic Operations (64)Table 5-17: FPU-Approximate Arithmetic Operations (64)Table 5-18: FPU Multiply-Accumulate Arithmetic Operations (65)Table 5-19: FPU Conversion Operations Using the FCSR Rounding Mode (65)Table 5-20: FPU Conversion Operations Using a Directed Rounding Mode (65)Table 5-21: FPU Formatted Operand Move Instructions (66)Table 5-22: FPU Conditional Move on True/False Instructions (66)iv MIPS32™ Architecture For Programmers Volume I, Revision 2.00 Copyright © 2001-2003 MIPS Technologies Inc. All rights reserved.Table 5-23: FPU Conditional Move on Zero/Nonzero Instructions (67)Table 5-24: FPU Conditional Branch Instructions (67)Table 5-25: Deprecated FPU Conditional Branch Likely Instructions (67)Table 5-26: CPU Conditional Move on FPU True/False Instructions (68)Table 5-27: FPU Operand Format Field (fmt, fmt3) Encoding (68)Table 5-28: Valid Formats for FPU Operations (69)Table 5-29: FPU Instruction Format Fields (72)Table A-1: Symbols Used in the Instruction Encoding Tables (76)Table A-2: MIPS32 Encoding of the Opcode Field (77)Table A-3: MIPS32 SPECIAL Opcode Encoding of Function Field (78)Table A-4: MIPS32 REGIMM Encoding of rt Field (78)Table A-5: MIPS32 SPECIAL2 Encoding of Function Field (78)Table A-6: MIPS32 SPECIAL3 Encoding of Function Field for Release 2 of the Architecture (78)Table A-7: MIPS32 MOVCI Encoding of tf Bit (79)Table A-8: MIPS32 SRL Encoding of Shift/Rotate (79)Table A-9: MIPS32 SRLV Encoding of Shift/Rotate (79)Table A-10: MIPS32 BSHFL Encoding of sa Field (79)Table A-11: MIPS32 COP0 Encoding of rs Field (79)Table A-12: MIPS32 COP0 Encoding of Function Field When rs=CO (80)Table A-13: MIPS32 COP1 Encoding of rs Field (80)Table A-14: MIPS32 COP1 Encoding of Function Field When rs=S (80)Table A-15: MIPS32 COP1 Encoding of Function Field When rs=D (81)Table A-16: MIPS32 COP1 Encoding of Function Field When rs=W or L (81)Table A-17: MIPS64 COP1 Encoding of Function Field When rs=PS (81)Table A-18: MIPS32 COP1 Encoding of tf Bit When rs=S, D, or PS, Function=MOVCF (81)Table A-19: MIPS32 COP2 Encoding of rs Field (82)Table A-20: MIPS64 COP1X Encoding of Function Field (82)Table A-21: Floating Point Unit Instruction Format Encodings (82)MIPS32™ Architecture For Programmers Volume I, Revision 2.00v Copyright © 2001-2003 MIPS Technologies Inc. All rights reserved.vi MIPS32™ Architecture For Programmers Volume I, Revision 2.00 Copyright © 2001-2003 MIPS Technologies Inc. All rights reserved.Chapter 1About This BookThe MIPS32™ Architecture For Programmers V olume I comes as a multi-volume set.•V olume I describes conventions used throughout the document set, and provides an introduction to the MIPS32™Architecture•V olume II provides detailed descriptions of each instruction in the MIPS32™ instruction set•V olume III describes the MIPS32™Privileged Resource Architecture which defines and governs the behavior of the privileged resources included in a MIPS32™ processor implementation•V olume IV-a describes the MIPS16e™ Application-Specific Extension to the MIPS32™ Architecture•V olume IV-b describes the MDMX™ Application-Specific Extension to the MIPS32™ Architecture and is notapplicable to the MIPS32™ document set•V olume IV-c describes the MIPS-3D™ Application-Specific Extension to the MIPS64™ Architecture and is notapplicable to the MIPS32™ document set•V olume IV-d describes the SmartMIPS™Application-Specific Extension to the MIPS32™ Architecture1.1Typographical ConventionsThis section describes the use of italic,bold and courier fonts in this book.1.1.1Italic Text•is used for emphasis•is used for bits,fields,registers, that are important from a software perspective (for instance, address bits used bysoftware,and programmablefields and registers),and variousfloating point instruction formats,such as S,D,and PS •is used for the memory access types, such as cached and uncached1.1.2Bold Text•represents a term that is being defined•is used for bits andfields that are important from a hardware perspective (for instance,register bits, which are not programmable but accessible only to hardware)•is used for ranges of numbers; the range is indicated by an ellipsis. For instance,5..1indicates numbers 5 through 1•is used to emphasize UNPREDICTABLE and UNDEFINED behavior, as defined below.1.1.3Courier TextCourier fixed-width font is used for text that is displayed on the screen, and for examples of code and instruction pseudocode.MIPS32™ Architecture For Programmers Volume I, Revision 2.001 Copyright © 2001-2003 MIPS Technologies Inc. All rights reserved.Chapter 1 About This Book1.2UNPREDICTABLE and UNDEFINEDThe terms UNPREDICTABLE and UNDEFINED are used throughout this book to describe the behavior of theprocessor in certain cases.UNDEFINED behavior or operations can occur only as the result of executing instructions in a privileged mode (i.e., in Kernel Mode or Debug Mode, or with the CP0 usable bit set in the Status register).Unprivileged software can never cause UNDEFINED behavior or operations. Conversely, both privileged andunprivileged software can cause UNPREDICTABLE results or operations.1.2.1UNPREDICTABLEUNPREDICTABLE results may vary from processor implementation to implementation,instruction to instruction,or as a function of time on the same implementation or instruction. Software can never depend on results that areUNPREDICTABLE.UNPREDICTABLE operations may cause a result to be generated or not.If a result is generated, it is UNPREDICTABLE.UNPREDICTABLE operations may cause arbitrary exceptions.UNPREDICTABLE results or operations have several implementation restrictions:•Implementations of operations generating UNPREDICTABLE results must not depend on any data source(memory or internal state) which is inaccessible in the current processor mode•UNPREDICTABLE operations must not read, write, or modify the contents of memory or internal state which is inaccessible in the current processor mode. For example,UNPREDICTABLE operations executed in user modemust not access memory or internal state that is only accessible in Kernel Mode or Debug Mode or in another process •UNPREDICTABLE operations must not halt or hang the processor1.2.2UNDEFINEDUNDEFINED operations or behavior may vary from processor implementation to implementation, instruction toinstruction, or as a function of time on the same implementation or instruction.UNDEFINED operations or behavior may vary from nothing to creating an environment in which execution can no longer continue.UNDEFINED operations or behavior may cause data loss.UNDEFINED operations or behavior has one implementation restriction:•UNDEFINED operations or behavior must not cause the processor to hang(that is,enter a state from which there is no exit other than powering down the processor).The assertion of any of the reset signals must restore the processor to an operational state1.3Special Symbols in Pseudocode NotationIn this book, algorithmic descriptions of an operation are described as pseudocode in a high-level language notation resembling Pascal. Special symbols used in the pseudocode notation are listed in Table 1-1.Table 1-1 Symbols Used in Instruction Operation StatementsSymbol Meaning←Assignment=, ≠Tests for equality and inequality||Bit string concatenationx y A y-bit string formed by y copies of the single-bit value x2MIPS32™ Architecture For Programmers Volume I, Revision 2.00 Copyright © 2001-2003 MIPS Technologies Inc. All rights reserved.1.3Special Symbols in Pseudocode Notationb#n A constant value n in base b.For instance10#100represents the decimal value100,2#100represents the binary value 100 (decimal 4), and 16#100 represents the hexadecimal value 100 (decimal 256). If the "b#" prefix is omitted, the default base is 10.x y..z Selection of bits y through z of bit string x.Little-endian bit notation(rightmost bit is0)is used.If y is less than z, this expression is an empty (zero length) bit string.+, −2’s complement or floating point arithmetic: addition, subtraction∗, ×2’s complement or floating point multiplication (both used for either)div2’s complement integer divisionmod2’s complement modulo/Floating point division<2’s complement less-than comparison>2’s complement greater-than comparison≤2’s complement less-than or equal comparison≥2’s complement greater-than or equal comparisonnor Bitwise logical NORxor Bitwise logical XORand Bitwise logical ANDor Bitwise logical ORGPRLEN The length in bits (32 or 64) of the CPU general-purpose registersGPR[x]CPU general-purpose register x. The content of GPR[0] is always zero.SGPR[s,x]In Release 2 of the Architecture, multiple copies of the CPU general-purpose registers may be implemented.SGPR[s,x] refers to GPR set s, register x. GPR[x] is a short-hand notation for SGPR[ SRSCtl CSS, x].FPR[x]Floating Point operand register xFCC[CC]Floating Point condition code CC.FCC[0] has the same value as COC[1].FPR[x]Floating Point (Coprocessor unit 1), general register xCPR[z,x,s]Coprocessor unit z, general register x,select sCP2CPR[x]Coprocessor unit 2, general register xCCR[z,x]Coprocessor unit z, control register xCP2CCR[x]Coprocessor unit 2, control register xCOC[z]Coprocessor unit z condition signalXlat[x]Translation of the MIPS16e GPR number x into the corresponding 32-bit GPR numberBigEndianMem Endian mode as configured at chip reset (0→Little-Endian, 1→ Big-Endian). Specifies the endianness of the memory interface(see LoadMemory and StoreMemory pseudocode function descriptions),and the endianness of Kernel and Supervisor mode execution.BigEndianCPU The endianness for load and store instructions (0→ Little-Endian, 1→ Big-Endian). In User mode, this endianness may be switched by setting the RE bit in the Status register.Thus,BigEndianCPU may be computed as (BigEndianMem XOR ReverseEndian).Table 1-1 Symbols Used in Instruction Operation StatementsSymbol MeaningChapter 1 About This Book1.4For More InformationVarious MIPS RISC processor manuals and additional information about MIPS products can be found at the MIPS URL:ReverseEndianSignal to reverse the endianness of load and store instructions.This feature is available in User mode only,and is implemented by setting the RE bit of the Status register.Thus,ReverseEndian may be computed as (SR RE and User mode).LLbitBit of virtual state used to specify operation for instructions that provide atomic read-modify-write.LLbit is set when a linked load occurs; it is tested and cleared by the conditional store. It is cleared, during other CPU operation,when a store to the location would no longer be atomic.In particular,it is cleared by exception return instructions.I :,I+n :,I-n :This occurs as a prefix to Operation description lines and functions as a label. It indicates the instruction time during which the pseudocode appears to “execute.” Unless otherwise indicated, all effects of the currentinstruction appear to occur during the instruction time of the current instruction.No label is equivalent to a time label of I . Sometimes effects of an instruction appear to occur either earlier or later — that is, during theinstruction time of another instruction.When this happens,the instruction operation is written in sections labeled with the instruction time,relative to the current instruction I ,in which the effect of that pseudocode appears to occur.For example,an instruction may have a result that is not available until after the next instruction.Such an instruction has the portion of the instruction operation description that writes the result register in a section labeled I +1.The effect of pseudocode statements for the current instruction labelled I +1appears to occur “at the same time”as the effect of pseudocode statements labeled I for the following instruction.Within one pseudocode sequence,the effects of the statements take place in order. However, between sequences of statements for differentinstructions that occur “at the same time,” there is no defined order. Programs must not depend on a particular order of evaluation between such sections.PCThe Program Counter value.During the instruction time of an instruction,this is the address of the instruction word. The address of the instruction that occurs during the next instruction time is determined by assigning a value to PC during an instruction time. If no value is assigned to PC during an instruction time by anypseudocode statement,it is automatically incremented by either 2(in the case of a 16-bit MIPS16e instruction)or 4before the next instruction time.A taken branch assigns the target address to the PC during the instruction time of the instruction in the branch delay slot.PABITSThe number of physical address bits implemented is represented by the symbol PABITS.As such,if 36physical address bits were implemented, the size of the physical address space would be 2PABITS = 236 bytes.FP32RegistersModeIndicates whether the FPU has 32-bit or 64-bit floating point registers (FPRs).In MIPS32,the FPU has 3232-bit FPRs in which 64-bit data types are stored in even-odd pairs of FPRs.In MIPS64,the FPU has 3264-bit FPRs in which 64-bit data types are stored in any FPR.In MIPS32implementations,FP32RegistersMode is always a 0.MIPS64implementations have a compatibility mode in which the processor references the FPRs as if it were a MIPS32 implementation. In such a caseFP32RegisterMode is computed from the FR bit in the Status register.If this bit is a 0,the processor operates as if it had 32 32-bit FPRs. If this bit is a 1, the processor operates with 32 64-bit FPRs.The value of FP32RegistersMode is computed from the FR bit in the Status register.InstructionInBranchDelaySlotIndicates whether the instruction at the Program Counter address was executed in the delay slot of a branch or jump. This condition reflects the dynamic state of the instruction, not the static state. That is, the value is false if a branch or jump occurs to an instruction whose PC immediately follows a branch or jump, but which is not executed in the delay slot of a branch or jump.SignalException(exce ption, argument)Causes an exception to be signaled, using the exception parameter as the type of exception and the argument parameter as an exception-specific argument). Control does not return from this pseudocode function - the exception is signaled at the point of the call.Table 1-1 Symbols Used in Instruction Operation StatementsSymbolMeaning。
斑马技术公司DS8108数字扫描仪产品参考指南说明书
电子信息类专业英语翻译
1.This electron beam sweeps across each line at a uniform rate,then flies back to scan another line directly below the previous one and so on,until the horizontal lines into which it is desired to break or split the picture have been scannedin the desired sequence.电子束以均匀的速率扫描每一行,然后飞速返回去扫描下一行,直到把被扫描的图像按所希望的顺序分割成行。
2.The technical possibilities could well exist,therefore,of nation-wide integrated transmission network of high capacity,controlled by computers,interconnected globally by satellite and submarine cable,providing speedy and reliable communications throughout the word因此,在技术上完全可能实现全国性的集成发送网络。
这种网络容量大,由计算机控制,并能通过卫星和海底电缆实现全球互联,提供世界范围的高速、可靠的通信。
3.Transit time is the primary factor which limits the ability of a transistor to operate at high frequency.渡越时间是限制晶体管高频工作能力的主要因素4.The intensity of sound is inversely proportional to the square of the distance measured from the source of the sound.声强与到声源的距离的平方成反比。
运筹学作业d 文档
注:没有选项的题是判断题,每一章的前几道都是判断题Chapter 11. Managers do not need to know the mathematical theory behind the techniques of management science in order to lead management science teams.2. Management scientists are responsible for making the managerial decisions for an organization.3. Once management makes its decisions, the management science team typically continues to work to implement the new plan.4. At the break-even point, the fixed cost equals the variable cost.5. Sensitivity analysis is used to check the effect on the recommendations of a model if the estimates turn out to be wrong.6. Enlightened future managers do not need to know which of the following?A. How the models of management science are solved.B. When management science can and cannot be applied.C. How to apply the major techniques of management science.D. How to interpret the results of a management science study.E. None of the above.7. Which of the following is not a component of a mathematical model for decision making?A. Decision variables.B. A spreadsheet.C. Constraints.D. Parameters.E. All of the above.8. Which of the following is not a step taken in a typical management science study?A. Define the problem and gather data.B. Formulate a model.C. Apply the model and develop recommendations.D. Help to implement the recommendation.E. All of the above are typical steps in a management science study.9. Which of the following is true at the break-even point?A. The fixed cost equals the variable cost.B. The production quantity equals the sales forecast.C. The company will neither make nor lose money on the product.D. The profit equals the cost.E. None of the above.10. A constraint in a mathematical model isA. a variable representing the decision to be made.B. an inequality or equation that restricts the values of the variables.C. a measure of the performance of the model.D. the sales forecast.E. none of the above.Chapter 21. Linear programming problems may have only one goal or objective specified.2. A feasible solution is one that satisfies at least one of the constraints of a linear programming problem.3. The cell containing the measure of performance is referred to as a changing cell.4. A linear programming problem can have only one optimal solution.5. When solving a maximization problem graphically, it is generally the goal to move the objective function line in, toward the origin, as far as possible.6. In a linear programming spreadsheet model, the output cells can typically be expressed as a SUMPRODUCT function.7. Changing only the right-hand side of a constraint creates parallel constraint boundary lines.8. The Assume Nonnegative option assures that the target cell will remain nonnegative.9. Which of the following is a component of a linear programming model?A. Constraints.B. Decision variables.C. Parameters.D. An objective.E. All of the above.10. Which of the following are not types of cells in a linear programming spreadsheet model?A. Changing cellsB. Target cellC. Output cellsD. Input cellsE. Data cells11. For the products x and y, which of the following could be a linear programming objective function?A. C = x + 2y.B. C = x+ 2xy.C. C = x - 2(y-squared).D. C = x + 2x/y.E. All of the above.12. Which of the following is not a step in the graphical method:A. Draw the constraint boundary line for each functional constraint.B. Find the feasible region.C. Determine the slope of one objective function line.D. Find the optimal solution using a straight-edge.E. All of the above are steps in the graphical method.13. Given the following 2 constraints, which solution is a feasible solution for a maximization problem?A. (X1 , X2 ) = (1, 5).B. (X1 , X2 ) = (4, 1).C. (X1 , X2 ) = (4, 0).D. (X1 , X2 ) = (2, 1).E. (X1 , X2 ) = (2, 4).14. What is the cost of the optimal solution for the following problem?A. 0.B. 3.C. 15.D. 18.E. 21.15. A local bagel shop produces bagels (B) and croissants (C). Each bagel requires 6 ounces of flour, 1 gram of yeast, and 2 tablespoons of sugar. A croissant requires 3 ounces of flour, 1 gram of yeast, and 4 tablespoons of sugar. The company has 6,600 ounces of flour, 1,400 grams of yeast, and 4,800 tablespoons of sugar available for today's baking. Bagel profits are 20 cents each and croissant profits are 30 cents each. What is the objective function?A. 2B + 4C <= 4,800.B. (B, C) = (0, 1400).C. P = 0.2B + 0.3C.D. $340.E. None of the above.Chapter 31. There is only one correct way to set up a spreadsheet model.2. In the Everglade Golden Years Company problem, the long-term loan had a lower interest rate than the short-term loan.3. When sketching out a spreadsheet, all of the equations should be entered in the sketch.4. Data should be repeated on the spreadsheet wherever it is needed.5. Numbers should be entered directly into formulas.6. Range names can make equations and the Solver dialogue box easier to read and interpret.7. Shading of cells in the spreadsheet should be avoided.8. The toggle alternates between showing equations and showing values in the cells of the spreadsheet.9. Powerful Excel functions should be used to keep the spreadsheet as concise as possible.10. Using absolute and relative references appropriately makes it easy to expand a model to full-size.11. Which of the following is not a major step in the process of modeling with spreadsheets?A. PlanB. BuildC. TestD. AnalyzeE. All are major steps in the process of modeling with spreadsheets.12. Which of the following are useful steps in the planning stage?A. Visualize where you want to finishB. Do some calculations by handC. Sketch out a spreadsheetD. Sensitivity analysisE. All are useful steps in the planning stage.13. Each constraint should be entered into how many cells on the spreadsheet?A. 1B. 2C. 3D. 4E. 514. Which of the following is not useful for debugging a spreadsheet?A. The auditing toolbar.B. The toggle.C. Trying different values in the changing cells for which you know the solution.D. A and C only.E. All are useful for debugging a spreadsheet.15. Which element of the spreadsheet model should be entered first?A. The data.B. The output cells.C. The target cell.D. The changing cells.E. None of the above.Chapter 41. When formulating a linear programming model on a spreadsheet, the constraints are located in the data cells.2. A mathematical model will be an approximation of the real problem.3. Linear programming must have integer solutions.4. Strict inequalities (i.e., < or >) are permitted in linear programming formulations.5. Once a linear programming problem has been formulated, it is common to make major adjustments to it.6. Resource-allocation problems have constraints for each limited resource.7. A resource constraint has a >= sign in a linear programming model.8. Distribution-network problems typically have mostly <= constraints.9. Which of the following is not a category of linear programming problems?A. Resource-allocation problems.B. Cost-benefit-tradeoff problems.C. Distribution-network problems.D. B and C.E. All of the above are categories of linear programming problems.10. A linear programming model does not contain which of the following components?A. Data.B. Decisions.C. Constraints.D. Measure of performance.E. A spreadsheet.11. Which of the following may not be in a linear programming formulation?A. <=.B. >.C. =.D. A. and C. only.E. All of the above.12. Distribution-network problems have the following type of constraints:A. >=.B. <=.C. >.D. <.E. None of the above.13. Resource-allocation problems typically have which of the following type of constraints:A. >=.B. <=.C. =.D. None of the above.E. All of the above.14. Cost-benefit tradeoff problems typically have which of the following type of constraints:A. >=.B. <=.C. =.D. None of the above.E. All of the above.15. Mixed problems may not have which of the following type of constraints:A. >=.B. <=.C. =.D. All of the above.E. None of the above.Chapter 61. Transportation problems are concerned with distributing commodities from sources to destinations in such a way as to maximize the total amount shipped.2. Transportation problems always have integer solutions if the supplies and demands are all integer.3. The Hungarian Method is an algorithm used to solve assignment problems.4. When demand and supply are not equal in a transportation problem then the problem can be reformulated and solved.5. It is possible to adjust the transportation simplex method to maximize profit instead of minimize cost.6. Which of the following is needed to use the transportation model?A. Capacity of the sources.B. Demand of the destinations.C. Unit shipping costs.D. All of the above.E. None of the above.7. Which of the following is not an assumption or requirement of a transportation problem?A. I and IVB. II and IIIC. I, II and IVD. I and IIIE. I, II, III, and IV8. Which of the following can be modeled as variants of the standard transportation problem?A. The sum of the supplies exceeds the sum of demands.B. A destination has a minimum and maximum demand.C. Certain source-destination combinations cannot be used for distributing units.D. A. and B. only.E. All can be modeled as a variation of the transportation problem.9. An assignment problem:A. will always have an integer solution.B. has all supplies and demands equal to 0.C. always has the demand greater than the supply.D. All of the above.E. None of the above.10. Which of the following is an assumption of assignment problems?A. The number of assignees and the number of tasks are the sameB. The objective is to minimize the number of assignments not made.C. Each task is to be performed by exactly one assignee.D. A. and C. only.E. None of the aboveChapter 71. Each node in a minimum cost flow problem where the net amount of flow generated is a fixed positive number is a supply node.2. If the SUMIF function is used in a network optimization models, it will be nonlinear.3. In a maximum flow problem, the source and sink do not have fixed supplies and demands.4. A shortest path problem may have multiple destinations.5. The number of links in a spanning tree is always the same as the number of nodes.6. The network simplex is a streamlined version of the simplex method.7. Which of the following is not a special type of linear programming problem?A. I and IV.B. I, II, and III.C. II, III, and IV.D. IV only.E. None of the above.8. Which of the following will have positive net outflow in a minimum cost flow problem?A. Supply nodes.B. Transshipment nodes.C. Demand nodes.D. All of the above.E. None of the above.9. Which of the following is not an application of a shortest path problem?A. I and II onlyB. I, II, and III only.C. II onlyD. I, II, III, and IVE. I, III, and IV only.10. If there are 8 nodes in a minimum spanning tree problem then how many links will there be in the solution?A. 6.B. 7.C. 8.D. We cannot tell how many links there will be until it has been solved.E. The total cost will be 7.Chapter 81. In an Activity-On-Arc project network, the nodes are used to separate an activity from each of its immediate predecessors.2. If two paths are tied for the longest duration, the one with the most activities would be considered to be the critical path.3. The slack of an activity is the difference between the latest finish and the latest start times.4. When calculating the probability that a project will finish by a certain time, the approximation that is obtained is usually higher than the true probability.5. The latest finish time for an activity is:A. based on the length of the critical path.B. determined by the maximum of the earliest finish times of its immediate predecessors.C. determined by the maximum of the earliest finish times of its immediate successors.D. the same as the latest start time of its immediate predecessor.E. None of the above.6. Activity C has an early start time of 7, an early finish time of 12, a latest start time of 13, and a latest finish time of 18. Its slack is:A. 0.B. 1.C. 4.D. 6.E. 9.7. Which of the following is a benefit of PERT/CPM?A. It provides an estimate of how long a project will take.B. It allows an activity to overlap with its immediate predecessors.C. It addresses the important issue of how to allocate limited resources.D. A. and C. only.E. All of the above.8. An activity has an optimistic time estimate of four days, a most likely time estimate of eight days, and a pessimistic time estimate of fifteen days. The expected duration of this activity is:A. 7.0 days.B. 7.5 days.C. 8.0 days.D. 8.5 days.E. 10.0 days.9. Which of the following is not a way of crashing an activity?A. Using overtime.B. Hiring more workers.C. Using specialized equipment.D. A. and C.E. All of the above are ways of crashing an activity.10. PERT/Cost does not:A. find the penalty costs if a project is not completed on time.B. compare the actual budget with the planned budget.C. show management where to focus attention during the project.D. A. and B. only.E. B. and C. only.Chapter 91. In an integer programming problem, all of the decision variables are not necessarily required to be integer values.2. Solving the LP relaxation of an integer programming problem and rounding the solution will always find the optimal solution.3. Binary integer programming problems are those where all the decision variables are restricted to integer values.4. Variables whose only possible values are 0 and 1 are called binary variables.5. A problems where all the variables are binary variables is called a mixed BIP problem.6. If choosing one alternative from a group excludes choosing all of the others then these alternatives are called complimentary.7. The constraint x1 +x2 +x3 <= 1 in a BIP represents mutually exclusive alternatives.8. Solving the LP relaxation of an integer programming problem and rounding the solution will find a solution that may not be:A. feasible.B. optimal.C. integer.D. A. and B.E. All of the above.9. Binary integer programming problems can answer which types of questions?A. How much of a product should be produced?B. Should an investment be made?C. Should a plant be located at a particular location?D. All of the above.E. B. and C. only.10. Binary variables can have the following values:A. 0.B. 1.C. any integer value.D. A. and B. only.E. All of the above.11. In a BIP problem with 3 mutually exclusive alternatives, A, B, and C , the following constraint needs to be added to the formulation if two alternatives must be chosen:A. A + B + C <= 2.B. A + B + C = 2.C. A - B - C <= 2.D. A + B + C <= 1.E. None of the above.12. In a BIP problem, 1 corresponds to a yes decision and 0 to a no decision. If project S can be undertaken only if project T is also undertaken then the following constraint needs to be added to the formulation:A. S + T <= 1.B. S + T = 1.C. S <= T.D. T <= S.E. None of the above.13. In a BIP problem, 1 corresponds to a yes decision and 0 to a no decision. If there are 3 projects under consideration (A, B, and C) and at most 2 can be chosen then the following constraint needs to be added to the formulation:A. A + B + C <= 3.B. A + B + C <= 2.C. A + B + C >= 2.D. A + B + C = 2.E. None of the above.14. Auxiliary binary variables can be used to deal with:A. set-up costs for initiating production.B. mutually exclusive products.C. either-or constraints.D. All of the above.E. None of the above.Chapter 101. If the slope of a curve on a profit graph never increases but sometimes decreases as the level of the activity increases, then it is said to have increasing marginal returns.2. The Solver Table can be used to try a variety of starting points in a nonlinear programming problem.3. Separable programming requires that the objective function be piecewise linear.4. The Evolutionary Solver uses an algorithm that is sometimes called a genetic algorithm.5. Evolutionary Solver is a good choice for problems with many constraints.6. The Evolutionary Solver requires that the constraints all be linear.7. Problems with increasing marginal returns are generally easier for Solver to solve than problems with decreasing marginal returns.8. A nonlinear programming problem will have how many local maxima?A. 0B. 1C. 2D. 3E. It can have any number of local maxima.9. A linear function may not contain which of the following?A. A term that contains a single variable with an exponent of 1.B. A term that contains a single variable with an exponent of 2.C. A term that is a constant times the product of two variables.D. B. and C. only.E. All of the above.10. Which of the following Excel functions are linear (assuming changing cells are in C1:C6 and data cells are in D1:D6):A. I only.B. I and II.C. I and III.D. II and IV.E. III and IV.11. Which of the following Excel functions are linear (assuming changing cells are in C1:C6 and data cells are in D1:D6):A. I only.B. I and II.C. II and III.D. I and IV.E. IV only.12. Which of the following is an example of a nonlinear function?A. P= 5 X1+ 7 X2 - 2 (X2-squared).B. P= 8 X1 - 4 X2.C. P= X1 + 6 X2 + 3 X1 X2.D. A. and C. only.E. All of the above.13. The requirement that each term in the objective function only contains a single variable is referred to as:A. the proportionality assumption.B. the divisibility assumption.C. the additivity assumption.D. a nonlinear function.E. None of the above.Chapter 111. The overall objective for a goal programming problem is to determine the most important objective in the problem.2. Goal programming provides two alternative ways of formulating problems with multiple goals: preemptive and weighted goal programming.3. Preemptive goal programming is an appropriate technique when all of the goals are fairly equal in importance.4. In preemptive goal programming it is assumed that there is a distinct order of importance for all goals, and that no goals are of equal importance.5. Preemptive goal programming involves solving a single linear programming model.6. Weighted goal programming involves solving a single linear programming model.7. Goal programming can handle problems with how many different objectives or goals?A. 1.B. 2.C. 3.D. 4.E. Any number of objectives or goals.8. Which of the following are included as changing cells in a goal programming formulation?A. The levels of the various activities.B. The amount over each goal.C. The amount under each goal.D. B. and C. only.E. All of the above are changing cells.9. In weighted goal programming the objective is toA. Maximize profit.B. Minimize cost.C. Achieve the most important goal.D. Minimize a weighted sum of deviations from the various goals.E. Minimize the amount under each goal.10. In preemptive goal programming, the most important thing is toA. Achieve the most important goal.B. Come close to achieving all the goals.C. Ignore the least important goal.D. A. and C.E. All of the above.Chapter 121. Prior probabilities refer to the relative likelihood of past events.2. Bayes' decision rule says to choose the alternative with the largest possible payoff.3. The EVPI indicates how much the payoff will be with perfect information.4. A risk seeker has an increasing marginal utility for money.5. The exponential utility function assumes a variable aversion to risk.6. The maximax criterion is appropriate for the eternal optimist.7. The expected payoff is the payoff that is most likely to occur.8. In a decision tree, the expected payoff of a particular event node is equal to the SUMPRODUCT of the probabilities and expected payoffs of each branch.9. Sensitivity analysis of a decision tree requires the use of Solver Table.10. If C > EVPI then it is not worthwhile to obtain more information.11. Which of the following statements is correct when making decisions?A. The sum of the state of nature probabilities must be 1.B. Every probability must be greater than or equal to 0.C. All probabilities are assumed to be equal.D. A. and B. only.E. All of the above.12. Given the following information what is the maximum likelihood strategy?A. A.B. B.C. C.D. D.E. E.13. Given the following information what is the Bayes' decision rule strategy?A. A.B. B.C. C.D. D.E. E.14. Given the following information what is the expected value of perfect information?A. 4.5.B. 9.C. 40.5.D. 49.5.E. 60.15. Which of the following can be used to do sensitivity analysis with decision trees?A. Trial and error.B. A Data Table.C. SensIt.D. A. and C.E. All of the above.答案:chapter 1Chapter 1 ABABA ABECBChapter 2 ABBBB AABED AEDDCChapter 3 BABBB ABABA EDCEAChapter 4 BABBA ABBEE BEBAEChapter 6 BAAAA DBEADChapter 7 ABABB BDACBChapter 8 ABBAE DADEAChapter 9 ABBAB BADED BCDEChapter 10 BABAB BBEDC EDCChapter 11 BABBB AEEDAChapter 12 BBBAB ABABA DCCBE。
UPC功能说明书
Standard Features:•Advanced Linear Amplifiers Provide Very Low Voltage Distortion, no Switching Noise, Fast Voltage and Current Slew Rates, Exceptionally Low Output Impedance and High Peak Current Capability• 1, 2, or 3 Phase Output Form selectable from front panel or bus command•20 to 5,000 Hz. Full Power Bandwidth Operation – 5Hz to 50KHz small signal bandwidth, 3dB at 10% of full voltage• Precision Voltage Programming – 0.05% with Continuous Self-Calibration (CSC) engaged • True-RMS Metering of Volts, Amps, and Power • GPIB (IEEE-488.2) or RS-232 Interface • Waveform Library – Arbitrary Waveform Generator• Up to 99 Programs with Associated Transients for Static and Dynamic Test Applications •UPC Studio Software SuiteAvailable Options:• Programmable Output Impedance• Harmonic Analysis and Waveform Synthesis • Peak Inrush Capture and Waveform Analysis (Available on models with UPC3 controller)•UPC Test Manager SoftwareUPC Manager Software SuiteMaster the Power of the Wave!UPC Manager Software gives you the tools neces-sary to quickly and easily operate your AC Power Source. With our graphical interface control all areas of your AC Power Source testing with simple presets, user prompts, test sequences, test plans and custom reports.Model 312AMXFREQUENCY CONVERSION R & D MANUFACTURING AEROSPACE MILITARYCUSTOM1, 2, or 1,200VA 20-5,000 HzModel 312AMXAs a member of Pacific Power’s AMX-Series popular family of high performance Linear AC Power Sources, the 312AMX offers the same low output voltage noise and distortion, ease of installation, and high AC waveform fidelity as found in all of Pacific Power’s Linear AC Power Sources. Control and operational features provide a high degree of versatility and ease of use for applications ranging from simple,manually controlled frequency conversion to harmonic testing and sophisticated programmable transient simulation.AC TEST POWERAll 312AMX models are equipped with a powerful micro-controller with the ability to operate as a fully integrated test system. This enables a variety of power conditions and transients to be applied to the device under test while metering and analyzing all output performance parameters. For higher power requirements, refer to the AMX & ASX series catalog.FREQUENCY/ VOLTAGE CONVERSIONThe 312AMX is an excellent source of stable AC Voltage over the frequency range of 20 to 5,000 Hz when using the high-end UPC-32 controller. Also available in 1,200 Hz maximum output frequency when using UPC3 or Manual controller. The output frequency is quartz-crystal stabilized. Output voltages up to 300V L-L in split phase mode and 260V L-L in three phase mode are available on the 312AMX model.PHASE CONVERSIONWith the ability to provide either single or two phase output, the 312AMX is a good choice to convert one-phase line voltage into precisely controlled split (two-phase) or three-phase output power.UPC SERIES CONTROLLERThree controller models are available in both manual and programmable control version. All controllers provide manual operation from the front panel. Programmable Controllers may be operated from the front panel or from a remote interface via RS 232 or GPIB.The Leader in AC Power TechnologyAn early pioneer in the development solid-state power conversion equipment, Pacific Power Source continues to develop, manufacture, and market both linear and high-performance PWM AC Power Sources. Pacific Power Source’s reputation as a market and technology leader is best demonstrated by its continuing investments in both research and development and world-wide customer support. With corporate owned offices in the United States, France, the United Kingdom, and China, local personalized support is always available.1Ø42Ø43Ø40-150V L-N 0-300V L-L0-150V L-N / 0-260V L-LNOTES:1. Rated output power is based on a combination of nominal output voltage, rated current and load power factor. Values stated represent the maximum capabilities of a given model (maximum power in split phase (Form2) direct coupled mode is 800VA). Consult factory for assistance in determining specific unit capabilities as they might apply to your application.2. Unit is operable as single phase with dual range capability or 3 phase. Output voltage range and 1/2/3 conversions are selected by front panel or bus commands.3. Vmax is output voltage with nominal input and full rated load applied.4. Available current will vary with output voltage and power factor. Current shown is per phase.Output RatingsThermal and Power Factor Rating CurvesAMX Power Source Specifications (PF = 1.0, V out > 25% F.S.)Input Power Requirements (47-63 Hz)312AMXOutput Frequency Line Regulation Load Regulation Ripple and Noise OUTPUT VOLTAGE-AC VOLTS RMSShort term overloads to 150% are permitted. Operating time before thermal shutdown or circuit breaker trip varies from sec-onds to several minutes depending upon line and temperature conditions.THERMAL RATING -AC CURRENT RMSShort tem overloads to 150% of rated current are permitted.Operating time before thermal shutdown or circuit breaker trip varies from seconds to several minutes depending upon line and temperature conditions.Rated Continuous Load Current as a Function of Ambient Temperature and Power Factor and Output Voltage at Nominal Input Line.The UPC Controlleris a highly versatile one, two, or threephase oscillator/signal generator designed to control any ofPacific Power’s AC Power Sources. Three controller models,UPC-3M, UPC-3, or UPC-32 are offered. To use the full 5KHz power bandwidth of the 312AMX, the UPC-32 controller isrequired.Controller ModelsOutput Control SpecificationsTotal Control, Metering, and Analysis of AC Power- Simple, Intuitive OperationWaveform ControlExternal Inputs/OutputsOutput MeteringUsing the front panel keyboard and display , all controllermodels provide for selection of power source output mode, cou-pling, voltage, and frequency. Selecting the correct UPC controller for a given application varies with your test requirement, desired features, and price.Both the UPC-3 and UPC-32 Controllers are available witheither RS-232 or GPIB remote interface. Commands are structured in accordance with SCPI (Standard Commands for Programmable Instruments).© 2012 Pacific Power Source, Inc. Subject to change without notice. #DS312AMX101217692 Fitch, Irvine, CA 92614 USAPhone: +1 949.251.1800 Fax: +1 949.756.0756 T oll Free: 800.854.2433E-mail:**********************19" (483mm)Ordering InformationAvailable Models312AMX-UPC3M312AMX-UPC3312AMX-UPC32 General/EnvironmentalMechanical SpecificationsSoftware/Firmware OptionsProtection and SafetyOrder Example312AMX-UPC32, V IN : 120VAC • 1,200VA, 3-Phase, AC Power Source with UPC-32 programmable controller.• Standard GPIB Interface•120VAC, 1 Phase Input VoltageTypical Delivery Items• AC Power Source• English Manuals (AC Source and Controller)• UPC Studio Software - (Download)• UPC Interactive LabVIEW TM Libraries (Download)• Compliance Certificate with Test data •CE Conformity Document (CE Models)。
3GPP协议-36521-1-e40_s00-s05
3GPP TS 36.521-1 V14.4.0 (2017-09)Technical Specification3rd Generation Partnership Project; Technical Specification Group Radio Access Network; Evolved Universal Terrestrial Radio Access (E-UTRA);User Equipment (UE) conformance specification;Radio transmission and reception;Part 1: Conformance Testing(Release 14)The present document has been developed within the 3rd Generation Partnership Project (3GPP TM) and may be further elaborated for the purposes of 3GPP.KeywordsUMTS LTE3GPPPostal address3GPP support office address650 Route des Lucioles - Sophia AntipolisValbonne - FRANCETel.: +33 4 92 94 42 00 Fax: +33 4 93 65 47 16InternetCopyright NotificationNo part may be reproduced except as authorized by written permission.The copyright and the foregoing restriction extend to reproduction in all media.© 2017, 3GPP Organizational Partners (ARIB, ATIS, CCSA, ETSI, TSDSI, TTA, TTC).All rights reserved.UMTS™ is a Trade Mark of ETSI registered for the benefit of its members3GPP™ is a Trade Mark of ETSI registered for the benefit of its Members and of the 3GPP Organizational Partners LTE™ is a Trade Mark of ETSI registered for the benefit of its Members a nd of the 3GPP Organizational Partners GSM® and the GSM logo are registered and owned by the GSM AssociationContentsForeword (92)Introduction (92)1Scope (93)2References (94)3Definitions, symbols and abbreviations (96)3.1Definitions (96)3.2Symbols (98)3.3Abbreviations (100)4General (103)4.1Categorization of test requirements in CA, UL-MIMO, ProSe, Dual Connectivity, UE category 0, UEcategory M1, UE category 1bis, UE category NB1 and V2X Communication (104)4.2RF requirements in later releases (105)5Frequency bands and channel arrangement (106)5.1General (106)5.2Operating bands (106)5.2A Operating bands for CA (108)5.2B Operating bands for UL-MIMO (116)5.2C Operating bands for Dual Connectivity (116)5.2D Operating bands for ProSe (117)5.2E Operating bands for UE category 0 and UE category M1 (118)5.2F Operating bands for UE category NB1 (118)5.2G Operating bands for V2X Communication (118)5.3TX–RX frequency separation (119)5.3A TX–RX frequency separation for CA (120)5.4Channel arrangement (120)5.4.1Channel spacing (120)5.4.1A Channel spacing for CA (121)5.4.1F Channel spacing for UE category NB1 (121)5.4.2Channel bandwidth (121)5.4.2.1Channel bandwidths per operating band (122)5.4.2A Channel bandwidth for CA (124)5.4.2A.1Channel bandwidths per operating band for CA (126)5.4.2B Channel bandwidth for UL-MIMO (171)5.4.2B.1Channel bandwidths per operating band for UL- MIMO (171)5.4.2C Channel bandwidth for Dual Connectivity (171)5.4.2D Channel bandwidth for ProSe (171)5.4.2D.1Channel bandwidths per operating band for ProSe (171)5.4.2F Channel bandwidth for category NB1 (172)5.4.2G Channel bandwidth for V2X Communication (173)5.4.2G.1Channel bandwidths per operating band for V2X Communication (173)5.4.3Channel raster (174)5.4.3A Channel raster for CA (175)5.4.3F Channel raster for UE category NB1 (175)5.4.4Carrier frequency and EARFCN (175)5.4.4F Carrier frequency and EARFCN for category NB1 (177)6Transmitter Characteristics (179)6.1General (179)6.2Transmit power (180)6.2.1Void (180)6.2.2UE Maximum Output Power (180)6.2.2.1Test purpose (180)6.2.2.4Test description (182)6.2.2.4.1Initial condition (182)6.2.2.4.2Test procedure (183)6.2.2.4.3Message contents (183)6.2.2.5Test requirements (183)6.2.2_1Maximum Output Power for HPUE (185)6.2.2_1.1Test purpose (185)6.2.2_1.2Test applicability (185)6.2.2_1.3Minimum conformance requirements (185)6.2.2_1.4Test description (185)6.2.2_1.5Test requirements (186)6.2.2A UE Maximum Output Power for CA (187)6.2.2A.0Minimum conformance requirements (187)6.2.2A.1UE Maximum Output Power for CA (intra-band contiguous DL CA and UL CA) (189)6.2.2A.1.1Test purpose (189)6.2.2A.1.2Test applicability (189)6.2.2A.1.3Minimum conformance requirements (189)6.2.2A.1.4Test description (189)6.2.2A.1.5Test Requirements (191)6.2.2A.2UE Maximum Output Power for CA (inter-band DL CA and UL CA) (192)6.2.2A.2.1Test purpose (192)6.2.2A.2.2Test applicability (192)6.2.2A.2.3Minimum conformance requirements (192)6.2.2A.2.4Test description (192)6.2.2A.2.5Test Requirements (194)6.2.2A.3UE Maximum Output Power for CA (intra-band non-contiguous DL CA and UL CA) (196)6.2.2A.4.1UE Maximum Output Power for CA (intra-band contiguous 3DL CA and 3UL CA) (196)6.2.2A.4.1.1Test purpose (196)6.2.2A.4.1.2Test applicability (196)6.2.2A.4.1.3Minimum conformance requirements (196)6.2.2A.4.1.4Test description (196)6.2.2A.4.1.5Test Requirements (198)6.2.2A.4.2UE Maximum Output Power for CA (inter-band 3DL CA and 3UL CA) (198)6.2.2A.4.2.1Test purpose (199)6.2.2A.4.2.2Test applicability (199)6.2.2A.4.2.3Minimum conformance requirements (199)6.2.2A.4.2.4Test description (199)6.2.2A.4.2.5Test Requirements (201)6.2.2B UE Maximum Output Power for UL-MIMO (201)6.2.2B.1Test purpose (201)6.2.2B.2Test applicability (202)6.2.2B.3Minimum conformance requirements (202)6.2.2B.4Test description (204)6.2.2B.4.1Initial condition (204)6.2.2B.4.2Test procedure (205)6.2.2B.4.3Message contents (205)6.2.2B.5Test requirements (205)6.2.2B_1HPUE Maximum Output Power for UL-MIMO (207)6.2.2B_1.1Test purpose (207)6.2.2B_1.2Test applicability (207)6.2.2B_1.3Minimum conformance requirements (207)6.2.2B_1.4Test description (207)6.2.2B_1.5Test requirements (208)6.2.2C 2096.2.2D UE Maximum Output Power for ProSe (209)6.2.2D.0Minimum conformance requirements (209)6.2.2D.1UE Maximum Output Power for ProSe Discovery (209)6.2.2D.1.1Test purpose (209)6.2.2D.1.2Test applicability (209)6.2.2D.1.3Minimum Conformance requirements (209)6.2.2D.2UE Maximum Output Power for ProSe Direct Communication (211)6.2.2D.2.1Test purpose (211)6.2.2D.2.2Test applicability (211)6.2.2D.2.3Minimum conformance requirements (211)6.2.2D.2.4Test description (211)6.2.2E UE Maximum Output Power for UE category 0 (212)6.2.2E.1Test purpose (212)6.2.2E.2Test applicability (212)6.2.2E.3Minimum conformance requirements (212)6.2.2E.4Test description (212)6.2.2E.4.3Message contents (213)6.2.2E.5Test requirements (213)6.2.2EA UE Maximum Output Power for UE category M1 (215)6.2.2EA.1Test purpose (215)6.2.2EA.2Test applicability (215)6.2.2EA.3Minimum conformance requirements (215)6.2.2EA.4Test description (216)6.2.2EA.4.3Message contents (217)6.2.2EA.5Test requirements (217)6.2.2F UE Maximum Output Power for category NB1 (218)6.2.2F.1Test purpose (218)6.2.2F.2Test applicability (218)6.2.2F.3Minimum conformance requirements (218)6.2.2F.4Test description (219)6.2.2F.4.1Initial condition (219)6.2.2F.4.2Test procedure (220)6.2.2F.4.3Message contents (220)6.2.2F.5Test requirements (220)6.2.2G UE Maximum Output Power for V2X Communication (221)6.2.2G.1UE Maximum Output Power for V2X Communication / Non-concurrent with E-UTRA uplinktransmission (221)6.2.2G.1.1Test purpose (221)6.2.2G.1.2Test applicability (221)6.2.2G.1.3Minimum conformance requirements (221)6.2.2G.1.4Test description (222)6.2.2G.1.4.1Initial conditions (222)6.2.2G.1.4.2Test procedure (222)6.2.2G.1.4.3Message contents (222)6.2.2G.1.5Test requirements (223)6.2.2G.2UE Maximum Output Power for V2X Communication / Simultaneous E-UTRA V2X sidelinkand E-UTRA uplink transmission (223)6.2.2G.2.1Test purpose (223)6.2.2G.2.2Test applicability (223)6.2.2G.2.3Minimum conformance requirements (223)6.2.2G.2.4Test description (224)6.2.2G.2.4.1Initial conditions (224)6.2.2G.2.4.2Test procedure (225)6.2.2G.2.4.3Message contents (226)6.2.2G.2.5Test requirements (226)6.2.3Maximum Power Reduction (MPR) (226)6.2.3.1Test purpose (226)6.2.3.2Test applicability (226)6.2.3.3Minimum conformance requirements (227)6.2.3.4Test description (227)6.2.3.4.1Initial condition (227)6.2.3.4.2Test procedure (228)6.2.3.4.3Message contents (228)6.2.3.5Test requirements (229)6.2.3_1Maximum Power Reduction (MPR) for HPUE (231)6.2.3_1.1Test purpose (231)6.2.3_1.4Test description (232)6.2.3_1.5Test requirements (232)6.2.3_2Maximum Power Reduction (MPR) for Multi-Cluster PUSCH (232)6.2.3_2.1Test purpose (232)6.2.3_2.2Test applicability (232)6.2.3_2.3Minimum conformance requirements (233)6.2.3_2.4Test description (233)6.2.3_2.4.1Initial condition (233)6.2.3_2.4.2Test procedure (234)6.2.3_2.4.3Message contents (234)6.2.3_2.5Test requirements (234)6.2.3_3Maximum Power Reduction (MPR) for UL 64QAM (235)6.2.3_3.1Test purpose (236)6.2.3_3.2Test applicability (236)6.2.3_3.3Minimum conformance requirements (236)6.2.3_3.4Test description (236)6.2.3_3.4.1Initial condition (236)6.2.3_3.4.2Test procedure (237)6.2.3_3.4.3Message contents (237)6.2.3_3.5Test requirements (238)6.2.3_4Maximum Power Reduction (MPR) for Multi-Cluster PUSCH with UL 64QAM (240)6.2.3_4.1Test purpose (240)6.2.3_4.2Test applicability (240)6.2.3_4.3Minimum conformance requirements (240)6.2.3_4.4Test description (241)6.2.3_4.4.1Initial condition (241)6.2.3_4.4.2Test procedure (242)6.2.3_4.4.3Message contents (242)6.2.3_4.5Test requirements (242)6.2.3A Maximum Power Reduction (MPR) for CA (243)6.2.3A.1Maximum Power Reduction (MPR) for CA (intra-band contiguous DL CA and UL CA) (243)6.2.3A.1.1Test purpose (243)6.2.3A.1.2Test applicability (243)6.2.3A.1.3Minimum conformance requirements (244)6.2.3A.1.4Test description (245)6.2.3A.1.5Test Requirements (248)6.2.3A.1_1Maximum Power Reduction (MPR) for CA (intra-band contiguous DL CA and UL CA) for UL64QAM (250)6.2.3A.1_1.1Test purpose (251)6.2.3A.1_1.2Test applicability (251)6.2.3A.1_1.3Minimum conformance requirements (251)6.2.3A.1_1.4Test description (252)6.2.3A.1_1.5Test requirement (254)6.2.3A.2Maximum Power Reduction (MPR) for CA (inter-band DL CA and UL CA) (255)6.2.3A.2.1Test purpose (255)6.2.3A.2.2Test applicability (255)6.2.3A.2.3Minimum conformance requirements (255)6.2.3A.2.4Test description (256)6.2.3A.2.5Test Requirements (260)6.2.3A.2_1Maximum Power Reduction (MPR) for CA (inter-band DL CA and UL CA) for UL 64QAM (263)6.2.3A.2_1.1Test purpose (263)6.2.3A.2_1.2Test applicability (263)6.2.3A.2_1.3Minimum conformance requirements (263)6.2.3A.2_1.4Test description (264)6.2.3A.2_1.5Test Requirements (266)6.2.3A.3Maximum Power Reduction (MPR) for CA (intra-band non-contiguous DL CA and UL CA) (267)6.2.3A.3.1Test purpose (267)6.2.3A.3.2Test applicability (267)6.2.3A.3.3Minimum conformance requirements (268)6.2.3A.3.4Test description (268)6.2.3A.3_1Maximum Power Reduction (MPR) for CA (intra-band non-contiguous DL CA and UL CA) forUL 64QAM (270)6.2.3A.3_1.1Test purpose (270)6.2.3A.3_1.2Test applicability (270)6.2.3A.3_1.3Minimum conformance requirements (270)6.2.3A.3_1.4Test description (271)6.2.3A.3_1.5Test Requirements (272)6.2.3B Maximum Power Reduction (MPR) for UL-MIMO (272)6.2.3B.1Test purpose (272)6.2.3B.2Test applicability (272)6.2.3B.3Minimum conformance requirements (273)6.2.3B.4Test description (273)6.2.3B.4.1Initial condition (273)6.2.3B.4.2Test procedure (274)6.2.3B.4.3Message contents (275)6.2.3B.5Test requirements (275)6.2.3D UE Maximum Output Power for ProSe (277)6.2.3D.0Minimum conformance requirements (277)6.2.3D.1Maximum Power Reduction (MPR) for ProSe Discovery (278)6.2.3D.1.1Test purpose (278)6.2.3D.1.2Test applicability (278)6.2.3D.1.3Minimum conformance requirements (278)6.2.3D.1.4Test description (278)6.2.3D.1.4.1Initial condition (278)6.2.3D.1.4.2Test procedure (279)6.2.3D.1.4.3Message contents (279)6.2.3D.1.5Test requirements (280)6.2.3D.2Maximum Power Reduction (MPR) ProSe Direct Communication (281)6.2.3D.2.1Test purpose (282)6.2.3D.2.2Test applicability (282)6.2.3D.2.3Minimum conformance requirements (282)6.2.3D.2.4Test description (282)6.2.3D.2.4.1Initial conditions (282)6.2.3D.2.4.2Test procedure (282)6.2.3D.2.4.3Message contents (282)6.2.3D.2.5Test requirements (282)6.2.3E Maximum Power Reduction (MPR) for UE category 0 (282)6.2.3E.1Test purpose (282)6.2.3E.2Test applicability (282)6.2.3E.3Minimum conformance requirements (282)6.2.3E.4Test description (282)6.2.3E.4.1Initial condition (282)6.2.3E.4.2Test procedure (283)6.2.3E.4.3Message contents (283)6.2.3E.5Test requirements (283)6.2.3EA Maximum Power Reduction (MPR) for UE category M1 (284)6.2.3EA.1Test purpose (284)6.2.3EA.2Test applicability (284)6.2.3EA.3Minimum conformance requirements (284)6.2.3EA.4Test description (285)6.2.3EA.4.1Initial condition (285)6.2.3EA.4.2Test procedure (287)6.2.3EA.4.3Message contents (287)6.2.3EA.5Test requirements (287)6.2.3F Maximum Power Reduction (MPR) for category NB1 (290)6.2.3F.1Test purpose (290)6.2.3F.2Test applicability (290)6.2.3F.3Minimum conformance requirements (290)6.2.3F.4Test description (291)6.2.3F.4.1Initial condition (291)6.2.3F.5Test requirements (292)6.2.3G Maximum Power Reduction (MPR) for V2X communication (292)6.2.3G.1Maximum Power Reduction (MPR) for V2X Communication / Power class 3 (293)6.2.3G.1.1Maximum Power Reduction (MPR) for V2X Communication / Power class 3 / Contiguousallocation of PSCCH and PSSCH (293)6.2.3G.1.1.1Test purpose (293)6.2.3G.1.1.2Test applicability (293)6.2.3G.1.1.3Minimum conformance requirements (293)6.2.3G.1.1.4Test description (293)6.2.3G.1.1.4.1Initial condition (293)6.2.3G.1.1.4.2Test procedure (294)6.2.3G.1.1.4.3Message contents (294)6.2.3G.1.1.5Test Requirements (294)6.2.3G.1.2 2956.2.3G.1.3Maximum Power Reduction (MPR) for V2X Communication / Power class 3 / SimultaneousE-UTRA V2X sidelink and E-UTRA uplink transmission (295)6.2.3G.1.3.1Test purpose (295)6.2.3G.1.3.2Test applicability (295)6.2.3G.1.3.3Minimum conformance requirements (295)6.2.3G.1.3.4Test description (295)6.2.3G.1.3.4.1Initial conditions (295)6.2.3G.1.3.4.2Test procedure (296)6.2.3G.1.3.4.3Message contents (297)6.2.3G.1.3.5Test requirements (297)6.2.4Additional Maximum Power Reduction (A-MPR) (297)6.2.4.1Test purpose (297)6.2.4.2Test applicability (297)6.2.4.3Minimum conformance requirements (298)6.2.4.4Test description (310)6.2.4.4.1Initial condition (310)6.2.4.4.2Test procedure (339)6.2.4.4.3Message contents (339)6.2.4.5Test requirements (344)6.2.4_1Additional Maximum Power Reduction (A-MPR) for HPUE (373)6.2.4_1.2Test applicability (374)6.2.4_1.3Minimum conformance requirements (374)6.2.4_1.4Test description (375)6.2.4_1.5Test requirements (376)6.2.4_2Additional Maximum Power Reduction (A-MPR) for UL 64QAM (378)6.2.4_2.1Test purpose (378)6.2.4_2.2Test applicability (378)6.2.4_2.3Minimum conformance requirements (378)6.2.4_2.4Test description (378)6.2.4_2.4.1Initial condition (378)6.2.4_2.4.2Test procedure (392)6.2.4_2.4.3Message contents (392)6.2.4_2.5Test requirements (392)6.2.4_3Additional Maximum Power Reduction (A-MPR) with PUSCH frequency hopping (404)6.2.4_3.1Test purpose (404)6.2.4_3.2Test applicability (404)6.2.4_3.3Minimum conformance requirements (405)6.2.4_3.4Test description (405)6.2.4_3.5Test requirements (406)6.2.4A Additional Maximum Power Reduction (A-MPR) for CA (407)6.2.4A.1Additional Maximum Power Reduction (A-MPR) for CA (intra-band contiguous DL CA and ULCA) (407)6.2.4A.1.1Test purpose (407)6.2.4A.1.2Test applicability (407)6.2.4A.1.3Minimum conformance requirements (407)6.2.4A.1.3.5A-MPR for CA_NS_05 for CA_38C (411)6.2.4A.1.4Test description (413)6.2.4A.1.5Test requirements (419)6.2.4A.1_1Additional Maximum Power Reduction (A-MPR) for CA (intra-band contiguous DL CA and ULCA) for UL 64QAM (425)6.2.4A.1_1.1Test purpose (425)6.2.4A.1_1.2Test applicability (425)6.2.4A.1_1.3Minimum conformance requirements (426)6.2.4A.1_1.3.5A-MPR for CA_NS_05 for CA_38C (429)6.2.4A.1_1.3.6A-MPR for CA_NS_06 for CA_7C (430)6.2.4A.1_1.3.7A-MPR for CA_NS_07 for CA_39C (431)6.2.4A.1_1.3.8A-MPR for CA_NS_08 for CA_42C (432)6.2.4A.1_1.4Test description (432)6.2.4A.1_1.5Test requirements (437)6.2.4A.2Additional Maximum Power Reduction (A-MPR) for CA (inter-band DL CA and UL CA) (443)6.2.4A.2.1Test purpose (443)6.2.4A.2.2Test applicability (444)6.2.4A.2.3Minimum conformance requirements (444)6.2.4A.2.4Test description (444)6.2.4A.2.4.1Initial conditions (444)6.2.4A.2.4.2Test procedure (457)6.2.4A.2.4.3Message contents (458)6.2.4A.2.5Test requirements (461)6.2.4A.3Additional Maximum Power Reduction (A-MPR) for CA (intra-band non-contiguous DL CAand UL CA) (466)6.2.4A.3.1Minimum conformance requirements (466)6.2.4A.2_1Additional Maximum Power Reduction (A-MPR) for CA (inter-band DL CA and UL CA) forUL 64QAM (466)6.2.4A.2_1.1Test purpose (466)6.2.4A.2_1.2Test applicability (466)6.2.4A.2_1.3Minimum conformance requirements (467)6.2.4A.2_1.4Test description (467)6.2.4A.2_1.4.1Initial conditions (467)6.2.4A.2_1.4.2Test procedure (479)6.2.4A.2_1.4.3Message contents (480)6.2.4A.2_1.5Test requirements (480)6.2.4B Additional Maximum Power Reduction (A-MPR) for UL-MIMO (484)6.2.4B.1Test purpose (484)6.2.4B.2Test applicability (485)6.2.4B.3Minimum conformance requirements (485)6.2.4B.4Test description (485)6.2.4B.4.1Initial condition (485)6.2.4B.4.2Test procedure (508)6.2.4B.4.3Message contents (508)6.2.4B.5Test requirements (508)6.2.4E Additional Maximum Power Reduction (A-MPR) for UE category 0 (530)6.2.4E.1Test purpose (530)6.2.4E.2Test applicability (531)6.2.4E.3Minimum conformance requirements (531)6.2.4E.4Test description (531)6.2.4E.4.1Initial condition (531)6.2.4E.4.2Test procedure (535)6.2.4E.4.3Message contents (535)6.2.4E.5Test requirements (536)6.2.4EA Additional Maximum Power Reduction (A-MPR) for UE category M1 (542)6.2.4EA.1Test purpose (542)6.2.4EA.2Test applicability (542)6.2.4EA.3Minimum conformance requirements (543)6.2.4EA.4Test description (544)6.2.4EA.4.1Initial condition (544)6.2.4EA.4.2Test procedure (552)6.2.4G Additional Maximum Power Reduction (A-MPR) for V2X Communication (562)6.2.4G.1Additional Maximum Power Reduction (A-MPR) for V2X Communication / Non-concurrentwith E-UTRA uplink transmissions (562)6.2.4G.1.1Test purpose (562)6.2.4G.1.2Test applicability (562)6.2.4G.1.3Minimum conformance requirements (563)6.2.4G.1.4Test description (563)6.2.4G.1.4.1Initial condition (563)6.2.4G.1.4.2Test procedure (564)6.2.4G.1.4.3Message contents (564)6.2.4G.1.5Test Requirements (564)6.2.5Configured UE transmitted Output Power (564)6.2.5.1Test purpose (564)6.2.5.2Test applicability (564)6.2.5.3Minimum conformance requirements (564)6.2.5.4Test description (594)6.2.5.4.1Initial conditions (594)6.2.5.4.2Test procedure (595)6.2.5.4.3Message contents (595)6.2.5.5Test requirement (596)6.2.5_1Configured UE transmitted Output Power for HPUE (596)6.2.5_1.1Test purpose (596)6.2.5_1.2Test applicability (597)6.2.5_1.3Minimum conformance requirements (597)6.2.5_1.4Test description (597)6.2.5_1.4.1Initial conditions (597)6.2.5_1.4.2Test procedure (597)6.2.5_1.4.3Message contents (597)6.2.5_1.5Test requirement (598)6.2.5A Configured transmitted power for CA (599)6.2.5A.1Configured UE transmitted Output Power for CA (intra-band contiguous DL CA and UL CA) (599)6.2.5A.1.1Test purpose (599)6.2.5A.1.2Test applicability (599)6.2.5A.1.3Minimum conformance requirements (599)6.2.5A.1.4Test description (601)6.2.5A.1.5Test requirement (602)6.2.5A.2Void (603)6.2.5A.3Configured UE transmitted Output Power for CA (inter-band DL CA and UL CA) (603)6.2.5A.3.1Test purpose (603)6.2.5A.3.2Test applicability (603)6.2.5A.3.3Minimum conformance requirements (603)6.2.5A.3.4Test description (605)6.2.5A.3.5Test requirement (606)6.2.5A.4Configured UE transmitted Output Power for CA (intra-band non-contiguous DL CA and ULCA) (607)6.2.5A.4.1Test purpose (607)6.2.5A.4.2Test applicability (607)6.2.5A.4.3Minimum conformance requirements (607)6.2.5A.4.4Test description (608)6.2.5A.4.5Test requirement (610)6.2.5B Configured UE transmitted Output Power for UL-MIMO (611)6.2.5B.1Test purpose (611)6.2.5B.2Test applicability (611)6.2.5B.3Minimum conformance requirements (611)6.2.5B.4Test description (612)6.2.5B.4.1Initial conditions (612)6.2.5B.4.2Test procedure (612)6.2.5B.4.3Message contents (613)6.2.5B.5Test requirement (613)6.2.5E Configured UE transmitted Output Power for UE category 0 (614)6.2.5E.4.1Initial conditions (614)6.2.5E.4.2Test procedure (614)6.2.5E.4.3Message contents (614)6.2.5E.5Test requirement (615)6.2.5EA Configured UE transmitted Power for UE category M1 (615)6.2.5EA.1Test purpose (615)6.2.5EA.2Test applicability (615)6.2.5EA.3Minimum conformance requirements (615)6.2.5EA.4Test description (616)6.2.5EA.4.1Initial condition (616)6.2.5EA.4.2Test procedure (617)6.2.5EA.4.3Message contents (617)6.2.5EA.5Test requirements (617)6.2.5F Configured UE transmitted Output Power for UE category NB1 (618)6.2.5F.1Test purpose (618)6.2.5F.2Test applicability (618)6.2.5F.3Minimum conformance requirements (618)6.2.5F.4Test description (619)6.2.5F.4.1Initial conditions (619)6.2.5F.4.2Test procedure (620)6.2.5F.4.3Message contents (620)6.2.5F.5Test requirement (620)6.2.5G Configured UE transmitted Output Power for V2X Communication (620)6.2.5G.1Configured UE transmitted Output Power for V2X Communication / Non-concurrent with E-UTRA uplink transmission (621)6.2.5G.1.1Test purpose (621)6.2.5G.1.2Test applicability (621)6.2.5G.1.3Minimum conformance requirements (621)6.2.5G.1.4Test description (622)6.2.5G.1.4.1Initial conditions (622)6.2.5G.1.4.2Test procedure (622)6.2.5G.1.4.3Message contents (622)6.2.5G.1.5Test requirements (622)6.2.5G.2Configured UE transmitted Output Power for V2X Communication / Simultaneous E-UTRAV2X sidelink and E-UTRA uplink transmission (622)6.2.5G.2.1Test purpose (623)6.2.5G.2.2Test applicability (623)6.2.5G.2.3Minimum conformance requirements (623)6.2.5G.2.4Test description (625)6.2.5G.2.4.1Initial conditions (625)6.2.5G.2.4.2Test procedure (626)6.2.5G.2.4.3Message contents (626)6.2.5G.2.5Test requirements (626)6.3Output Power Dynamics (627)6.3.1Void (627)6.3.2Minimum Output Power (627)6.3.2.1Test purpose (627)6.3.2.2Test applicability (627)6.3.2.3Minimum conformance requirements (627)6.3.2.4Test description (627)6.3.2.4.1Initial conditions (627)6.3.2.4.2Test procedure (628)6.3.2.4.3Message contents (628)6.3.2.5Test requirement (628)6.3.2A Minimum Output Power for CA (629)6.3.2A.0Minimum conformance requirements (629)6.3.2A.1Minimum Output Power for CA (intra-band contiguous DL CA and UL CA) (629)6.3.2A.1.1Test purpose (629)6.3.2A.1.4.2Test procedure (631)6.3.2A.1.4.3Message contents (631)6.3.2A.1.5Test requirements (631)6.3.2A.2Minimum Output Power for CA (inter-band DL CA and UL CA) (631)6.3.2A.2.1Test purpose (631)6.3.2A.2.2Test applicability (632)6.3.2A.2.3Minimum conformance requirements (632)6.3.2A.2.4Test description (632)6.3.2A.2.4.1Initial conditions (632)6.3.2A.2.4.2Test procedure (633)6.3.2A.2.4.3Message contents (633)6.3.2A.2.5Test requirements (633)6.3.2A.3Minimum Output Power for CA (intra-band non-contiguous DL CA and UL CA) (634)6.3.2A.3.1Test purpose (634)6.3.2A.3.2Test applicability (634)6.3.2A.3.3Minimum conformance requirements (634)6.3.2A.3.4Test description (634)6.3.2A.3.4.1Initial conditions (634)6.3.2A.3.4.2Test procedure (635)6.3.2A.3.4.3Message contents (635)6.3.2A.3.5Test requirements (635)6.3.2B Minimum Output Power for UL-MIMO (636)6.3.2B.1Test purpose (636)6.3.2B.2Test applicability (636)6.3.2B.3Minimum conformance requirements (636)6.3.2B.4Test description (636)6.3.2B.4.1Initial conditions (636)6.3.2B.4.2Test procedure (637)6.3.2B.4.3Message contents (637)6.3.2B.5Test requirement (637)6.3.2E Minimum Output Power for UE category 0 (638)6.3.2E.1Test purpose (638)6.3.2E.2Test applicability (638)6.3.2E.3Minimum conformance requirements (638)6.3.2E.4Test description (638)6.3.2E.4.1Initial conditions (638)6.3.2E.4.2Test procedure (639)6.3.2E.4.3Message contents (639)6.3.2E.5Test requirement (639)6.3.2EA Minimum Output Power for UE category M1 (639)6.3.2EA.1Test purpose (639)6.3.2EA.2Test applicability (640)6.3.2EA.3Minimum conformance requirements (640)6.3.2EA.4Test description (640)6.3.2EA.4.1Initial condition (640)6.3.2EA.4.2Test procedure (641)6.3.2EA.4.3Message contents (641)6.3.2EA.5Test requirements (641)6.3.2F Minimum Output Power for category NB1 (641)6.3.2F.1Test purpose (641)6.3.2F.2Test applicability (641)6.3.2F.3Minimum conformance requirements (642)6.3.2F.4Test description (642)6.3.2F.4.1Initial conditions (642)6.3.2F.4.2Test procedure (643)6.3.2F.4.3Message contents (643)6.3.2F.5Test requirements (643)6.3.3Transmit OFF power (643)6.3.3.5Test requirement (644)6.3.3A UE Transmit OFF power for CA (644)6.3.3A.0Minimum conformance requirements (644)6.3.3A.1UE Transmit OFF power for CA (intra-band contiguous DL CA and UL CA) (645)6.3.3A.1.1Test purpose (645)6.3.3A.1.2Test applicability (645)6.3.3A.1.3Minimum conformance requirements (645)6.3.3A.1.4Test description (645)6.3.3A.1.5Test Requirements (645)6.3.3A.2UE Transmit OFF power for CA (inter-band DL CA and UL CA) (646)6.3.3A.2.1Test purpose (646)6.3.3A.2.2Test applicability (646)6.3.3A.2.3Minimum conformance requirements (646)6.3.3A.2.4Test description (646)6.3.3A.2.5Test Requirements (646)6.3.3A.3UE Transmit OFF power for CA (intra-band non-contiguous DL CA and UL CA) (646)6.3.3A.3.1Test purpose (646)6.3.3A.3.2Test applicability (646)6.3.3A.3.3Minimum conformance requirements (647)6.3.3A.3.4Test description (647)6.3.3A.3.5Test Requirements (647)6.3.3B UE Transmit OFF power for UL-MIMO (647)6.3.3B.1Test purpose (647)6.3.3B.2Test applicability (647)6.3.3B.3Minimum conformance requirement (647)6.3.3B.4Test description (647)6.3.3B.5Test requirement (648)6.3.3C 6486.3.3D UE Transmit OFF power for ProSe (648)6.3.3D.0Minimum conformance requirements (648)6.3.3D.1UE Transmit OFF power for ProSe Direct Discovery (648)6.3.3D.1.1Test purpose (649)6.3.3D.1.2Test applicability (649)6.3.3D.1.3Minimum Conformance requirements (649)6.3.3D.1.4Test description (649)6.3.3D.1.5Test requirements (650)6.3.3E UE Transmit OFF power for UE category 0 (650)6.3.3E.1Test purpose (650)6.3.3E.2Test applicability (650)6.3.3E.3Minimum conformance requirement (650)6.3.3E.4Test description (651)6.3.3E.5Test requirement (651)6.3.3EA UE Transmit OFF power for UE category M1 (651)6.3.3EA.1Test purpose (651)6.3.3EA.2Test applicability (651)6.3.3EA.3Minimum conformance requirements (651)6.3.3EA.4Test description (651)6.3.3EA.5Test requirements (652)6.3.3F Transmit OFF power for category NB1 (652)6.3.3F.1Test purpose (652)6.3.3F.2Test applicability (652)6.3.3F.3Minimum conformance requirement (652)6.3.3F.4Test description (652)6.3.3F.5Test requirement (652)6.3.4ON/OFF time mask (652)6.3.4.1General ON/OFF time mask (652)6.3.4.1.1Test purpose (652)6.3.4.1.2Test applicability (653)。
机械毕业设计英文外文翻译493五轴数控铣床翻译
机械毕业设计英⽂外⽂翻译493五轴数控铣床翻译【附】英⽂原⽂翻译⽂献:Five-axis milling machine tool kinematic chain design and analysis作者:E.L.J. Bohez⽂献出处:International Journal of Machine Tools & Manufacture 42 (2002) 505–520 翻译页数:Five-axis milling machine tool kinematic chain design and analysis 1. IntroductionThe main design specifications of a machine tool can be deduced from the following principles:● The kinematics should provide sufficient flexibility inorientation and position of tool and part.● Orientation and positioning with the highest poss iblespeed.● Orientation and positioning with the highest possibleaccuracy.● Fast change of tool and workpiece.● Save for the environment.● Highest possible material removal rate.The number of axes of a machine tool normally refers to the number of degrees of freedom or the number of independent controllable motions on the machine slides.The ISO axes nomenclature recommends the use of a right-handed coordinate system, with the tool axis corresponding to the Z-axis.A three-axis milling machine has three linear slides X, Y and Z which can be positioned everywhere within the travel limit of each slide. The tool axis direction stays fixed during machining. This limits the flexibility of the tool orientation relative to the workpiece and results in a number of different set ups. To increase the flexibility in possible tool workpiece orientations, without need of re-setup, more degrees of freedom must be added. For a conventional three linear axes machine this can be achieved by providing rotational slides. Fig. 1 gives an example of a five-axis milling machine.2. Kinematic chain diagramTo analyze the machine it is very useful to make a kinematic diagram of the machine. From this kinematic (chain) diagram two groups of axes can immediately be distinguished: the workpiece carrying axes and the tool carrying axes. Fig. 2 gives the kinematic diagram of the five-axis machine in Fig. 1. As can be seen the workpiece is carried by four axes and the toolonly by one axis.The five-axis machine is similar to two cooperating robots, one robot carrying the workpiece and one robot carrying the tool.Five degrees of freedom are the minimum required to obtain maximum flexibility in tool workpiece orientation,this means that the tool and workpiece can be oriented relative to each other under any angle. The minimum required number of axes can also be understood from a rigid body kinematics point of view. To orient two rigid bodies in space relative to each other 6 degrees of freedom are needed for each body (tool and workpiece) or 12 degrees. However any common translation and rotation which does not change the relative orientation is permitted reducing the number of degrees by 6. The distance between the bodies is prescribed by the toolpath and allows elimination of an additional degree of freedom, resulting in a minimum requirement of 5 degrees.3.Literature reviewOne of the earliest (1970) and still very useful introductions to five-axis milling was given by Baughman [1]clearly stating the applications. The APT language was then the only tool to program five-axis contouring applications.The problems in postprocessing were also clearly stated by Sim [2] in those earlier days of numerical control and most issues are still valid. Boyd in Ref.[3] was also one of the early introductions. Bez iers’ book[4] is also still a very useful introduction. Held [5] gives a very brief but enlightening definition of multi-axis machining in his book on pocket milling. A recent paper applicable to the problem of five-axis machine workspace computation is the multiple sweeping using the Denawit-Hartenberg representation method developed by Abdel-Malek and Othman [6].Many types and design concepts of machine tools which can be applied to five-axis machines are discussed in Ref. [7] but not specifically for the five-axis machine.he number of setups and the optimal orientation of the part on the machine table is discussed in Ref.[8]. A review about the state of the art and new requirements for tool path generation is given by B.K. Choi et al. [9].Graphic simulation of the interaction of the tool and workpiece is also a very active area of research and a good introduction can be found in Ref. [10].4. Classification of five-axis machines’ kinematic structureStarting from Rotary (R) and Translatory (T) axes four main groups can be distinguished: (i) three T axes and two R axes; (ii) two T axes and three R axes; (iii) one T axis and four R axes and (iv) five R axes. Nearly all existing five-axis machine tools are in group (i). Also a number of welding robots, filament winding machines and laser machining centers fall in this group. Only limited instances of five-axis machine tools in group (ii)exist for the machining of ship propellers. Groups (iii)and (iv) are used in the design of robots usually with more degrees of freedom added.The five axes can be distributed between the workpiece or tool in several combinations. A first classification can be made based on the number of workpiece and tool carrying axes and the sequence of each axis in the kinematic chain.Another classification can be based on where the rotary axes are located, on the workpiece side or tool side. The five degrees of freedom in a Cartesian coordinates based machine are: three translatory movements X,Y,Z (in general represented as TTT) and two rotational movements AB, AC or BC (in general represented as RR).Combinations of three rotary axes (RRR)and two linear axes (TT) are rare. If an axis is bearing the workpiece it is the habit of noting it with an additional accent. The five-axis machine in Fig. 1 can be characterized by XYABZ. The XYAB axes carry the workpiece and the Z-axis carries the tool. Fig. 3 shows a machine of the type XYZAB , the three linear axes carry the tool and the two rotary axes carry the workpiece.5. Workspace of a five-axis machineBefore defining the workspace of the five-axis machine tool, it is appropriate to define the workspace of the tool and the workspace of the workpiece. The workspace of the tool is the space obtained by sweeping the tool reference point (e.g. tool tip) along the path of the tool carrying axes. The workspace of the workpiece carrying axes is defined in the same way (the center of the machine table can be chosen as reference point).These workspaces can be determined by computing the swept volume [6].Based on the above-definitions some quantitative parameters can be defined which are useful for comparison, selection and design of different types of machines.6.Selection criteria of a five-axis machineIt is not the objective to make a complete study on how to select or design a five-axis machine for a certain application. Only the main criteria which can be used to justify the selection of a five-axis machine are discussed.6.1. Applications of five-axis machine toolsThe applications can be classified in positioning and contouring. Figs. 12 and 13 explain the difference between five-axispositioning and five-axis contouring.6.1.1. Five-axis positioningFig. 12 shows a part with a lot of holes and flat planes under different angles, to make this part with a three axis milling machine it is not possible to process the part in one set up. If a five-axis machine is used the tool can process. More details on countouring can be found in Ref. [13]. Applications of five-axis contouring are: (i) production of blades, such as compressor and turbine blades; (ii) injectors of fuel pumps; (iii) profiles of tires; (iv) medical prosthesis such as artificial heart valves; (v) molds made of complex surfaces.6.1.2. Five-axis contouringFig. 13 shows an example of five-axis contouring, tomachine the complex shape of the surface we need to control the orientation of the tool relative to the part during cutting. The tool workpiece orientation changes in each step. The CNC controller needs to control all the five-axes simultaneously during the material removal process. More details on countouring can be found in Ref. [13]. Applications of five-axis contouring are: (i) production of blades, such as compressor and turbine blades; (ii) injectors of fuel pumps; (iii) profiles of tires; (iv) medical prosthesis such as artificial heart valves; (v)molds made of complex surfaces.6.2. Axes configuration selectionThe size and weight of the part is very important as a first criterion to design or select a configuration. Very heavy workpieces require short workpiece kinematic chains. Also there is a preference for horizontal machine tables which makes it more convenient to fix and handle the workpiece. Putting a heavy workpiece on a single rotary axis kinematic chain will increase the orientation flexibility very much. It can be observed from Fig. 4that providing a single horizontal rotary axis to carry the workpiece will make the machine more flexible. In most cases the tool carrying kinematic chains will be kept as short as possible because the toolspindle drive must also be carried.6.3.five-axes machining of jewelryA typical workpiece could be a flower shaped part as in Fig. 14. This application is clearly contouring. The part will be relatively small compared to the tool assembly. Also small diameter tools will require a high speed spindle. A horizontalrotary table would be a very good option as the operator will have a good view of the part (with range 360°). All axes as workpiece carrying axes would be a good choice because the toolspindlecould be fixed and made very rigid. There are 20 ways in which the axes can be combined in the workpiece kinematic chain (Section 4.2.1). Here only two kinematic chains will be considered. Case one will be a T T T R R kinematic chain shown in Fig. 15. Case two will be a R R T T T kinematic chain shown in Fig.16.For model I a machine with a range of X=300mmY=250 mm, Z=200 mm, C=n 360° and A=360°, and a machine tool table of 100 mm diameter will be considered. For this kinematic chain the tool workspace is a single point. The set of tool reference points which can be selected is also small. With the above machine travel ranges the workpiece workspace will be the space swept by the center of the machine table. If the centerline of the two rotary axes intersect in the reference point, a prismatic workpiece workspace will be obtained with as size XYZ or 300×250×200 mm3. If the centerlines of the two rotary axes do not intersect in the workpiece reference point then the workpiece workspace will be larger.It will be a prismatic shape with rounded edges. The radius of this rounded edge is the excentricity of the bworkpiece reference point relative to each centerline. Model II in Fig. 15 has the rotary axes at the beginning of the kinematic chain (R R T T T ). Here also two different values of the rotary axes excentricity will be considered. The same range of the axes as in model I is considered. The parameters defined in Section 5 are computed for each model and excentricity and summarized in Table 1. It can be seen that with the rotary axes at the end of the kinematic chain (model I), a much smaller machine tool workspace is obtained. There are two main reasons for this. The swept volume of the tool and workpiece WSTOOL WSWORK is much smaller for model I. The second reason is due to the fact that a large part of the machine tool workspace cannot be used in the case of model I, because of interference with the linear axes. The workspace utilization factor however is larger for the model I with no excentricity because the union of the tool workspace and workpiece workspace is relatively smaller compared with model I with excentricity e=50 mm. The orientation space index is the same for both cases if the table diameter is kept the same. Model II can handle much larger workpieces for the same range of linear axes as in model I. The rotary axes are here in the beginning of the kinematic chain, resulting in a much larger machine tool workspace then for model I. Also there is much less interference of the machine tool workspace with the slides. The other 18 possible kinematicchain selections will give index values somewhat in between the above cases.6.4. rotary table selectionTwo machines with the same kinematic diagram (T T R R T) and the same range of travel in the linear axes will be compared (Fig. 17). There are two options for the rotary axes: two-axis table with vertical table (model I), two-axis table with horizontal table (model II). Tables 2 and 3 give the comparison of the important features. It can be observed that reducing the range of the rotary axes increases the machine tool workspace. So model I will be more suited for smaller workpieces with operations which require a large orientation range, typically contouring applications. Model II will be suited for larger workpieces with less variation in tool orientation or will require two setups. This extra setup requirement could be of less importance then the larger size. The horizontal table can use pallets which transform the internal setup to external setup. The larger angle range in the B-axes 105 to +105, Fig. 17. Model I and model II T T R R T machines. compared to 45 to +20, makes model I more suited for complex sculptured surfaces, also because the much higher angular speed range of the vertical angular table. The option with the highest spindle speed should be selected and it will permit the use of smaller cutter diameters resulting in less undercut and smaller cutting forces. The high spindle speed will make the cutting of copper electrodes for die sinking EDM machines easier. The vertical table is also better for the chip removal. The large range of angular orientation, however, reduces the maximum size of the workpiece to about 300 mm and 100 kg. Model II with the same linear axes range as model I, but much smaller range in the rotation, can easily handle a workpiece of double size and weight. Model II will be good for positioning applications. Model I cannot be provided with automaticworkpiece exchange, making it less suitable for mass production. Model II has automatic workpiece exchange and is suitable for mass production of position applications. Model I could, however, be selected for positioning applications for parts such as hydraulic valve housings which are small and would require a large angular range.7.New machine concepts based on the Stewart platformConventional machine tool structures are based on Carthesian coordinates. Many surface contouring applications can be machined in optimal conditions only with five-axis machines. This five-axis machine structure requires two additional rotary axes. To make accurate machines, with the required stiffness, able to carry large workpieces, very heavy and large machines are required. As can be seen from the kinematic chain diagram of the classical five-axis machine design the first axis in the chain carries all the subsequent axes. So the dynamic responce will be limited by the combined inertia. A mechanism which can move the workpiece without having to carry the other axes would be the ideal. A new design concept is the use of a‘HEXAPOD’. Stewart [16] described the hexapod principle in 1965. It was first constructed by Gough and Whitehall [20] in 1954 and served as tire tester. Many possible uses were proposed but it was only applied to flight simulator platforms. Thereason was the complexity of the control of the six actuators. Recently with the amazing increase of speed and reduction in cost of computing, the Stewart platform is used by two American Companies in the design of new machine tools. The first machine is the VARIAX machine from the company Giddings and Lewis, USA. The second machine is the HEXAPOD from the Ingersoll company, USA. The systematic design of Hexapods and other similar systems is discussed in Ref. [17]. The problem of defining and determining the workspace of virtual axis machine tools is discussed in Ref. [18]. It can be observed from the design of the machine that once the position of the tool carrying plane is determined uniquely by the CL date (point + vector), it is still possible to rotate the tool carrying platform around the tool axis. This results in a large number of possible length combinations of the telescopic actuators for the same CL data.8.ConclusionTheoretically there are large number of ways in which a five-axis machine can be built. Nearly all classical Cartesian five-axis machines belong to the group with three linear and two rotational axes or three rotational axes and two linear axes. This group can be subdivided in six subgroups each with 720 instances.If only the instances with three linear axes are considered there are still 360instances in each group. The instances are differentiated based on the order of the axes in both tool and workpiece carrying kinematic chain.If only the location of the rotary axes in the tool and workpiece kinematic chain is considered for grouping five-axis machines withthree linear axes and two rotational axes, three groups can be distinguished. In the first group the two rotary axes are implemented in the workpiece kinematic chain. In the second group the two rotary axes are implemented in the tool kinematic chain.In the third group there is one rotary axis in each kinematic chain. Each group still has twenty possible instances.To determine the best instance for a specific application area is a complex issue. To facilitate this some indexes for comparison have been defined such as the machine tool workspace, workspace utilization factor, orientation space index, orientation angle index and machine tool space efficiency. An algorithm to compute the machine tool workspace and the diameter of the largest spherical dome which can be machined on the machine was outlined.The use of these indexes for two examples was discussed in detail. The first example considers the design of a five-axis machine for jewelry machining. The second example illustrates the selection of the rotary axes options in the case of a machine with the same range in linear axes.翻译题名:Five-axis milling machine tool kinematic chain design and analysis期刊与作者:E.L.J. Bohez出版社:International Journal of Machine Tools & Manufacture 42 (2002) 505–520●英⽂译⽂摘要:现如今五轴数控加⼯中⼼已经⾮常普及。
伊顿 Quik-Spec 电源模块面板 数据表
Product description:The Quik-Spec™ Power Module Panel (PMP) is an all-in-one multi-elevator disconnect switch available in configurations to meet virtually any shutdown and disconnect requirement.Quik-Spec Power Module PanelAll-in-one elevator disconnectFeatures and options:• 400-800 amp bus MLO and/or main fused switch*• 200kA RMS short-circuit current rating • Feeder switches 30-200 amp, 600Vac with Class J clips 1•Copper busOptional features:• Control power transformer with fuses and blocks• Fire safety interface relay • Key to test switch • Pilot light – “ON”• Isolated neutral lug 2•Mechanically interlocked auxiliary contact for hydraulic elevators with battery backup (5 amp 120Vac rated)• Fire alarm voltage monitoring relay (to monitor shunt trip voltage)• NEMA 3R enclosures available (consult factory)• Phase failure and undervoltage relay available (consult factory)•For added safety, use the Bussmann SAMI™ fuse covers to improve maintenance personnel protection [OSHA 1910.335(A)(2)(ii)]3Agency information:•UL 67 enclosed and dead-front switches* Contact Bussmann for applications greater than 800 amps.1Class J fuses not included.2Oversized 200% rated neutral option available where required byexcessive non-linear loads.3Through 100A.Typical control with wiring options for fire safety interface (option R1)LegendN.O.F .A.Normally Open Fire Alarm contacts supplied from the fire alarm system to initiate the shunt trip.Shunt Trip Solenoid for remote trip of switch, which is activated by the closing of the fire alarm contacts or key test switch.Option R1Fire Safety Interface Relay that is operated at 120Vac from secondary of transformer. No additional power needed.CR Control Relay used to isolate the N.O.F .A. contacts from the duty of the shunt trip.FRFire Alarm Voltage Monitoring Relay used to monitor presence of voltage in switch from a remote location (Fire Alarm Control Panel).PL Pilot Light to visually indicate presence of voltage on outside of switch enclosure.CPT Control Power Transformer used to step down line voltage to 120Vac to power shunt trip coil.SW Aux.Normally closed contact when switch is closed. Opens as power switch opens.Key Test Key-to-Test switch used to operate shunt trip from the outside of switch enclosure. Can be used for trouble-shootingand inspection.Mechanically Interlocked Auxiliary Contact – Contact used to disconnect secondary source of power.Terminal block connection point. Pre-wired connection point.Mechanically interlocked aux contact Shunt tripOption F1: Relay terminal configurationVoltage monitoringNote: Contacts for FR are shown inde-energized postion.Wiring diagramOption A: battery backup terminal configurationMechanically interlocked auxiliary contactTo connect the battery lowering for hydraulic elevator, connectto points NC and COM.Note: Contacts for mechanically interlocked auxiliary contact areshown in the energized position.LegendN.O.F .A.Normally Open Fire Alarm contacts supplied from the fire alarm system to initiate the shunt trip.Shunt Trip Solenoid for remote trip of switch, which is activated by the closing of the fire alarm contacts or key test switch.Option R2Fire Safety Interface Relay that is operated at 24Vdc from fire alarm system. May require an additional power source to be needed.CR Control Relay used to isolate the N.O.F .A. contacts from the duty of the shunt trip.FR Fire Alarm Voltage Monitoring Relay used to monitor presence of voltage in switch from a remote location (i.e., FireAlarm Control Panel).PL Pilot Light to visually indicate presence of voltage on outside of switch enclosure.CPT Control Power Transformer used to step down line voltage to 120Vac to power shunt trip coil.SW Aux.Normally closed contact when switch is closed. Opens as power switch opens.Key Test Key-to-Test switch used to operate shunt trip from the outside of switch enclosure. Can be used for trouble-shootingand inspection.Mechanically Interlocked Auxiliary Contact Contact used to disconnect secondary source of power.Terminal block connection point.Pre-wired connection point.Wiring diagramOption A: battery backup terminal configurationMechanically interlocked aux contact Shunt tripVoltage monitoring24Vdc source provided by fire alarm systemMechanically interlocked auxiliary contactTo connect the battery lowering for hydraulic elevator, connectto points NC and COM.Note: Contacts for mechanically interlocked auxiliary contact areshown in the energized position.Typical control with wiring options for fire safety interface (option R2)The only controlled copy of this data sheet is the electronic read-only version located on the Bussmann network drive. All other copies of this document are by definition uncontrolled. This bulletin is intended to clearly present comprehensive product data and provide technical information that will help the end user with design applications. Bussmann reserves the right, without notice, to change design or construction of any products and to discontinue or limit distribution of any products. Bussmann also reserves the right to change or update, without notice, any technical information contained in this bulletin. Once a product has been selected, it should be tested by the user in all possible applications.Eaton’s Bussmann Business114 Old State RoadEllisville, MO 63021United States© 2014 EatonAll Rights ReservedPublication No. 1146 - BU-SB14456 July 2014Eaton is a registered trademark. All other trademarks are property of their respective owners.。
国际半导物 IRS27951 2 220W 评估板指南说明书
Rev. 4.0 5/22/2010 International RectifierPage 1 of 16PROPRIETARY INFORMATION - This document and the information contained therein are proprietary and are not to be reproduced, used or disclosedEnergy Saving Products101 N.Sepulveda Blvd, EL Segundo 90245 California, USAIRAC27951-220WIRS27951 Evaluation BoardUser GuideTable of Contents1INTRODUCTION (3)2IRS27951/2 DESCRIPTION (3)3EVALUATION BOARD SPECIFICATIONS (4)3.1Board Description (4)3.2Schematic (5)3.3Evaluation Board Picture (6)3.4Board Component Placement (6)3.5Board PCB Layout (7)3.6Bill of Materials (8)4EVALUATION BOARD OPERATING PROCEDURE (9)4.1Load Connection (9)4.2AC/DC Input (10)4.3IRS27951 DC Supply Voltage (10)4.4Power-up Sequence (10)5SYSTEM PERFORMANCE CHARACTERIZATION (11)5.1Steady-State and Start-up Waveforms (11)5.2Short Circuit Protection (12)5.3Dynamic Load Response & Output Voltage Regulation (13)5.4User Initiated SLEEP Mode (14)5.5Efficiency Chart (14)5.6Thermal Data (15)6Transformer Spec (15)6.1Electrical Diagram (16)6.2Resonant Transformer Winding Position on Coil former (16)6.3Resonant Transformer Winding Characteristics (16)Rev. 4.0 5/22/2010 International Rectifier Page 2 of 16 PROPRIETARY INFORMATION - This document and the information contained therein are proprietary and are not to be reproduced, used or disclosed1 INTRODUCTIONThis document details the test procedure for validation of IRS27951 Evaluation Board, featuring the IRS27951 Resonant Half Bridge controller HVIC. The document includes schematic diagram, test setup, test procedure, and test results.2 IRS27951/2 DESCRIPTIONThe IRS2795 is an 8 pin, high-voltage, double-ended controller specific for the resonant half-bridge topology. It provides 50% complementary duty cycle; the high-side and the low-side devices are driven 180° out-of-p hase for exactly the same time. The IC incorporates additional protection features for robust operation and provides a high performance solution while minimizing external components, design time, and printed circuit board real estate, all in an 8 pin SOIC package.The IC enables the designer to externally program all the following features using a 2 pin oscillator - operating frequency range (minimum and maximum frequency), startup frequency, dead time, soft-start time and sleep mode. Each of these functions are programmed as follows –The minimum frequency is programmed using RT and CT.The dead time is programmed using CT.RSS and CSS program the converter soft-start time.RSS//RT and CT program the converter start-up frequency.The converter maximum frequency is set by (Rmax//RT) and CT.Sleep mode is initiated by pulling the CT/SD to COM.At start-up, to prevent uncontrolled inrush current, the switching frequency starts from a programmable maximum value and progressively decays until it reaches the steady-state value determined by the control loop. This frequency shift is non linear to minimize output voltage overshoot and its duration is programmable as well. Output voltage regulation is obtained by modulating the operating frequency. An externally programmable dead time is inserted between the turn-OFF of one switch and the turn-ON of the other one allows device zero-voltage turn-on transitions.IRS2795 uses IR’s proprietary high-voltage technology to implement a VS sensing circuitry that monitors the current through the low-side half bridge MOSFET for short circuit faults. By using the R DSON of the low-side MOSFET, the IRS2795 eliminates the need for an additional current sensing resistor, filter and current-sensing pin. This protection feature is latched and the thresholds are fixed at 2V for IRS27951 and 3V for IRS27952.Finally, the controller IC also features a micro power startup current (I CC<100µA) and a user initiated sleep mode during which the IC power consumption is less than 200µA (@ Vcc=15V). The sleep mode function allows system designs with reduced standby power consumption and can be used to meet stringent energy standards from Blue Angel, Energy Star etc.Rev. 4.0 5/22/2010 International Rectifier Page 3 of 16 PROPRIETARY INFORMATION - This document and the information contained therein are proprietary and are not to be reproduced, used or disclosed3 EVALUATION BOARD1 SPECIFICATIONSInput Voltage...……….………………………………………………………….. ….280VAC or 400V DC AC Line Frequency Range…………………………………………………………..47 – 63HzConverter Switching Frequency Range……………………………………….. ….70-150 kHz Converter Outputs ....…… ………………………………………………………….24V/6A & 12V/6A Maximum Output Power…………………………………………………………......220WMinimum Load Requirement…………………………………………………………NoneMaximum Ambient Operating Temperature………………………………………..40°C2Efficiency (@ 220W)……...…………………………………………… ……….….. 92%Short Circuit Protection on both Output Rails...………………………………….. YesSingle Layer PCB with 2oz CopperThere are high voltages present whenever the board is energized and proper precautions should be taken to avoid potential shock and personal injury.3.1 Board DescriptionThe evaluation board consists of a front-end AC-DC rectifier stage cascaded with a half-bridge resonant DC-DC converter with multiple output voltage rails (24V and 12V). The front end is a conventional rectifier stage with a rectifier bridge and an EMI filter.The downstream converter is a multi-resonant half bridge LLC converter whose control is implemented with the IRS27951 (U1) controller HVIC. The controller drives the two half-bridge MOSFETs with a 50 percent fixed duty cycle with dead-time, changing the frequency according to the feedback signal in order to regulate the output voltages against load and input voltage variations. As described earlier, in addition to current protection, all the critical functions needed to control resonant converter designs can be externally programmed using this 8 pin controller IC.The transformer uses the magnetic integration approach, incorporating the resonant series and shunt inductances in the power transformer. The transformer configuration chosen for the secondary winding is center-tap, and the output rectifiers are Schottky diodes. The feedback loop is implemented by means of a classical configuration using a TL431 (U3) to adjust the current in the optocoupler TLP621 (U2). Weighted resistive dividers from both voltages are summed at the reference node of the TL431 in order to achieve a1 Please note that EMI measurements have not been performed on this evaluation board. The primary goal of this board is to verify the functionality of the IRS27951 controller IC.2 A fan is recommended whenever operating at the maximum load for a prolonged period of time.Rev. 4.0 5/22/2010 International Rectifier Page 4 of 16 PROPRIETARY INFORMATION - This document and the information contained therein are proprietary and are not to be reproduced, used or disclosedRev. 4.0 5/22/2010International RectifierPage 6 of 16PROPRIETARY INFORMATION - This document and the information contained therein are proprietary and are not to be reproduced, used or disclosed 3.3 Evaluation Board PictureFigure 2 – Evaluation Board Photo3.4 Board Component Placement3.5 Board PCB LayoutRev. 4.0 5/22/2010 International Rectifier Page 7 of 16 PROPRIETARY INFORMATION - This document and the information contained therein are proprietary and are not to be reproduced, used or disclosed3.6 Bill of MaterialsRev. 4.0 5/22/2010 International Rectifier Page 8 of 16 PROPRIETARY INFORMATION - This document and the information contained therein are proprietary and are not to be reproduced, used or disclosed4 EVALUATION BOARD OPERATING PROCEDURECAUTION: Potentially lethal voltages exist on this demo board when powered up. Improper or unsafe handling of this board may result in serious injury or death.Figure 5 - Recommended Evaluation Board Test Setup4.1 Load ConnectionConnect a resistive or electronic load, capable of 150W continuous power on the 24V rail to connector JP4 and a 75W continuous power load on the 12V output rail to JP5. Please note that there is no minimum load3 requirement for this board.3 A minimum load has been added on both the output rails to ensure tight voltage regulation for both output rails from no load to full load.Rev. 4.0 5/22/2010 International Rectifier Page 9 of 16 PROPRIETARY INFORMATION - This document and the information contained therein are proprietary and are not to be reproduced, used or disclosed4.2 AC/DC InputThe use of an isolation transformer on the AC side is highly recommended, so that all the control signals on the test points can easily be probed by using regular scope probesConnect a 60Hz AC power source capable of operation up to 280VAC or a 400V DC source to JP1. The converter can keep the output regulated when the BUS voltage is in the range of 350V DC to 420V DC.The NTC resistor limits the inrush current upon initial application of full AC line voltage. Once power is applied to demo board, potentially lethal high voltages will be present on board and necessary precautions should be taken to avoid serious injury.4.3 IRS27951 DC Supply VoltageThe board is self-supplied by startup circuit and auxiliary winding of transformer. The startup circuit starts to work once AC or DC input voltage applies to the board. However, the Vcc will be stable only when BUS voltage is 350Vdc or above. The VCC voltage is monitored at test points VCC and COM.If you choose to supply VCC voltage using external DC power supply (in order to study IC VCC UVLO features etc.) then simply provide DC voltage to connector JP3 or alternatively between Test Points V CC and COM. You should also dis-connect Rvcc and Rstart in order to measure the Vcc supply current from the DC source. The minimum supply voltage recommended is 12V while a maximum voltage of 18V can be applied without damaging the IC. The location of the DC power connector and controller IC is shown in Figure 6.IRS27951 and controlcomponents onbottom layerVCC COMFigure 6 - VCC connector and test points4.4 Power-up SequenceOnce all the connections are made, the system can be powered up. When using external DC supply to bias Vcc, power-up the AC supply or 400V DC supply first and then the Vcc circuitry. This sequence is necessary to ensure soft start operation of the DC-DC converter.Rev. 4.0 5/22/2010 International Rectifier Page 10 of 16 PROPRIETARY INFORMATION - This document and the information contained therein are proprietary and are not to be reproduced, used or disclosedRev. 4.0 5/22/2010 International Rectifier Page 11 of 16PROPRIETARY INFORMATION - This document and the information contained therein are proprietary and are not to be reproduced, used or disclosed 5 SYSTEM PERFORMANCE CHARACTERIZATIONTest Conditions – V IN=400V DC; Full Load (24V/6A, 12V/6A); No Load (24V/0A, 12V/0A)5.1 Steady-State and Start-up WaveformsCh 1: Low-side device VGS – : Voltage at VS pin: Resonant tank currentFull Load Operation No Load OperationFull Load Start-up No Load Start-upRev. 4.0 5/22/2010 International Rectifier Page 12 of 16PROPRIETARY INFORMATION - This document and the information contained therein are proprietary and are not to be reproduced, used or disclosed 5.2 Short Circuit ProtectionIRS27951 uses high-voltage technology to sense the current in the low-side MOSFET. The voltage at the VS node is sensed when the low-side device is turned ON and the system shuts off when a load short-circuit condition is sensed (i.e. I D *R DSON exceeds the fixed internal threshold). Inthis reference design,IRS27951 latched shutdown when primary current exceed 8.9A peak.: 12V Rail Output Voltage : 12V Rail Output Voltage : Resonant tank current24V Rail short-circuit12V Rail short circuitRev. 4.0 5/22/2010 International Rectifier Page 13 of 16PROPRIETARY INFORMATION - This document and the information contained therein are proprietary and are not to be reproduced, used or disclosed5.3 Dynamic Load Response & Output Voltage RegulationA load step from full load to no load and no load to full load was applied to test the dynamic response of the system. The output voltage is tightly regulated within a 3% regulation band over the entire line load range. A summary of the load performance is also shown below.: 24V Rail output voltage : 12V Rail output voltage: Resonant tank currentNo Load to Full Load StepFull Load to No Load Step23.423.623.82424.224.424.611.811.8511.911.951212.0512.112.1512.20123456V o u t (V )Iout (A)Load Regulation12V Output 24V OutputFigure 7 - Output voltage regulation plotRev. 4.0 5/22/2010International RectifierPage 14 of 16PROPRIETARY INFORMATION - This document and the information contained therein are proprietary and are not to be reproduced, used or disclosed5.4 User Initiated SLEEP ModeThe CT/SD pin of IRS27951 can be used to disablethe IC and enter sleep mode in which the IC power consumption is highly minimized. The IC enters this mode when the CT/SD pin is externally pulled to COM. This feature facilitates the implementation of system power management functions for reducing overall standby power consumption by disabling the down converter when no power is being requested by the converter main output voltage rails.Ch 1: Low-side device V GS Ch 2: CT/SD pin of IRS27951 Ch 3: High-side device V GS Ch 4: Resonant tank currentSleep mode initiated by externally pulling the CT/SD pin to COM5.5 Efficiency ChartThe efficiency of IRS27951 demo board was tested at both 270Vac input and 400Vdc input over the load range. The result is shown in the table below.270Vac 400Vdc24Vout 24V current(A) 12Vout 12V current (A) Pout(W) Efficiency Efficiency 24.176 1.5 11.97 1.5 54.2 90.8% 91.0% 24.2 3 11.92 3 108.4 92.6% 92.6% 24.22 4.5 11.9 4.5 162.5 92.4% 92.9% 24.24 6 11.86 6 216.6 92.2% 92.7% 23.517 6 12.26 0 141.1 92.8% 24.814 0 11.63 6 69.8 89.5%Rev. 4.0 5/22/2010 International Rectifier Page 15 of 16PROPRIETARY INFORMATION - This document and the information contained therein are proprietary and are not to be reproduced, used or disclosedThe average efficiency of the board at 25%, 50%, 75% and 100% load is 92% at 270Vac input:90.5%91.0%91.5%92.0%92.5%93.0%93.5%50.070.090.0110.0130.0150.0170.0190.0210.0E f f i c i e n c yOutput Power (W)Efficieny vs. Output Power400Vdc input 270Vac inputFigure 8 - Efficiency plot5.6 Thermal DataThe thermal performance of IRS27951 demo board is tested at 400Vdc input and 220W full load under room temperature.Part Case Temperature (°C) MOSFET Q1 44.5 MOSFET Q2 42.5 U1 IRS27951 41 Transformer 73 24V diodes 72 12V diodes 606 Transformer SpecCore type: ETD49 - 0R44949EC Minimum operating frequency: 80 kHzPrimary inductance: 585 µH ±10% @1 kHz - 0.25V (Note 1) Leakage inductance: 125 µH ±10% @1 kHz - 0.25V (Note 2)Note: 1 Measured between Pins 2 and 5Note: 2 Measured between Pins 2 and 5 with secondary windings shortedRev. 4.0 5/22/2010 International Rectifier Page 16 of 16PROPRIETARY INFORMATION - This document and the information contained therein are proprietary and are not to be reproduced, used or disclosed 6.1 Electrical Diagram97141720111319251812TXNote: pin19 is shorted to pin18 on PCB, pin13 is shorted to pin12 on PCB.6.2 Resonant Transformer Winding Position on Coil former6.3 Resonant Transformer Winding CharacteristicsPins Winding Turn numberRMS CurrentWire type [mm] 2 - 5 Primary 36 1.8A LITZ - dia. 0.15x309 - 7 Auxiliary 2 0.1A Dia. 0.2 20 – 19 Sec. A 4 7A LITZ - dia. 0.20x40 18 - 17 Sec. B 4 7A LITZ - dia. 0.20x40 14 – 13 Sec. C 2 7A LITZ - dia. 0.20x40 12 - 11Sec. D27ALITZ - dia. 0.20x40PrimarAuxiliarySec A Sec BSec CSec D。
UVM1.1应用指南及源代码分析_20111211版
6.2. 强大的config .............................................................................................94
6.3. 聚合config变量 .........................................................................................98
写这本书,只是想把自己会的一点东西完全的落于纸上。在努力学习 UVM 的 过程中,自己花费了很多时间和精力。我只想把学习的心得记录下来,希望能够给 后来的人以启发。如果这本书能够给一个人带来一点点的帮助,那么我的努力就不 算是白费。
这本书的前半部分(第 1 到第 9 章)介绍了 UVM 的使用,其用户群较为广泛;
8.2. 搭建一个简单的register model...............................................................129
8.3. 复杂的register model...............................................................................137
函数索引609xvi图目录图11uvm在数字电路设计中的位置3图12uvm对systemverilog的封装4图13简单验证平台5图14uvm验证平台的树形结构6图15实际验证平台7图16packbytes和unpackbytes14图17uvm验证平台中的agent181图21完整的uvm树35图22uvm中常用类的继承关系37图31uvm中的常用phase47图32uvm中所有的phase50图33两个driver位于同一domain57图34两个driver位于不同的domain58图41穿梭的transaction60图51defaultsequence的设置与启动77图52sequencer与driver之间的通信80图53virtualsequence的使用85图61半全局变量93图71monitor与scoreboard的通信104图72使用public成员变量实现通信105图73put操作106图74get操作106xvii图75transport操作107图76component在端口通信中的作用109图77connect关系的建立110图78port与imp的连接111图79portexport与imp的连接115图710使用fifo连接component122图81uvmregfield和uvmreg126图82使用registermodel读取寄存器的流程128图83uvmregfield
Circular Chart Recorder Model C1492 商品说明书
Circular Chart RecorderModel C1492I 1 to 3 pen versions–for all your recording requirementsI Dedicated Flow version–to record and totalize; one batched and one secure totalizer per channel I Universal process inputs – THC, RTD, V, mV, and mA I 0.25% measurement accuracy –reliable recordingI Clear vacuum fluorescent display–with units of measure and channel identifier I Up to 6 alarm relays–high/low process, 3-state or latching I 2-wire transmitter power supply –power for all inputsC1492…the ideal solution for yourrecording needsData SheetSS/1492_2Circular Chart Recorder Model C1492SS/1492_22Model C1492 Circular Chart RecorderDisplays and ControlsThe C1492 is available as a one-, two-, or three-channel recorder, offering up to 6 output relays, allocated to six set points, which can be used on any channel or channels.24V DC power supply modules can be fitted for use with two-wire field transmitters.Also available are isolated retransmission output modules which can be added to any channel without change of software.The C1492 can be supplied for flow indication and recording with totalization available on all channels.Displays and ControlsThe display is a blue-filtered, 20-character, single-line 5 x 7 dot matrix, vacuum fluorescent type. In general use the input value and units of measurement are displayed sequentially for each channel.During programming of the instrument the display provides easily read prompts, together with program variables. The clarity of these prompts reduces dependency on the instruction manual.Alarm state is indicated by a red/green l.e.d. for each set point.These l.e.d.s are visible through the window in the door and can be programmed to indicate the required color when the input signal is above or below the set point.All output relays can be programmed to be either energized or de-energized in the alarm condition in an on/off, latch or 3-state mode.Control Panel DetailsUnits of MeasureIn addition to the 156 standard units of measurement programmed into the recorder (e.g. °C, °F, l/h, pH), further units,up to six characters in length, may be entered into the program by the user.Programming the instrument is carried out by the operation of a sequence of tactile membrane switches: three ‘Scroll’ switches in conjunction with ‘Up’, ‘Down’, ‘Decimal Point’ and ‘Enter’switches. A further switch is used to raise & lower the pens for pen and chart replacement.Circular Chart Recorder Model C1492SS/1492_23Flow OptionsThe C1492 is available for flow indication and recording with totalization on all channels. Input signals can be linear or square law analog.x 3/2 or x 5/2 linearization is included in the standard software package. Any analog flow input channel may be changed from a totalizer to a standard version accepting analog signals for other measurements simply by programming the flow total to 'off'.Secure TotalsEach flow channel has two totalizers, one of which can be used for a batch total, resetable from the front panel and displayed in sequence with flow rate. The other is used for display of a secure total, accessible only by operating the appropriate channel select buttons.Both totals are protected in the memory for up to ten years in the event of power failure.For applications requiring a remote counter, a relay module with volt-free contacts can be fitted.The totalizers can be programmed to count either up or down. A ‘wrap around ’ feature enables the totalizer to count to a predetermined value and then reset to a preset value. A relay, or relays, can be allocated to the ‘wrap ’ feature, energizing for 1second at the predetermined value.SpecificationAccuracyIntrinsic error±0.25% span max. for all zero-based ranges within reference conditions 68°F and 115V or 230V supply Linearizer accuracy ±0.18°F typical Electrical Limits)s t u p n I e r u t a r e p m e T (t u p n I ep y T ti e h n e r h a F s e e r g e D .p m e T t r a t S .n i M na p S .n i M .p m e T .x a M se l p u o c o m r e h T 485C E I d n a n o C /e F 01734N I D n o C /e F 485C E I d n a l A i N /r C i N 485C E I d n a h R t P /t P 485C E I d n a i N u C /u C 485C E I d n a i N u C /r C i N 485C E I d n a h R %03t P iS i N /i S r C i N J L K S &R T E B N 841–841–841–0814–841–0823–0810810720801)e v +(612)e v –(6030810891)e v +(4232561256127322903075056127232732re t e m o m r e h T e c n a t s i s e R 001t P 823–092111ResolutionMeasurementmV, V, mA, THC≥0.1% span for all zero-based ranges within permitted limits RTD 0.06ΩPen≤0.1% full scale travel Display±1 digit (in –999 to 3300)Pen response time 6s for 0 to 100% typicalTemperature Limitse p y T t u p n I l a c i r t c e l E ()s t u p n I t r a t S .n i M e u l a V n a p S .n i M n a p S .x a M e g n a R d n a e u l a V s t l o v i l l i M s t l o V s p m a i l l i M ec n a t s i s e R 999–0.02–9.99–0.02–00.505.005.00.0200010.020.0010002Circular Chart Recorder Model C1492SS/1492_24…SpecificationAnalog InputsNo. of inputs 1, 2 or 3Broken sensor detectionProgrammable, upscale or downscale drive or none LinearizationProgrammable for all inputs – linear, square root, power 3/2,5/2 law, or type of thermocouple, or resistance thermometer Filter TimeProgrammable from 0 to 60s in 1s steps Change of input mode By repositioning plug-in link Change of input range/span Programmable via front panel Program modificationBy user-operated switches above chart Floating inputs isolation12.5V max. between channels(upon removal of terminal block links)Insulation inputs to earth 500V DC Input Resistance Millivolt inputs >10M ΩVoltage inputs 500k Ω min.Current inputs10ΩDisplays and RecordsDisplay20-character, alpha-numeric, dot-matrix, vacuum fluorescent with blue filter 5mm (0.196 in. characters)ProgrammingUp, down and 'scroll' switches above chart Chart – 250mm (10 in.)Circular with linear graduations. Specify the chart rotation time,graduations and chart number if known.Chart speed1 rev. per hour up to 1 rev. per week (168h) programmable in 1hour steps PensRed, channel 1. Green, channel 2. Blue, channel 3Environmental DataOperating temperature limits 32 to 131°FOperating humidity limits0 to 80% RH (paper and ink system)0 to 95% RH (electronics)Error due to ambient temperature variation ±0.01% span/°F typical (unsuppressed ranges)Protection rating NEMA 3EMC and SafetyEmissionsMeets requirements of EN 50081-2ImmunityMeets requirements of EN 50082-2Design and Manufacturing Standard CE markCSA General Safety Approved UL General Safety Approved Electrical Safety EN 61010-1Power SuppliesVoltage requirement110V AC (93V min. 127V max.) 50/60Hz 230V AC (195V min. 265V max.) 50/60Hz Alternatively, 10 to 30V DC Power requirement <28VAError due to power supply voltage variation ±0.1% span for ±15% variation in supply Line interruption<110ms loss, no effect,>110ms loss, instrument returns to operation after automatic reset Common mode<1% span error max. for 250V RMS 50Hz Series mode<1% span error for 200% span, 50HzTransmitter Power SupplyOutput voltage25V ±0.5V at 0 or 60mA (loaded with 3 transmitters)Output ripple100mV peak-to-peak max.Regulation±0.1V for output change 4 to 20mAOutput voltage variation with supply voltage <0.1V for ±15% supply voltageCircular Chart Recorder Model C1492SS/1492_25Alarms and RetransmissionAlarmsNo. of set points Up to 2 per channel Trip point adjustment Programmable No. of relaysUp to 2 per channel Relay contactsSingle pole changeover Rating250V AC 5A (non-inductive)1250VA 250V DC 5A (non-inductive)50WRetransmissionOutputsOutput modules are isolated. The maximum isolation voltage is 1000V between input and outputProgrammable min. (zero) and max. (full scale) values from 0 to 20.0mA in 0.1mA steps. Max. load 1k ΩMechanical DataMountingWall or panel by 3 brackets, supplied as standard kit Optional accessories Part No.Door seal moisture shield PX105/0111Carrying stand assembly P105M/0340(complete with cover)Overall dimensions14.56 in. wide x 14.17 in. high x 6.7 in. deep Panel cutout Specification for Flow Input VersionsGeneralFlow totalProgrammable ON or OFF Count rate zeroProgrammable from 0 to 0.999 in 0.001 pps steps then 1.00 to 9.99 in 0.01pps steps Count rate full scaleProgrammable from 0.001 to 0.999 then 1.00 to 10.00 pps Count rate cut offTotalization can be stopped if flow rate falls below preset value.Preset value adjustable over full span, programmable in 1% steps CountIncrease or decrease WrapProgrammable predetermined and preset valuesAnalog InputsMathematical linearizer accuracy √x –0 to 100%0.1% of reading x 3/2 –7 to 100%0.2% of readingx 5/2 –18 to 100%0.3% of readingBelow these values the error increases asymptotically as the input approaches zero+0.04+0.0413.7in. x 13.46in.–0–0Panel space requirement16.14 in. wide x 15.74 in. high, 5.90 in. deep from panel face Case and doorSheet steel case with hinged chart plate. Foam-moulded door with glass window (or polycarbonate to special order)Weight 23 lb approx.Circular Chart Recorder Model C1492SS/1492_26Electrical Connectionsno i t a t o R r u o H 42n o i t a t o R y a D 7e g n a R .o N t r a h C e g n a R .o N t r a h C e g n a R .o N t r a h C e g n a R .o N t r a h C e g n a R .o N t r a h C 001+o t 001–05+o t 05–001+o t 05–52+o t 52–51+o t 51–64215521934140656501o t 041o t 051o t 002o t 052o t 003o t 004o t 005o t 006o t 008o t 0001o t 0021o t 0051o t 0002o t 0052o t 0003o t 0004o t 0005o t 0006o t 07351631903135112251350364157955450155154655411525585045055046008o t 00001o t 00021o t 00002o t 00052o t 00003o t 00004o t 000001o t 0001o t 02021o t 02051o t 05652245553403484185612607633611226201o t 041o t 002o t 052o t 003o t 004o t 005o t 006o t 008o t 0001o t 0002o t 0052o t 0003o t 0004o t 0006o t 0008o t 00001o t 0001o t 02021o t 0210635310931553175320450460616410140265263211434613197471313294311001+o t 001–05+o t 05–051+o t 05–52+o t 52–0121852175312031Supply ConnectionsModule ConnectionsChart ExamplesCircular Chart Recorder Model C1492SS/1492_27le n n a h c r e P **Ordering InformationCircular Chart Recorder Model C1492SS/1492_2S S /C 1492I s s u e 2ABB Inc.125 E. County Line Road Warminster, PA 18974USATel:+1 215 674 6000Fax:+1 215 674 7183ABB LimitedHoward Road, St. Neots Cambridgeshire, PE19 8EU UKTel:+44 (0)1480 475321Fax:+44 (0)1480 217948ABB has Sales & Customer Supportexpertise in over 100 countries worldwide The Company ’s policy is one of continuous product improvement and the right is reserved to modify theinformation contained herein without notice.Printed in UK (04.03)© ABB 2003。
WaveBook 516E、WaveBook 516、WaveBook 516A、WaveBook
WBK10A Analog Expansion Module Important Notice! WaveBook/516E UsersWBK option cards for WaveBook/516E are installed at the factory per customer order.Users are not to remove or install cards for these products as the cards are not “plug-and-play” for these devices and erroneous signal values could result. If you desire to removeor add a card to WaveBook/516E contact the factory or your service representative.Important Notice! WaveBook/516, /516A, /512A, and WBK10A UsersWith exception of the WBK30 option, WBK option cards for WaveBook/516, /516A,/512A, and WBK10A are installed at the factory per customer order. Users are not toremove or install cards for these products [other than WBK30 series cards] as the cardsare not “plug-and-play” for these devices and erroneous signal values could result. If youdesire to remove or add a card to these products, contact the factory or your servicerepresentative.The WBK10A Analog Expansion Module can be used to provide WaveBook with 8 additional differential-analog-inputs. The WBK10A is equipped with a programmable gain instrumentation amplifier (PGA) and,like the WaveBook, has a built-in expansion bus.Up to eight WBK10A modules can be cascaded together for a system capacity of 72 differential channels.Each module is capable of supporting a WBK11A, WBK12A, or WBK13A option card.Note: WBK10A can be ordered with a PGA, WBK11A, WBK12A, or a WBK13A card installed.WBK10A Block DiagramThe front panel has the following connectors and indicators:• 1 Analog Common binding post for reference.•8 BNC connectors for analog inputs. Channels are labeled 1 through 8.• 3 Status LEDs (Active, Ready, Power).The rear panel has a power switch and the following connectors:• 2 DIN5 connectors [one for Power In, one for Power Out]• 1 HD-15M Expansion Control In• 1 HD-15F Expansion Control Out• 2 BNC connectors [one for analog Expansion Signal In,one for analog Expansion Signal Out]Reference Notes:➣Setup information pertaining to power, expansion control, and expansion signal connections is contained in the System Setup and Power Options chapter of the WaveBook User’sManual (p/n 489-0901).➣For detailed WaveView information, refer to the WaveView Document Module that is included on the data acquisition CD. The document can be accessed using the<View PDFs> button on the CD’s opening screen.Specifications - WaveBook/516, /516A, /516E, and WBK10AAnalog SpecificationsFor either a stand alone WaveBook, or for a WBK10A with a WaveBookChannel Capacity:WaveBook/516E: 8 built-in voltage channels, expandable up to 72 channels via WBK options. In addition, WaveBook/516E can accommodate up to 3 WaveBook/516A, /512A, or WBK40 options, in any combination. Each added on WaveBook canbe expanded up to 72 channels. The maximum WBK41 capacity is 224 T/C channels, 4 analog output channels, 272digital I/O channels, and 6 counter/timer channels.WaveBook/516 and /516A: 8 differential, expandable up to 72 differentialBNC Input Connectors: Center conductor is Channel Hi, outer conductor is Channel LowInput Voltage Ranges (DC Specifications)Standard Unit With WBK11A (Note 3)With WBK12A/13A (Note 3)VoltageRange Accuracy (Note 2)One Year, 18-28°C Input NoiseLSB rmsDC-500KHz(typical)Accuracy (Note 2)One Year, 18-28°CInput NoiseLSB rmsDC-500KHz(typical)Accuracy (Note 2)One Year, 18-28°CInput NoiseLSB rms(typical)±% reading±%range±%reading±%range±%reading±%range1KHzFilterFilterBypass0 to +10V.012%.008%2.012%.008%2.012%.008% 2.2 2.2 0 to +5V (10A)0 to +4V (516).012%.009%2.012%.009%2.012%.009% 2.2 2.20 to +2V.012%.012%3.012%.012%3.012%.012% 2.23 0 to +1V(10A only).012%.018%3.012%.018%3.012%.018% 2.23 0 to +.5V.018%.033%6.018%.033% 2.26 0 to +.2V.018%.08%8.018%.08% 2.212 0 to +.1V.018%.16%15.018%.16% 2.220 -10 to +10V.012%.008%2.012%.008%2.012%.008% 2.2 2.2 -5 to +5V.012%.008%2.012%.008%2.012%.008% 2.2 2.2 -2 to +2V.012%.009%2.012%.009%2.012%.009% 2.23 -1 to +1V.018%.012%3.018%.012%3.018%.012% 2.2 3.3 -.5 to +.5V(10A only).018%.018%5.018%.018%6.018%.018% 2.26 -.2 to +.2V.018%.033%8.018%.033% 2.212 -.1 to +.1V.018%.08%15.018%.08% 2.220 -.05 to +.05V(10A only).018%.16%26.018%.16%440Notes: 1. Specifications assume differential input scan, unfiltered.2. Accuracy specification is exclusive of noise.3. Unipolar ranges are not available for WaveBook/516, /516A, or /516E when a WBK11A, WBK12A,or WBK13A option is installed. Unipolar ranges are available with WBK10A and any option.System Performance:one year, 18-28°C unless otherwise notedDifferential Nonlinearity:±2 LSB maxTotal Harmonic Distortion (10Hz-20KHz): -84dB typicalSignal to Noise and Distortion (SINAD, 10Hz-20KHz): -74dB typicalTemperature Coefficient of Accuracy (0-18 and 28-50°C):With PGA and WBK11A:± (.002% + 0.6 LSB)/°C typical, -10 to +10V rangeWith WBK12A/13A:± (.002% + 1 LSB)/°C typical, -10 to +10V rangeInput Resistance: 5MΩ (single ended); 10MΩ (differential), in parallel with 30pFBias Current: <400 nA (0 to 35°C)Common Mode Rejection: >70dB minimum; >80dB typical; DC-20KHzInput Bandwidth:DC to 500KHzHostile Channel-to-channel Crosstalk (5Vrms input signal, DC-100KHz):-88dB typicalOver-Voltage Protection: ±35 V relative to analog commonNote: Specifications are subject to change without notice.PGA FilterFilter Type: 20KHz low pass, Butterworth, 5-pole filterWBK11A FunctionsInput Voltage Ranges:Software programmable prior to a scan sequenceAperture Uncertainty (SSH): 75ps maxVoltage Droop (SSH): 0.01mV/ms typWBK12A, WBK13A FunctionsInput Voltage Ranges:Software programmable prior to a scan sequenceLow Pass Filter Type: Software selectable, 8-Pole elliptic or linear phaseAnti-Aliasing Filters: Single-pole pre and post filters, automatically set depending on filter frequency selectedLow-Pass Filter Frequency Cutoff Range: 100KHz, 75KHz, 60KHz…400Hz, bypass (fc=300KHz/N whereN=3 to 750Filter Grouping: 4 Channels each in two programmable banksAperture Uncertainty (SSH): 75ps maxVoltage Droop (SSH): 0.01mV/ms typTriggeringChannel 1 Analog TriggerInput Signal Range:-10 to +10VInput Characteristics and Protection:Same as channel inputsLatency: 300nsMulti-Channel Analog Trigger (up to 72 channels):Range: Selectable per channel to input rangeLatency: 2us/channel, plus 4us maximumTTL Trigger:Input Signal Range: 0-5VInput Characteristics: TTL-compatible with 10K ohm pull-up resistorInput Protection:Zener clamped –0.7 to +5VLatency: 300nsSoftware TriggerLatency:100us typicalPulse TriggerInput Signal Range:0-5VInput Characteristics: 75 ohmsInput Protection:±10V maximumMinimum Pulse Width: 100nsLatency: 300nsExternal ClockConnector:Available on DB25 digital inputInput Signal Range:5V TTL compatibleInput Characteristics:50K ohms pull up (to +5V) in parallel with 50pFInput Protection:Zener clamped –0.7 to +5VDelay: 200nsSignal Slew Rate Requirement:20V/us minimumRate:Up to 1MHzDivisor ratio:Divide by 1 through 255, selectableClock Counter Accuracy:<0.02% errorClock Counter Range:0.01Hz to 100KHzSequencerOperation:Programmable for channel, gain, and for unipolar/bipolar range in random orderDepth: 128 locationChannel-to-Channel Rate: 1.0-1.1us/channel, all channels equalMaximum Repeat Rate: 1MHzMinimum Repeat Rate: 100 seconds per scanExpansion Channel Sample Rate: Same as on-board channelsHigh-Speed Digital Inputs/General-Purpose OutputsConnector:DB25 FemaleConfiguration:16 TTL-compatible pins, selectable for input or outputInput Characteristics:TTL-compatibleOutput Characteristics:ALS TTL output in series with 33 ohmsOutput Updates: Outputs may be changed via program controlInput/Output Protection:Diode clamped to ground and +5VPeriod CounterOperation: Internal counter calculates and reports the external clock’s period;counter can be read with each scanClock Counter Accuracy: <0.02% errorClock Counter Range: 0.01 Hz to 100 kHzGeneral SpecificationsWarm-up:30 minutes to rated specificationsEnvironment:Operating:0-50°C, 0-95% RH (non-condensing)Storage:-20 to 70°CPower Consumption:/516E: 1.8A max @ 15 VDC/516, /516A & /512A: 1.4A max @ 15VDCInput Power Range: 10 VDC to 30 VDCInput Power Fuse F201: 4A MINI ATO; See chapter 9 for fuse replacement instructions.Vibration:MIL STD 810E, Category 1 and 10PC Communication:/516E: 10/100BaseT Ethernet/516, /516A & /512A:Enhanced Parallel Port (EPP)Channel Capacity:/516E: 8 built-in voltage channels, expandable up to 72 channels via WBK options. Inaddition, WaveBook/516E can accommodate up to 3 WaveBook/516A, /512A, orWBK40 options, in any combination. Each added on WaveBook can be expandedup to 72 channels. The maximum WBK41 capacity is 224 T/C channels, 4 analogoutput channels, 272 digital I/O channels, and 6 counter/timer channels./516, /516A & /512A:8 built-in voltage channels, expandable up to 72 channels via WBKoptionsDimensions:/516E: 285 mm wide x 220 mm deep x 70 mm high (11 x 8.5 x 2.70 inches)/516, /516A & /512A:285 mm wide x 220 deep x 45 mm high (11 x 8.5 x 1.75 inches) Weight:/516E: 1.9 kg (4.2 lbs)/516, /516A & /512A: 1.5 kg (3.3 lbs)。
公差分析表格
ANALYSIS SUMMARY
Prepared For: Prepared By: Report Date: Yu Jichang Phone: Phone: DTS NUMBER: 021-28919445 REQUIREMENT DESCRIPTION: NOM LSL USL Year: Program:
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Gravity Bias
< 返回首页 公差分析表格 dimensionalmanagement analysis summary prepared phone:dts number: prepared yujichang phone: 021-28919445 report date: requirement description: nom lsl usl meas.type subject: year: program: part/processdescription tol. source tolerance est contributionlwr lim upr lim 1011 12 gravitybias direction assumptions:results rigidparts normallydistributed sigmatolerances centerednominals. nominal mean shift allpart features assumedwithin spec 3srss variation result processcapability equal specrange 4s rss variation result geometricallylinear result,limit stack graphicaloutput unlessnoted calculatedtrigonometrically. welddistortion, thermal growth, bending edmundoreyes vega springback considered.dimensional gmm inputdata blueedmundo.reyesvega@ 8-950-5662status key: green 0-5%red >5%report number: rev 002 (oct04) revision level: 0.80.6 0.4 0.2 dimensionalmanagement analysis summary prepared phone:dts number: prepared yujichang phone: 021-28919445 report date: requirement description: nom lsl usl me
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Requirement of a 5Ј-Proximal Linear Sequence on Minus Strands for Plus-Strand Synthesisof a Satellite RNA Associated with Turnip Crinkle VirusHancheng Guan,Clifford D.Carpenter,and Anne E.Simon 1Department of Biochemistry and Molecular Biology and Program in Molecular and Cellular Biology,University of Massachusetts,Amherst,Massachusetts 01003Received August 9,1999;returned to author for revision September 10,1999;accepted December 16,1999Viral RNA replication begins with specific recognition of cis -acting RNA elements by the viral RNA-dependent RNA polymerase (RdRp)and/or associated host factors.A short RNA element (3Ј-AACCCCUGGGAGGC)located 41bases from the 5Јend of minus strands of satellite RNA C (satC),a 356-base subviral RNA naturally associated with turnip crinkle virus (TCV),was previously identified as important for plus-strand synthesis using an in vitro RdRp assay (H.Guan,C.Song,A.E.Simon,1997,RNA 3,1401–1412).To examine the functional significance of this element in RNA replication,mutations were introduced into the consecutive C residues in the element.A single mutation of the 3Ј-most C residue resulted in undetectable levels of satC plus strands when transcripts were assayed in protoplasts and suppressed transcription directed by the element in vitro.However,satC minus strands were detectable at 6h postinoculation (hpi)of protoplasts,accumulating to about 10%of wild-type levels at 24hpi.This mutation,when in the plus-sense orientation,had little or no effect on minus-strand synthesis from full-length satC plus strands in vitro,suggesting that the 5Ј-proximal RNA element is required for satC plus-strand synthesis.In addition,in vivo genetic selection revealed a strict requirement for 10of the 14nucleotides of the element,indicating that the primary sequence is essential for RNA accumulation.©2000Academic PressINTRODUCTIONReplication of positive-sense RNA viruses proceeds through complementary minus-strand intermediates,which in turn serve as templates for plus-strand RNA synthesis.This process requires both cis -acting signals located on viral RNA molecules and trans -acting factors such as virus-encoded RNA-dependent RNA polymerase (RdRp)and host proteins (Buck,1996;Lai,1998).A wide variety of cis -acting promoter elements,rang-ing from short linear sequences to extensive multiple stem-loop structures,are recognized by RdRp.For exam-ple,brome mosaic virus (BMV)has three different types of promoters:a tRNA-like structure at the 3Јend of the genomic RNAs that contains elements required for mi-nus-strand synthesis,a promoter located at the 3Јtermi-nus of minus-strand intermediates for genomic plus-strand RNA synthesis,and an internal subgenomic RNA promoter (Dreher and Hall,1988;Marsh et al.,1988;Pogue et al.,1992;Pogue and Hall,1992;Duggal et al.,1994).Recognition of at least the subgenomic RNA core promoter by the BMV RdRp in vitro is through a se-quence-specific mechanism (Siegel et al.,1997,1998).How a single RdRp recognizes diverse linear and hairpinelements is not known,but may involve different RNA-binding sites in the RdRp or different host factors.Stud-ies with Q replicase indicate the presence of two dif-ferent RNA-binding sites responsible for the recognition of pseudoknot structures and pyrimidine-rich sequences (Brown and Gold,1995a,b).Furthermore,hairpins found in promoter regions may be present for reasons other than directing RdRp recognition.Singh and Dreher (1998)have demonstrated that specific recognition of a 3Ј-CCA triplet by the turnip yellow mosaic virus RdRp requires only an adjacent nonspecific secondary structure,indi-cating that the function of the structure is to keep the specific sequence sterically accessible to the RdRp and/or associated factors.While cis -acting signals required for RNA replication have generally been localized to the ends of virus genomic RNAs (Duggal et al.,1994;Buck,1996),internal cis -acting elements are necessary for replication of some RNA viruses including BMV (French and Ahlquist,1987;Pogue et al.,1992).For bacteriophage Q ,two internal sites are required for the synthesis of minus strands (Barrera et al.,1993)while an internal region consisting of a stem-loop structure is involved in plus-strand synthesis of a defective-interfering (DI)RNA of mouse hepatitis virus (Lin and Lai,1993;Kim and Makino,1995).An internal region in potato virus X genomic RNA participates in a long-distance interaction with terminal sequences,which is required for efficient plus-strand synthesis (Kim and Hemenway,1999).The1To whom correspondence and reprint requests should be ad-dressed at Department of Biochemistry and Molecular Biology,Univer-sity of Massachusetts,Amherst,MA 01003.Fax:(413)545-4529.E-mail:simon@.Virology 268,355–363(2000)doi:10.1006/viro.1999.0154,available online at on355function of internal cis-acting elements is not well known,but roles in RNA folding,host factor binding,and replicase assembly have been proposed(Buck,1996; Klovins et al.,1998;Kim and Hemenway,1999). Defining a complete set of elements required for rep-lication of a viral RNA is complicated by the large size of most viral RNAs.Identification of internal sequences required for replication has mainly come from studies where random,limited deletions were generated,mak-ing it likely that the majority of specific virus regions involved in replication for any given genomic RNA remain to be determined.Also complicating studies on virus replication is the link between replication and transla-tion;sequences required for translation of many viral proteins can have a substantial,but indirect,impact on replication.Turnip crinkle virus(TCV),a single-stranded positive-sense RNA virus,is naturally associated with several small subviral RNAs(Simon and Howell,1986).Since these viral-associated RNAs are not translated and are replicated by the viral RdRp,they have been very useful in studying sequences required for RNA replication (Song and Simon,1995;Guan et al.,1997;Stupina and Simon,1997;Carpenter and Simon,1998).One of the subviral RNAs,satC,is a chimeric RNA containing the sequence of a second TCV subviral RNA at its5Јend and two regions from TCV genomic RNA at its3Јend(Simon and Howell,1986).The promoter for minus-strand syn-thesis of satC is a hairpin with a single-stranded tail contained within a29-base sequence at the3Јend of the RNA(Song and Simon,1995a;Stupina and Simon,1997; Carpenter and Simon,1998).Two short elements on satC minus strands,located11bases from the3Јend(3Ј-UCCCAAAGUAU)and41bases from the5Јend(3Ј-AACCCCUGGGAGGC),were previously identified by de-letion analysis as having a role in complementary strand synthesis in vitro(Guan et al.,1997).Deletion of both elements was required to eliminate detectable comple-mentary strand synthesis,suggesting that the elementsplay a redundant role under in vitro conditions(Guan et al.,1997).When joined to the3Јend of a Qbacterio-phage-associated midivariant(MDV)RNA,which alone is not a template for the TCV RdRp,either element can direct the TCV RdRp to synthesize complementary strands in vitro with transcription initiating internally in the vicinity of the multiple C residues within the ele-ments.We now report that the5Ј-proximal element is sequence-specific and essential for satC plus-strand synthesis in vivo.RESULTS AND DISCUSSIONThe5Ј-proximal element is required for replication in vivoThe5Ј-proximal element and other sequences that can serve as TCV promoters,including the promoter for satC minus-strand synthesis and two subgenomic RNA promoters located on the viral genomic RNA,contain multiple consecutive C residues(Song and Simon, 1995a;Wang and Simon,1997;Wang et al.,1999).In addition,multiple consecutive C residues are present in a hairpin replication enhancer element located on satC minus strands,which is thought to aid in attracting the RdRp to the template(Nagy et al.,1998,1999).To deter-mine if the in vitro identified5Ј-proximal element is im-portant for satC accumulation in protoplasts,mutations were introduced into positions304to307containing four consecutive C residues(Fig.1A).Conversion of the C residue at position304(C304)to A,U,or G,either singly or in context with other alterations,eliminated detection of satC plus strands at24h postinoculation(hpi)(con-structs M1,M3,and M6-10,Fig.1B)while minus strands accumulated at10to35%of wild-type.Single-,double-, FIG.1.Mutational analysis of the5Ј-proximal element.(A)Mutations introduced into the consecutive C residues(underlined)of the element. SatC minus strand is represented by a black bar.The5Ј-proximal element is denoted by a small open box.The5Ј-proximal sequence is shown under the bar and positions with respect to location in the minus strand are indicated.Dots indicate no change of s of the constructs are shown to the left.WT,wild-type satC.(B)RNA gel-blot analysis of TCV genomic RNA(gRNA),satC plus strand[C(ϩ)],and minus strand[C(Ϫ)].To probe gRNA and C(ϩ),equal amounts of total RNA isolated from2ϫ105protoplasts at24hpi were subjected to agarose gel electrophoresis.Double-stranded RNA obtained from8ϫ105protoplasts was used to detect satC minus strands.None,no sat-RNA added.356GUAN,CARPENTER,AND SIMONand triple-base mutations introduced into the other three C residues at positions305to307reduced plus-strand accumulation of satC to20%of wild-type at24hpi(con-structs M2,M4,and M5,Fig.1B).Minus strands of these three mutants accumulated at20to30%of wild-type at this time point(Fig.1B).Since minus-strand levels at24hpi are also a reflec-tion of the level of nascent plus strands,we tested the effect of the mutations in the5Ј-proximal element region on minus-strand synthesis of satC in protoplasts at early times postinoculation(6,9,and12hpi).As shown in Fig. 2,alteration of the C residue at position307to G(con-struct M2),which reduced plus-strand accumulation to 20%of wild-type at24hpi(Fig.1),resulted in almost undetectable plus-strand accumulation at6hpi,a time point where wild-type satC plus strands were clearly detectable.Plus-strand levels of this mutant reached2.5 and10%of wild-type at9and12hpi,respectively(Figs. 2A and2B).In contrast to the barely detectable accumu-lation of plus strands at6hpi,minus strands of M2 mutant accumulated to2%of wild-type at6hpi(Figs.2A and2C).At9and12hpi,minus-strand levels increased to4and12%of wild-type,respectively.No plus strands of construct M3were detected at6,9,or12hpi(Fig.2A).In contrast,minus strands of M3accumulated at2.5,3,and 3.5%of wild-type levels at the three time points,respec-tively(Figs.2A and2C).Altogether,these results suggest that minus strands of template containing an A at posi-tion304(M3)are synthesized at a very low rate from basal levels of transfected plus strands,while further synthesis of nascent plus strands from minus-strand template is inhibited.Alteration of C304abolishes transcription directed by the5Ј-proximal element in vitroTo further explore whether alteration of C304mainly affects plus-strand synthesis,plus-and minus-strand templates containing mutations at position304were subjected to in vitro transcription using the TCV RdRp. Since full-length satC minus strands contain the3Ј-prox-imal element and either element is sufficient to direct complementary strand synthesis in vitro(Guan et al., 1997),chimeric RNAs were constructed containing the 5Ј-proximal element and downstream sequences(posi-tions284to356)of satC minus strands joined to non-template Qbacteriophage-associated MDV RNA gen-erating construct MC5Ј(Ϫ)(Fig.3A).Initiation of tran-scription for this construct is not at the3Јend of thetranscript but internally within the multiple consecutive C residues of the5Ј-proximal element,producing a com-plementary product shorter than template length(Guan et al.,1997).Since the conversion of C304to A in satC minus strands eliminated detectable plus-strand synthe-sis in vivo(Fig.1B and Fig.2A,M3),the same mutation was introduced into the chimeric construct to generate MM5Ј(Ϫ)(Fig.3A).Results obtained from in vitro tran-scription reactions indicate that the C to A change when the5Ј-proximal element is in minus-sense orientation caused a95%reduction in activity(Fig.3B).To test the mutation’s effect when in the plus-sense orientation,a second construct was generated containing positions 284to356of satC plus strands,which containsthe FIG.2.Effect of mutations in the5Ј-proximal element on satC accu-mulation in protoplasts at early times postinoculation.(A)RNA gel-blot analysis.Time points of the sampling are shown above the blots.See legend to Fig.1for other details.The relative levels of satC plus(B)and minus strands(C)were measured from the blots shown in(A)and another independent experiment.Error bars indicate standard error.357INTERNAL cis-ACTING ELEMENT ON MINUS STRANDShairpin promoter for minus-strand synthesis,connected to the 3Јend of MDV RNA (construct MC3Ј(ϩ),Fig.3A).Transcription initiating from this construct is at the 3Јend,generating a template-length product (Fig.3B).Al-teration of the analogous G residue at position 304to U reduced activity of the hairpin promoter by 30%(con-struct MM3Ј(ϩ),Fig.3B).These results suggest that the ability of the 5Ј-proximal element in the minus-sense orientation to serve as a promoter in vitro is connected to its function in vivo and that the element functions primar-ily,but possibly not exclusively,in the minus-sense ori-entation.The effect of the mutations at position 304on full-length template activity in vitro was also assayed.The TCV RdRp generated both template-sized products (T-RNA),which are synthesized by transcription initiation at the 3Јterminus of the template,and larger-than-tem-plate-length products (L-RNA)(C(Ϫ),Fig.4),which are synthesized by primer extension from the template 3Јend at an internal location (Song and Simon,1995b).Conversion of C 304to A in the 5Ј-proximal element had little or no effect on T-RNA synthesis in vitro (M3(Ϫ),Fig.4).This is likely because the minus-strand template con-tains the 3Ј-proximal element that can also direct com-plementary strand synthesis in vitro (Guan et al.,1997).However,synthesis of L-RNA and other larger-than-full-length products was markedly reduced by this mutation,suggesting that the mutation interferes with priming of RNA synthesis at internal locations.Transcription of full-length plus-strand satC template in vitro produced only template-length products (C(ϩ),Fig.4).Alteration of the G residue at position 304to U in the plus-strand RNA did not reduce template activity in vitro (M3(ϩ),Fig.4).While it is not clear what role the ability to generate L-RNA has on normal replication in vivo,these results further dem-onstrate that position 304in satC functions mainly on minus strands ofsatC.FIG.4.In vitro transcription of full-length satC plus-and minus-strand templates using TCV RdRp.M3(Ϫ)denotes satC minus strand with a C to A change at position 304.M3(ϩ)is satC plus strand containing an alteration of G to U at the same position.T-RNA,template-sized products;L-RNA,larger-than-template-length products.See legend to Fig.3.FIG.3.In vitro transcription using partially purified RdRp and chi-meric RNA templates containing a mutation at position 304of plus-and minus-strand satC.(A)Schematic representation of the chimeric RNAs derived from MDV RNA and the 5Ј-end sequence of satC minus strand or the 3Ј-end complementary sequence of satC plus strand.Black and shaded bars represent satC minus-and plus-strand sequences,re-spectively.Long open bar denotes MDV RNA (220bases).Small open box represents the 5Ј-proximal element.Hatched bar indicates the 18plasmid-derived nucleotides.The 5Ј-proximal element and the hairpin promoter for satC minus-strand synthesis are shown.Numbers indi-cate positions with respect to location in satC.Mutations introduced into position 304are s of constructs are shown to the right.Bent arrows denote the putative transcription start sites.(B)Denaturing gel analysis of 32P-labeled products synthesized in vitro.The ethidium bromide-stained gel showing the migration positions and the relative levels of the templates is shown to the left of the autora-diogram.358GUAN,CARPENTER,AND SIMONThe primary sequence of the 5Ј-proximal element is important for accumulation of satC in plantsTo further identify sequence requirements of the 5Ј-proximal element for satC accumulation in vivo,the se-quence of the element was randomized and in vivo genetic selection,also known as SELEX (Systematic Evolution of Ligands by Exponential enrichment)(Elling-ton and Szostak,1990;Tuerk and Gold,1990),was car-ried out as described under Materials and Methods.Transcripts of satC containing 14randomized bases in the 5Ј-proximal element were coinoculated onto 42tur-nip seedlings along with the TCV helper virus.Total RNA was isolated from uninoculated leaves at 21days post-inoculation (dpi).Only 2of the 42infected plants (plants 7and 11)generated satC-sized RNAs that were visible in ethidium bromide-stained agarose gels (data not shown;satC normally accumulates to a level similar to that of 5S ribosomal RNA).Although sat-RNA species were not detectable in the other plants,satC species could be cloned from all infected plants.All cloned satC-like spe-cies accumulating in 12randomly selected plants con-tained similar sequences in the 5Ј-proximal element re-gion (Table 1).The wild-type sequence was also recov-ered from one of the analyzed plants (plant 8),indicating that sufficient complexity existed in the initial random-ized population to recover the wild-type sequence.This is in contrast with the results obtained from in vivo SELEX of the 3Јend of satC minus strands,including the 3Ј-proximal element,in which no wild-type or identical sequences were generated in different plants from the first round (Guan et al.,2000).However,unlike the se-quence-specific nature of the 5Ј-proximal element (see below),little sequence conservation was found within the 3Ј-proximal element.Comparison of the recovered molecules revealed the presence of the consensus sequence 3Ј-(A/C/G)ACC-NCUGGN 1–2AGG(C/U)0–1in the 5Ј-proximal region of all cloned RNAs except those obtained from plant 19(Table 1).The bases at position N 1–2in the consensus sequence were not completely random;if one base was present at this position,it was usually a G residue.If two bases were present,they were usually a combination of AU,CG,or GA (3Јto 5Јorientation).In addition,the least conserved sequence (found in plant 19)still contained multiple C residues followed by multiple purines,which is the hallmark of the 5Ј-and 3Ј-proximal elements (Guan et al.,1997).These results suggest that alterations at only limited positions are tolerated in the 5Ј-proximal element.To subject the sat-RNA sequences to further compe-tition,equal portions of total RNA from the 12analyzed plants (pool 1)or all 42infected plants (pool 2)from the first round were combined and inoculated onto 8new plants.Three weeks after inoculation,sat-RNA species were cloned and sequenced.Clone 1-a,which differed from the wild-type sequence at only two positions in the 5Ј-proximal element and was previously identified in plant 1from the first round,was recovered from all 8plants inoculated with RNA of pool 1(Table 2).This sequence was the only species found in 7of the 8plants.TABLE 1First-Round in Vivo SelectionName Sequence aPlant b12346781011192026WT 3Ј-A ACC C CUGG G AGG C 31-a A ACC G CUGG G AGG U 51-b Ag CC G CUGG G AGG U 12-a A A U CC A CUGG G AGG 22-b A A U CC A CUG aG AGG 23-a C ACC U CUGG CG AGG 13-b C AC uc CUGG CG AGG 33-c C AC uU CUGG CG AGG 14-a G ACC A CUGG AU AGG 22511224-b a ACC A CUGG AU AGG 14-c c ACC A CUGG AU AGG 35-a A ACC U CUGG GA AGG 1135-b A ACC Ug UGG GA AGG 46-aCCUG CC A CGG U GG A2Total clones sequenced48aOnly sequences in the 5Ј-proximal element region are shown.Lowercase letters denote differences from an arbitrarily selected “parental”molecule.All the sequences,except sequence 6-a from plant 19,contain the consensus sequence,3Ј–(A/C/G)ACCNCUGGN 1–2AGG (C/U)0–1,in the 5Ј-proximal element region.The most conserved bases are shown in bold.bThe number of clones of each sequence found in the plants is indicated.359INTERNAL cis -ACTING ELEMENT ON MINUS STRANDSTwo other RNA species(1-c,which differed from se-quence1-a at one position,and3-b,which was previ-ously identified in plant3of the first round)were cloned from one of the plants(plant6).No clones containing wild-type sequence were recovered,although wild-type satC was contained in pool1from plant8(Table1).In contrast,almost all RNA molecules obtained from inoc-ulation of pool2were wild-type(Table2),suggesting that additional wild-type satC was accumulating in unana-lyzed plants of the first round.Although a single-base change of C304to U abolished plus-strand synthesis in protoplasts(M1,Fig.1),several of the SELEX sequences such as2-a,2-b,and6-a con-tained a U residue at this parison of se-quences2-a,2-b,and6-a indicates that all contained “CCNC”immediately or1base5Јof the U residue at position304.This suggests that a C residue at position 304or“CCNC”in a nearby position relative to other essential bases in the5Ј-proximal element is important for satC plus-strand synthesis.Bases in the unconserved positions of the5Ј-proximal element may also affect template activity,since a single purine in position N1–2was preferred.Sequence1-a and wild-type satC contained a G residue in this position, while the other recovered sequences had2bases at this site.An extra base in this position may affect the recog-nition of the element by the TCV RdRp and/or associated factors(see below),thus resulting in a reduction in RNA competitiveness for accumulation.Nucleotide insertions or deletions between the four key nucleotides in the BMV subgenomic RNA core promoter decrease promoter ac-tivity in vitro(Stawicki and Kao,1999).To assess whether sequence1-a or wild-type satC was more fit for accumulation,competition assays were conducted.Equal amounts of transcripts of sequence1-a and wild-type satC were used to inoculate nine plants along with TCV helper virus.Sat-RNA species were cloned at10or21dpi.These two sequences,which differ by only2bases at nonconserved positions306and315 in the element,were similarly competent for accumula-tion in plants(Table3),indicating that strict nucleotide conservation is not required at positions306or315. Computer secondary structure analysis using an algo-rithm that predicts optimal and suboptimal RNA struc-tures(Zuker et al.,1991)indicates that the5Ј-proximal element might form secondary structures with other se-quences on satC minus strands.However,replacement of C304with U or A did not affect the predicted structures. In addition,mutations disrupting the predicted structures had no effect on template activity in vitro(data not shown).Altogether,these results suggest that the pri-mary sequence,especially the10most conserved bases,of the5Ј-proximal element are important for RNA replication and/or RNA stability,possibly from recogni-tion by the RdRp or other replication factors.The pres-ence of a linear RNA element is reminiscent of the BMV subgenomic RNA core promoter,in which4of22nucle-otides(at positionsϪ17,Ϫ14,Ϫ13,andϪ11)are essen-tial for recognition by the BMV RdRp in vitro(Siegel et al., 1997,1998).Possible functions of the5Ј-proximal elementIn addition to the5Ј-proximal element and possibly the 3Ј-proximal element(Guan et al.,2000),two additionalTABLE2Second-Round in Vivo SelectionName Sequence aPool1b Pool2c 1234567812345678WT3Ј-A ACC C CUGG G AGG C65666465 1-a A ACC G CUGG G AGG U6563635421-c A ACC G C c GG G AGG U13-b C AC UC CUGG CG AGG1Total clones sequenced4046a See the legend to Table1.b RNA used for infection was pooled from the12plants analyzed in the first round.c RNA used for infection was pooled from all42infected plants from the first round.TABLE3Competition between Wild-Type satC and Sequence1-afor Accumulation in VivoName Sequence aPlant b1–31–9 10dpi21dpiWT3Ј-A ACC C CUGG G AGG C10251-a A ACC g CUGG G AGG u826Total clones sequenced1851a See the legend to Table1.b The number of clones for the sequence found in plants1–3at10dpior plants1–9at21dpi is shown.360GUAN,CARPENTER,AND SIMONsequences are known to be required for efficient accu-mulation of plus-strand satC in vivo:the3Ј-terminal se-quence(3Ј-CCCUAU)of satC minus strands known as the carmovirus consensus sequence(Guan et al.,2000) and a30-base hairpin structure called the motif1-hairpin. The motif1-hairpin is located between the3Јend and the 5Ј-proximal element in satC minus strands and is re-quired for recombination between a second TCV subviral RNA and satC(Cascone et al.,1993;Nagy and Simon, 1998;Nagy et al.,1998).In addition,the motif1-hairpin enhances satC plus-strand accumulation in protoplasts and increases transcription from the linear3Ј-proximal element by almost10-fold in vitro(Nagy et al.,1999). Based on competition experiments,the motif1-hairpin is thought to bind either the RdRp or a factor that bridges the connection between the RdRp and the RNA template (Nagy et al.,1998).The motif1-hairpin contains8bases (3Ј-CUGGGAGG)also found in the5Ј-proximal element, and thus it is possible that the5Ј-proximal element also serves as an attractor for the TCV RdRp.While the5Ј-proximal element can function as an in-dependent promoter in vitro,transcription only initiates internally at the multiple consecutive C residues within the element(Guan et al.,1997;Fig.3in this paper).It is unlikely that such initiation occurs to any great extent in vivo,since the RNAs generated would be inviable.There-fore,if the5Ј-proximal element serves as a promoter element in vivo,it must do so only within the context of sequences that help target the RdRp to the3Јend of the template.It is possible,however,that the ability of the 5Ј-proximal element to attract the RdRp,and thus serve as a promoter in vitro,is necessary to fulfill a role other than as a promoter in vivo.For example,the RdRp and/or host factors may serve as RNA chaperones to assist in folding the newly synthesized minus-strand RNA and eliminate the formation of kinetically trapped intermedi-ates(Herschlag,1995).This function would be similar to one of the two internal replicase-binding sites(M site)in QRNA that is involved in a long-range interaction with the3Јend of the bacteriophage RNA,which brings the3Јend to the bound replicase at the M site(Klovines et al., 1998).Further studies are currently underway to charac-terize the relationship between the structure of satC minus strands and the functions of the various elements required for satC plus-strand synthesis.MATERIALS AND METHODSSite-directed mutagenesis of the5Ј-proximal element Site-specific mutations were introduced into the mul-tiple C residues(positions304to307)in the5Ј-proximal element using polymerase chain reaction(PCR).The primers used in the reaction were theϪ20sequencing primer(Biolabs)and a29-mer oligonucleotide,which contains positions294to322of satC with randomized bases in positions304to307(5Ј-GGTGGGCTTT-NNNNACCCTCCGAACCAAT,the randomized bases are denoted by“N”).The template was plasmid pT7C(ϩ), which contains a full-length satC cDNA immediately downstream from a T7RNA polymerase promoter(Song and Simon,1995a).The PCR product was treated with T4 DNA polymerase,followed by digestion with Eco RI,and then ligated into Eco RI/Hin dIII-digested pUC19with a second PCR product.The second PCR product was am-plified using oligo293(5Ј-CTTTCGGGATTTTAGTGGTT, complementary to positions274to293)and theϪ48 reverse sequencing primer(Biolabs).Before ligation,this product was treated with T4DNA polymerase and di-gested with Hin dIII.All the clones contained a T7RNA polymerase promoter upstream of full-length satC con-taining site-specific mutations in positions304to307. To construct minus-sense satC containing mutations in positions304to307,the plus-sense satC cDNA mu-tants as described above were used as templates for PCR.The primers used were C5Ј(5Ј-GGGATAACTA-AGGGTTTCA,homologous to positions1to19of satC) and T7C3Ј(5Ј-GTAATACGACTCACTATAGGGCAGGC-CCCCCGTCCGA,complementary to positions338to356 of satC;the5Ј18nucleotides are the T7RNA polymerase promoter sequence).The PCR products were cloned into the Sma I site of pUC19and mutations were verified by sequencing.In vitro transcription and inoculation of Arabidopsis protoplastsPlasmids were linearized with Sma I(unless otherwise noted)and subjected to in vitro transcription using T7 RNA polymerase(Carpenter et al.,1995).The Sma I-lin-earized plasmids generated RNA transcripts containing the wild-type3Јand5Јends.Protoplasts(5ϫ106)pre-pared from Col-0callus cultures were inoculated with20g of TCV genomic RNA transcripts and2.0g of either wild-type or mutant satC transcripts as described previ-ously(Kong et al.,1997).RNA gel-blot analysisTotal RNA extracted from protoplasts at6,9,12,or24 hpi was used for RNA gel-blot analysis as previously described(Guan et al.,2000).Construction of RNA chimerasTo construct RNA chimeras,positions284to356of wild-type or mutant satC in either plus-or minus-strand orientation were joined to the3Јend of MDV RNA.cDNA fragments containing positions284to356were ampli-fied by PCR from pT7C(ϩ)or a mutant satC clone(pM2), which contains an A/T basepair in position304in place of the wild-type G/C pair.The primers used were oligo 284(5Ј-ATCCCGAAAGGGTGGGCT,homologous to posi-tions284to301)and oligo7(5Ј-GGGCAGGC-CCCCCGTCCGA,complementary to positions338to361INTERNAL cis-ACTING ELEMENT ON MINUS STRANDS。