CS6717_MYSON代理

CS6717 1.25Gbps Fiber-Optic Pre-AmplifierGENERAL DESCRIPTION CS6717 is a low noise trans-impedance amplifier designed for 1.25Gbps fiber optical applications. In typical applications, it is connected to a PIN type photo diode, and amplifies the photo current into a differential voltage output. CS6717 uses advanced CMOS process and achieves typical input sensitivity of -32dBm. control, the typical overload limit is at +4dBm. components to achieve lower noise and higher sensitivity. And with AGC CS6717 uses discrete AGC circuits that minimize the input circuit CS6717 also include on-chip decoupling capacitors for There is also monitor output that mirrors theboth PINK and VCC that can reduce TO assembly configurations.photo diode current, and the output can be selectable current sink or current source output. FEATURES● ● ● ● ● ● ●3.3V operation 50 K-Ohm differential trans-impedance gain 1000MHz bandwidth -32dBm optical sensitivity +4dBm overloadOn-chip PINK (600pF) and VCC (1100pF) decoupling capacitorAvailable as dieAPPLICATIONS● ● ● ●Fiber Channel SDH/SONET Gigabit Ethernet GEPON**This datasheet is the confidential information of MYSON CENTURY, INC. and is subject to various privileges against unauthorized disclosure. Recipient shall not disclose this confidential information to any other person, nor shall one use the confidential information for the purpose of competing with MYSON CENTURY, INC.Myson Century, Inc. No. 2, Industry East Rd. III, Science-Based Industrial Park, Hsin-Chu, Taiwan Tel: 886-3-578-4866 Fax: 886-3-578-4349 sales@ Rev. 1.1 February 2010 Page 1 of 10CS6717BLOCK DIAGRAMMON_S Default=Source 1100pFR1 1.2K R2 1.2K+PINK 600pF I_PINMONITOR CONTROLI_MONMON1 MON2OPAMPI_R2AGC REGPD Rf I_AGCPINADOUTPTIABuff1 Buff2 Buff3DOUTNI_DCRESGNDFigure-1Block Diagrampage 2 of 10CS6717PAD CONNECTION DIAGRAMY GND VCC MON DOUTP5432 1GNDPINK6 16GND950μ mPINA259um 7CS671715MON_SPINK814 13 9 10 11 12GNDGNDGNDMON 1150 μmVCCDOUTN XFigure-2 PAD LOCATION Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pad Name GND DOUTP MON VCC GND PINK PINA PINK GND MON VCC DOUTN GND GND MON_S GND X (μm) 1087.155 735.685 588.165 440.305 292.785 63 259 63 288.425 435.945 583.805 731.325 1087.155 1087.155 1087.155 1087.155Die Diagram Y (μm) 719.085 887.5 887.5 887.5 887.5 747.035 491.59 209.215 62 62 62 62 234.865 329.285 477.145 624.665Note: The coordinates start from the left bottom of the die to the center of the padpage 3 of 10CS6717Area A: total chip size in Figure 2 mentioned 1150*950 um. （including seal ring ） Area B: scribe line residue after die saw, X=17.5±2.5 um/side, Y=17.5±2.5um/side Actual size after die-saw, Max: 1190*990um, Min: 1180*980um Chip thickness: 12mil±1milCS6717 chipA Bpage 4 of 10CS6717PIN DESCRIPTION Name GND DOUTP VCC MON PINK PINA DOUTN Pin 1, 5, 9, 13, 14,16 2 4, 11 3, 10 6, 8 7 12 Description Ground pin. Connect to most negative supply voltage. Data output pin. This pin goes high when current flows into pin PINA. Power pin. Connect to most positive supply voltage. Received Signal Strength Indicator. Sinks or sources current equal to PD current. PIN Cathode bias pin. Connect to the cathode of the photodiode. Connect an external capacitor between this pin and ground. PIN Anode pin. Connect to the anode of the photodiode. Inverting data output pin. Complementary to pin DOUTP. Selects whether MON output is a current sink or source. This pin has internal MON_S 15 pull-up resistor. Leave this pin floating (internal pulled-up) will configure MON output as a current source, connecting this pin to ground will configure MON output as current sink. Note: PINA is an ESD sensitive pin. Handle with care.page 5 of 10CS6717FUNCTIONAL DESCRIPTION CS6717 is a trans-impedance pre-amplifier fabricated by CMOS process. The CS6717 consists of a trans-impedance amplifier, an output buffer, a DC restore block, a voltage regulator, an AGC block and a monitor block. Voltage Regulator and PINK bias An on-chip regulator is used to provide a clean supply voltage to the front-end amplifier. The PINK bias is supplied with an on-chip variable resistor (40K – 12K – 3.1K – 1K – 300) depending on input current level. The current switching points of the resistor are the same as the AGC switching points. The current flowing through the on-chip resistor, which is really the average current of the photo diode, is replicated by a DC-Restore OPAMP (I_R2). This current is then duplicated at PINA to compensate the DC input current and reduce the pulse distortion at the input due to DC component. There is also an on-chip PINK decoupling capacitor of 600pF, therefore external decoupling capacitor for PINK can be omitted. External capacitor can be added to increase the decoupling effect and thus may gain 0.5dBm increase in sensitivity. However, the added capacitor should not be larger than 3500pF to ensure the stability of AGC loop. Low Noise Trans-Impedance Amplifier The first stage of CS6717 is a low-noise trans-impedance amplifier. The input current is fed into an inverting amplifier with a variable feedback resistor. The feedback resistor converts the input photo current to voltage at the output node. The feedback resistance is reduced by AGC control when the input is large. The typical input referred noise current (integrated to 875MHz) is 70nA when AGC is not turned-on. AGC Block The AGC control block receive the information of the input photo-diode current level then set the trans-impedance gain accordingly. stage amplifier. The higher the input current, the lower the gain is set to prevent the overload saturation of the first The AGC defines five gain settings according to the input current as shown in Figure 3. The input Typically, for low power input, the differentialpower is calculated from 0.9A/W photo-diode conversion efficiency. trans-impedance gain is set to 52KOhm. reduced to about 16KOh, as shown in Figure 3. oscillating around the switching points.60At -16.8dBm, the first AGC step is turned on, and the trans-impedance is As the input power is increased, the following AGC switching points These AGC switching points also include hysteresis to preventare -11.5dBm, -6.3dBm, and -0.8dBm respectively.50G a in v s in p u t p o w e r Transimpedance Gain (K)403020100 -3 5 -3 0 -2 5 -2 0 -1 5 -1 0 -5 0 5I n p u t o p t ic a l p o w e r ( d B m )Figure-3TIA Gain versus Input Powerpage 6 of 10CS6717The discrete AGC simplifies the circuit of front-end low-noise amplifier so to allow better noise performance. in typical AGC design to allow more stable operation to resist noise effect. The AGC switching points are determined by the input current from the regulator, thus also avoid dual-loop time constants With AGC reducing the trans-impedance gain, CS6717 can have up to +4dBm input without overloading the front-end amplifier. Output Buffer The single-ended output of trans-impedance amplifier is converted to differential signal through output buffer stage (Figure-4). The conversion is accomplished through the extraction of the DC average level by a RC low pass filter shown in the figure. This low-pass filter 3dB frequency is set at 50KHz. The output buffer has internal pull down current sources and is able to drive 100Ohm load. The output should be AC coupled to the post-amplifier input, and Please note the external AC coupling capacitor and thetermination resistors be placed after the coupling capacitor.external termination resistor also set another 3dB lower frequency.DO UTP Single-ended Signal DO UTNFigure-4Single-ended to Differential Signal conversionBecause the discrete AGC effects described above, the output amplitude is limited when the input power is higher than the first AGC setting. Because AGC circuit is discrete, the hysteresis is needed in order to keep the circuits stable when each AGC step switches from high (low) power to low (high) power. The typical output amplitude of CS6717 is shown in Figure-5.220 200 180 160Output Swing (mV)140 120 100 80 60 40 20 -3 5 -3 0 -2 5 -2 0 -1 5 -1 0 -5 0H ig h P o w e r ~ L o w P o w e r L o w P o w e r ~ H ig h P o w e rO p t ic a l P o w e r ( d B m )Figure-5oDifferential Output Swing versus Input Power(Ta=25 C, CPD=0.5pF, data is collected by differential output with 50ohm termination).page 7 of 10CS6717Monitor Block The MON output provides a copy of the photodiode mean input current. The MON output can be configured as either a current sink or a current source to suit the application requirement. By connecting a resistor between the MON output and either VCC (+3.3 V) or ground (GND) a voltage proportional to the photodiode current can be generated. If MON_S is left open the MON output is configured as a current source. In this case the resistor RMON should be terminated to ground to develop a ground referenced voltage across it directly proportional to the photodiode mean current. If MON_S is tied to ground, the MON output is configured as a current sink and the resistor RMON should be connected to VCC (+3.3 V). The typical the input optical power to the MON output current of CS6717 is shown in Figure-6.Figure-6Monitor current versus Input Powerpage 8 of 10CS6717ABSOLUTE MAXIMUM RATINGS Symbol VCC Tstg Parameter Power Supply (VCC - GND) Storage Temperature Rating 6 -65 to +150 Unit VoCRECOMMENDED OPERATING CONDITIONS Symbol VCC TA Parameter Power Supply (VCC - GND) Operating Ambient Rating 3.0-3.6 -40 to 85 Unit VoCELECTRICAL CHARACTERISTICS Symbol VIN ICC RO G IAC,MAX IDC,MAX VDF BW BWL IN Sensitivity PIN(max) PSRR Parameter Input bias voltage Supply current Output impedance Small signal trans-impedance Input = 2uAP-P (Note 1) Maximum AC input current Maximum DC input current Maximum differential output voltage Small signal bandwidth Cutoff frequency Input referred RMS noise Optical sensitivity Optical saturation Power supply rejection ratio F < 4MHz (Note 2) -3dB Cpd = 0.5pF (Note 1) Iinput = 1mAP-P,(RL = 100,differential)ConditionMin 0.55 -Typ 0.65 22 50 52K 260 1000 50 70 -32 +4 -Max 0.75 30 100 -10Unit V mA Ω Ω mAp-p mA mV MHz KHz nA dBm dBm dBSingle ended Differential(RL = 100,differential)3.6 2 800 30Note 1. Assuming photodiode of 0.9A/W conversion, extinction ration of 10 dB and BER of 10 , CPD=0.5pF Note 2. The result is guaranteed by design simulation.page 9 of 10CS6717TYPICAL APPLICATION CIRCUITVCC 3.3VC10.1uF DINPGNDGNDVCCMONDOUTP GND GNDGND PINKCS6717PINA MON_SCS6705 Post_Amp orGND(CS6716 Post_Amp +LD Driver)GNDPINKGND GND GND MON VCC DOUTNMONVCCDINN C4 1nF C2 0.1uFC3 0.1uFGNDFigure-7Typical Application CircuitTOP VIEW OF TO-46 HEADERTOP VIEW OF TO-46 HEADERCS6717 GND GND GNDCS6717 GNDDOUTPDOUTNDOUTPDOUTNPINKPINAPINKPINAPHOTODIODEPHOTODIODEVCCMONVCCCASE IS GROUNDCASE IS GROUNDFigure-8Typical 5-pin Assembly CircuitFigure-9Typical 4-pin Assembly Circuitpage 10 of 10。