微波炉控制器

微波炉控制器
微波炉是一种微波加热食品的现代化烹调灶具，它由电源、磁控管、控制电路和烹调腔组成。

其中，微波炉控制器部分完成各工作状态之间的切换功能，可以通过硬件语言描述的数字系统来实现。

详细分析微波炉控制器的原理和组成结构，并设计一个简单的具有定时和信息显示功能的微波炉控制器。

一、系统设计要求
设计一个具备定时和信息显示功能的微波炉控制器。

要求该微波炉控制器能够在任意时刻取消当前工作，复位为初始状态。

可以根据需要设置烹调时间的长短，系统最长的烹调时间为59分59秒；开始烹调后，能够显示剩余时间的多少。

显示微波炉控制器的烹调状态。

二、系统设计方案
分析上述设计要求，微波炉控制器可由以下四个电路模块组成：状态控制电路，其功能是控制微波炉工作过程中的状态转换，并发出相关控制信号；数据装载电路，其功能是根据控制信号选择定时时间，测试数据或计时完成信息的载入；计时电路，其功能是对时钟进行减法计数，提供烹调完成时的状态信号；显示译码电路，其功能是显示微波炉控制器的各状态信息。

图1 微波炉控制器的系统框图
微波炉控制器的系统框图如图1所示。

其中，CLK为时钟输入信号，时钟上升沿敏感；RESET为复位信号，高电平有效时系统复位清零；TEST为数码显示管测试信号，高电平有效，用于测试显示管是否正常工作；SET_T为烹调时间设置信号，高电平有效
时允许设置烹调时间；DATA为定时时间输入信号，用于设置烹调时间的长短，其由高到低分别表示定时时间分、秒的十位，个位；START为烹调开始信号，高电平有效时开始烹调；输出信号COOK指示微波炉状态，高电平时表示烹调进行时；SEC0、SEC1、MIN0、MIN1分别表示秒个位、秒十位、分个位、分十位。

顶层模块的RTL原理图如下：
微波炉控制器的工作流程如下：
首先，对系统进行复位清零，使其各电路模块均处于初始状态；当烹调时间设置信号SET_T有效时，读入时间信号DATA[15…0]的取值，此时系统自动复位并显示设置的时间信息，按下开始键START，系统进入烹调状态，COOK信号变为高电平，时钟计数器开始减法计数，显示剩余烹调时间。

烹调结束，系统恢复初始状态，数码管显示输出烹饪结束信息。

当系统处于复位清零状态时，按下显示管测试按钮TEST，将对显示管是否正常工作进行测试，正常工作时，显示管输出全1。

三个主要模块中状态控制电路的功能是根据输入信号和自身当时所处的状态完成状态的转换和输出相应的控制信号，根据微波炉工作流程的描述，分析状态转换条件及输出信号，可以得到如下所示的微波炉控制器的状态转换图。

三、VHDL编程
状态控制电路的VHDL实现如下：
Library IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY controller IS
PORT ( RESET, SET_T, START, TEST, CLK, DONE : IN STD_LOGIC;
COOK, LD_TEST, LD_CLK, LD_DONE: OUT STD_LOGIC );
END controller;
ARCHITECTURE rtl OF controller IS
TYPE STATES IS (IDLE, LAMP_TEST, SET_CLOCK, TIMER, DONE_MSG);
SIGNAL NXT, CUR: STATES;
BEGIN
PROCESS ( CLK, RESET)
BEGIN
IF RESET ='1' THEN
CUR <= IDLE;
ELSIF (CLK‟EVENT AND CLK=‟1‟) then
CUR <= NXT;
END IF;
END PROCESS;
PROCESS (CLK, CUR, SET_T, START, TEST, DONE) BEGIN
NEXT<=IDLE;
LD_TEST<=‟0‟;
LD_DONE<=‟0‟;
LD_CLK<=‟0‟;
COOK<=‟0‟;
CASE CUR IS
WHEN LAMP_TEST =>
LD_TEST <=‟1‟;
COOK<=‟0‟;
WHEN SET_CLOCK =>
LD_CLK <=‟1‟;
COOK<=‟0‟;
WHEN DONE_MSG =>
LD_DONE <=‟1‟;
COOK<=‟0‟;
WHEN IDLE=>
IF TEST=‟1‟ THEN
NXT <=LAMP_TEST;
LD_TEST <=‟1‟;
ELSIF SET_T=‟1‟ THEN
NXT <= SET_CLOCK;
LD_ CLK <=‟1‟;
ELSIF START=‟1‟ AND DONE=‟0‟ THEN
NXT <= TIMER;
COOK <=‟1‟;
END IF;
WHEN TIMER =>
IF DONE=‟1‟ THEN
NXT <= DONE_MSG;
LD_DONE <=‟1‟;
ELSE
NXT <= TIMER;
COOK <=‟1‟;
END IF;
END CASE;
END PROCESS;
END rtl;
数据装载电路的VHDL实现如下：
Library IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY loader IS
PORT ( LD_TEST, LD_CLK, LD_DONE : IN STD_LOGIC;
DATAIN : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DATAOUT : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
LOAD: OUT STD_LOGIC
);
END loader;
ARCHITECTURE rtl OF loader IS
BEGIN
PROCESS (DATAIN, LD_TEST, LD_CLK, LD_DONE)
CONSTANT ALLS: STD_LOGIC_VECTOR(15 DOWNTO 0) :=”1000100010001000”;
CONSTANT DONE: STD_LOGIC_VECTOR(15 DOWNTO 0) :=”1010101111001101”;
V ARIABLE TEMP: STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
LOAD<=LD_TEST OR LD_DONE OR LD_CLK;
TEMP:= LD_TEST & LD_DONE & LD_CLK;
CASE TEMP IS
WHEN “100”=>
DATAOUT <=ALLS;
WHEN “010” =>
DATAOUT <=DONE;
WHEN “001” =>
DATAOUT <=DATAIN;
WHEN OTHERS=> NULL;
END CASE;
END PROCESS;
END rtl;
计时电路的VHDL实现如下：
--十进制减法计数器
Library IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY cnt10 IS
PORT ( CLK, LOAD,EN : IN STD_LOGIC;
DATAIN : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
Q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
CARRY_OUT: OUT STD_LOGIC
);
END cnt10;
ARCHITECTURE rtl OF cnt10 IS
SIGNAL TMP: STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN
PROCESS ( CLK, LOAD,EN)
BEGIN
IF LOAD ='1' THEN
TMP <=DATAIN;
ELSIF (CLK‟EVENT AND CLK=‟1‟) then
IF EN ='1' THEN
IF TMP <=”0000” THEN
TMP <=”1001”;
ELSE
TMP<=TMP-…1‟;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS ( CLK, TMP)
BEGIN
IF (CLK‟EVENT AND CLK=‟1‟) then
IF TMP <=”0000” THEN
CARRY_OUT <=‟1‟;
ELSE
CARRY_OUT <=‟0‟;
END IF;
END IF;
END PROCESS;
Q<=TMP;
END rtl;
--六进制减法计数器
Library IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY cnt6 IS
PORT ( CLK, LOAD,EN : IN STD_LOGIC;
DATAIN : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
Q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
CARRY_OUT: OUT STD_LOGIC
);
END cnt6;
ARCHITECTURE rtl OF cnt6 IS
SIGNAL TMP: STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
PROCESS ( CLK, LOAD,EN)
BEGIN
IF LOAD ='1' THEN
TMP <=DATAIN;
ELSIF (CLK‟EVENT AND CLK=‟1‟) then
IF EN ='1' THEN
IF TMP <=”0000” THEN
TMP <=”0101”;
ELSE
TMP<=TMP-…1‟;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS ( CLK, TMP)
BEGIN
IF (CLK‟EVENT AND CLK=‟1‟) then
IF TMP <=”0000” THEN
CARRY_OUT <=‟1‟;
ELSE
CARRY_OUT <=‟0‟;
END IF;
END IF;
END PROCESS;
Q<=TMP;
END rtl;
--计数器电路模块设计
Library IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY counter IS
PORT ( COOK,LOAD,CLK : IN STD_LOGIC;
DATAIN : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
SEC0,SEC1,MIN0,MIN1: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
DONE: OUT STD_LOGIC
);
END counter;
ARCHITECTURE rtl OF counter IS
COMPONENT cnt10 IS
PORT ( CLK, LOAD,EN : IN STD_LOGIC;
DATAIN : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
Q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
CARRY_OUT: OUT STD_LOGIC
);
END COMPONENT cnt10;
COMPONENT cnt6 IS
PORT ( CLK, LOAD,EN : IN STD_LOGIC;
DATAIN : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
Q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
CARRY_OUT: OUT STD_LOGIC
);
END COMPONENT cnt6;
SIGNAL CLK0: STD_LOGIC;
SIGNAL S0: STD_LOGIC;
SIGNAL S1: STD_LOGIC;
SIGNAL S2: STD_LOGIC;
SIGNAL S3: STD_LOGIC;
BEGIN
U1: cnt10 PORT MAP(CLK, LOAD,COOK,DATA (3 DOWNTO 0),SEC0,S0);
U2: cnt6 PORT MAP(S0, LOAD,COOK,DATA (7 DOWNTO 4),SEC1,S1);
U3: cnt10 PORT MAP(S1, LOAD,COOK,DATA (11 DOWNTO 8),MIN0,S2);
U4: cnt6 PORT MAP(S2, LOAD,COOK,DATA (15 DOWNTO 12),MIN1,S3);
DONE<=S0 AND S1 AND S2 AND S3;
END rtl;
顶层模块的VHDL实现如下：
Library IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY top IS
PORT ( RESET, SET_T, START, TEST, CLK : IN STD_LOGIC;
DATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
SEC0,SEC1,MIN0,MIN1: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
COOK: OUT STD_LOGIC
);
END top;
ARCHITECTURE rtl OF top IS
COMPONENT controller IS
PORT ( RESET, SET_T, START, TEST, CLK,DONE: IN STD_LOGIC;
COOK,LD_TEST, LD_CLK, LD_DONE: OUT STD_LOGIC
);
END COMPONENT controller;
COMPONENT loader IS
PORT ( DATAIN : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
LD_TEST, LD_CLK, LD_DONE: IN STD_LOGIC;
DATAOUT : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
LOAD: OUT STD_LOGIC
);
END COMPONENT loader;
COMPONENT counter IS
PORT ( CLK, LOAD,COOK : IN STD_LOGIC;
DATAIN : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
SEC0,SEC1,MIN0,MIN1: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
DONE: OUT STD_LOGIC
);
END COMPONENT counter;
SIGNAL COOK_TMP: STD_LOGIC;
SIGNAL TEST_TMP: STD_LOGIC;
SIGNAL CLK_TMP: STD_LOGIC;
SIGNAL DONE_TMP: STD_LOGIC;
SIGNAL LOAD_TMP: STD_LOGIC;
SIGNAL DONE: STD_LOGIC;
SIGNAL DATA_TMP: STD_LOGIC_VECTOR(15 DOWNTO 0);
BEGIN
COOK<=COOK_TMP;
U1: controller PORT MAP(RESET, SET_T, START, TEST, CLK, DONE, COOK_TMP, TEST_TMP, CLK_TMP, DONE_TMP);
U2: loader PORT MAP(DATA, TEST_TMP, CLK_TMP, DONE_TMP, DATA_TMP, LODA_TMP);
U3: counter PORT MAP(COOK_TMP, LOAD_TMP, CLK, DATA_TMP, SEC0, SEC1, MIN0, MIN1, DONE);
END rtl;。