8位串行二进制全加器

只用一位二进制全加器为基本元件和一些辅助的时序电路，设计一个8位串行二进制全加器。

Vhdl代码如下：
顶层文件如下：
library ieee;
use ieee.std_logic_1164.all;
entity f8_adder is
port(a,b:in std_logic_vector(7 downto 0);
c0:in std_logic;
s:out std_logic_vector(7 downto 0);
c1:out std_logic);
end f8_adder;
architecture bhv of f8_adder is
signal cout:std_logic_vector(7 downto 1);
component f_adder is
port(ain,bin,cin:in std_logic;
cout,sum:out std_logic);
end component;
begin
u1: f_adder port map(ain=>a(0),bin=>b(0),cin=>c0,sum=>s(0),cout=>cout(1));
u2: f_adder port map(ain=>a(1),bin=>b(1),cin=>cout(1),sum=>s(1),cout=>cout(2));
u3: f_adder port map(ain=>a(2),bin=>b(2),cin=>cout(2),sum=>s(2),cout=>cout(3));
u4: f_adder port map(ain=>a(3),bin=>b(3),cin=>cout(3),sum=>s(3),cout=>cout(4));
u5: f_adder port map(ain=>a(4),bin=>b(4),cin=>cout(4),sum=>s(4),cout=>cout(5));
u6: f_adder port map(ain=>a(5),bin=>b(5),cin=>cout(5),sum=>s(5),cout=>cout(6));
u7: f_adder port map(ain=>a(6),bin=>b(6),cin=>cout(6),sum=>s(6),cout=>cout(7));
u8: f_adder port map(ain=>a(7),bin=>b(7),cin=>cout(7),sum=>s(7),cout=>c1);
end bhv;
全加器描述：
library ieee;
use ieee.std_logic_1164.all;
entity f_adder is
port(ain,bin,cin:in std_logic;
cout,sum:out std_logic);
end f_adder;
architecture fd1 of f_adder is
component h_adder
port(a,b:in std_logic;
co,so:out std_logic);
end component;
component or2a
port(a,b:in std_logic;
c:out std_logic);
end component;
signal d,e,f:std_logic;
begin
u1: h_adder port map(a=>ain,b=>bin,co=>d,so=>e); u2: h_adder port map(a=>e,b=>cin,co=>f,so=>sum); u3: or2a port map(a=>d,b=>f,c=>cout);
end fd1;
半加器描述：
library ieee;
use ieee.std_logic_1164.all;
entity h_adder is
port(a,b:in std_logic;
co,so:out std_logic);
end h_adder;
architecture fh1 of h_adder is
begin
so<=not(a xor not(b));
co<=a and b;
end fh1;
或门电路描述：
library ieee;
use ieee.std_logic_1164.all;
entity or2a is
port(a,b:in std_logic;
c:out std_logic);
end or2a;
architecture one of or2a is
begin
c<=a or b;
end one;
RTL 电路图如下：
由于RTL图比较大，因此将它另外一图片的格式显示出来，这里只给了一个略缩图。

时序仿真图如下：。