quartus ii 常见的19个错误、28个警告

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QuartusII常见警告分析

在后续版本的Quartus得到完善。
20.Timing Analysis does not support the analysis of latches as
synchronous elements for the currently selected device family
clock skew
原因：使用了行波时钟或门控时钟，把触发器的输出当时钟用就会报行波时钟，
将组合逻辑的输出当时钟用就会报门控时钟
措施：不要把触发器的输出当时钟，不要将组合逻辑的输出当时钟，如果本身如
此设计，则无须理会该警告
23.Warning (10268): Verilog HDL information at lcd7106.v(63):
|whole|clk10m
原因：因为你的波形仿真文件（ vector source file ）中并没有把所有的输入
信号(input pin)加进去，对于每一个输入都需要有激励源的
17.Error: Can't name logic scfifo0 of instance "inst" --
Quartus警告分析！
bjxiong 发表于 - 2007-8-21 11:10:00
1
推荐1.Found clock-sensitive change during active clock edge at time
<time> on register "<name>"
原因：vector source file中时钟敏感信号（如：数据，允许端，清零，同步加
载等）在时钟的边缘同时变化。而时钟敏感信号是不能在时钟边沿变化的。其后

quartus ii 常见的19个错误28个警告

(一) Q uartus警告解析(二)(三) 1.Found clock-sensitive change during active clock edge at time<time> on register"<name>"(四) 原因：vector source file中时钟敏感信号（如：数据，允许端，清零，同步加载等）在时钟的边缘同时变化。

而时钟敏感信号是不能在时钟边沿变化的。

其后果为导致结果不正确。

(五) 措施：编辑vector source file(六)(七) 2.Verilog HDL assignment warning at <location>: truncated with size <number> tomatch size of target (<number>(八) 原因:在HDL设计中对目标的位数进行了设定,如:reg[4:0] a;而默认为32位,将位数裁定到合适的大小(九) 措施:如果结果正确,无须加以修正,如果不想看到这个警告,可以改变设定的位数(十)(十一) 3.All reachable assignments to data_out(10) assign '0', register removed by optimization(十二) 原因:经过综合器优化后，输出端口已经不起作用了(十三)(十四) 4.Following 9 pins have nothing, GND, or VCC driving datain port -changes to this connectivity may change fitting results(十五) 原因:第9脚，空或接地或接上了电源(十六) 措施:有时候定义了输出端口，但输出端直接赋‘0’，便会被接地，赋‘1’接电源。

Altera QuartusII警告

Altera QuartusII警告在QuartusII下进行编译和仿真的时候,会出现一堆warning,有的可以忽略,有的却需要注意,虽然按F1可以了解关于该警告的帮助,但有时候帮助解释的仍然不清楚,大家群策群力,把自己知道和了解的一些关于警告的问题都说出来讨论一下,免得后来的人走弯路.1.Found clock-sensitive change during active clock edge at time <time> on register "<name>"原因：vector source file中时钟敏感信号（如：数据，允许端，清零，同步加载等）在时钟的边缘同时变化。

而时钟敏感信号是不能在时钟边沿变化的。

其后果为导致结果不正确。

2.Verilog HDL assignment warning at <location>: truncated value with size <number> to match size oftarget (<number>原因:在HDL设计中对目标的位数进行了设定,如:reg[4:0] a;而默认为32位,将位数裁定到合适的大小措施:如果结果正确,无须加以修正,如果不想看到这个警告,可以改变设定的位数3.All reachable assignments to data_out(10) assign '0', register removed by optimization原因:经过综合器优化后，输出端口已经不起作用了4.Following 9 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results原因:第9脚，空或接地或接上了电源措施:有时候定义了输出端口，但输出端直接赋…0‟，便会被接地，赋…1‟接电源。

QuartusII有关错误和警告的编译信息总结

在QuartusII下进行编译和仿真的时候,会出现一堆warning,有的可以忽略,有的却需要注意,虽然按F1可以了解关于该警告的帮助,但有时候帮助解释的仍然不清楚,大家群策群力,把自己知道和了解的一些关于警告的问题都说出来讨论一下,免得后来的人走弯路.下面是我收集整理的一些,有些是自己的经验,有些是网友的,希望能给大家一点帮助,如有不对的地方,请指正,如果觉得好,请版主给点威望吧,谢谢1.Found clock-sensitive change during active clock edge at time <time> on register "<name>"原因：vector source file中时钟敏感信号（如：数据，允许端，清零，同步加载等）在时钟的边缘同时变化。

而时钟敏感信号是不能在时钟边沿变化的。

其后果为导致结果不正确。

措施：编辑vector source file2.Verilog HDL assignment warning at <location>: truncated value with size <number> to match size of target (<number>原因:在HDL设计中对目标的位数进行了设定,如:reg[4:0] a;而默认为32位,将位数裁定到合适的大小措施:如果结果正确,无须加以修正,如果不想看到这个警告,可以改变设定的位数3.All reachable assignments to data_out(10) assign '0', register removed by optimization原因:经过综合器优化后，输出端口已经不起作用了4.Following 9 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results原因:第9脚，空或接地或接上了电源措施:有时候定义了输出端口，但输出端直接赋‘0’，便会被接地，赋‘1’接电源。

QUARTUSII常见错误解决方法

QUARTUSII常见错误解决方法QUARTUS II版本：9.0FPGA型号：EP2C8Q208配置芯片：EPCS4SDRAM型号: HY57V28820HCT-HFLASH型号 :TE28F320J3之前已经接触QUARTUS II比较长的时间了，也遇到过不少问题，有些比较简单解决后就忘了，现在把能记得起来列在前面几个。

后面的是自己后续遇到的问题的集锦...1.多模块或多进程驱动同一信号Error (10028): Can't resolve multiple constant drivers for net "FLASH_A[7]" at led.v(32)用Verilog描述电路时，一个信号只能在一个进程中驱动，如果在多个进程中对其驱动的话将产生如上错误。

解决方法为可以另加一个信号，通过在另一个进程中监视这个信号做出相应的动作。

2.多功能管脚的设置在用FLASH分配完管脚后编译出现如下错误：Error: Can't place multiple pins assigned to pin location Pin_108 (IOC_X34_Y2_N0)Info: Fitter preparation operations ending: elapsed time is 00:00:00Error: Can't fit design in deviceError: Quartus II Fitter was unsuccessful. 2 errors, 0 warnings Error: Quartus II Full Compilation was unsuccessful. 4 errors, 56 warnings原因是不能分配给多功能管脚PIN_108。

这是由于PIN_108是一个多功能管脚，还有一个功能是nCEO，也是默认的功能。

如果要用它当普通IO，需要提前设置一下：assignments>device>device and pin options>dual-purpose pins 里面把nCEO设置成use as regular i/o就可以了。

Quartus II 中常见Warning 及解决方法(转载)

14.Can't achieve minimum setup and hold requirement <text> along <number> path(s). See Report window for details.
原因：时序分析发现一定数量的路径违背了最小的建立和保持时间，与时钟歪斜有关,一般是由于多时钟引起的
21.Warning:Found xx output pins without output pin load capacitance assignment（网友：gucheng82提供）
原因：没有给输出管教指定负载电容
措施：该功能用于估算TCO和功耗，可以不理会，也可以在Assignment Editor中为相应的输出管脚指定负载电容，以消除警告
措施:如果结果正确,无须加以修正,如果不想看到这个警告,可以改变设定的位数
3.All reachable assignments to data_out(10) assign '0', register removed by optimization
原因:经过综合器优化后，输出端口已经不起作用了
措施:如果clk不是时钟，可以加“not clock”的约束；如果是，可以在clock setting当中加入；在某些对时钟要求不很高的情况下，可以忽略此警告或在这里修改:Assignments>Timing analysis settings...>Individual clocks...>...
和多时钟有关的Multicycle 和Multicycle Hold选项，如hold time为负，可使Multicycle hold的值>multicycle,如设为2和1。

QuartusII常犯错误

设计中从硬件到软件，不断有新的问题出现，先将出现的典型问题罗列如下。

1．Maxplus2功能问题：Maxplus2对用于数组描述的RAM及ROM在编译过程中会出错，有可能是M axplus2在语法支持上不太全面。

该用Quarters II运行或用元件例化的方法解决。

例如：subtype word is std_logic_vector(k-1downto0);type memory is array(0to2**w-1)of word;解决：在QuartusП上运行通过。

2.进行仿真实验时，结束时间设为100us时出现的问题：解决：不改动原状态的时间设置。

3.管脚编辑出现的问题：原因是自己改变了原来的管脚编号4.毛刺信号的产生信号在FPGA器件内部通过连线和逻辑单元时，都有一定的延时。

延时的大小与连线的长短和逻辑单元的数目有关。

同时还受器件的制作工艺、工作电压、温度等条件的影响。

信号的高低电平转换也许要一定的过渡时间。

由于以上因素的影响，多路信号的电平变化时，在信号变化的瞬间，组合逻辑的输出状态不确定，往往会出现一些不正确的尖峰信号。

这些尖峰信号被称为“毛刺”。

许多逻辑电路产生的小的寄生信号，也能成为毛刺信号。

这些无法预见的毛刺信号可通过设计来传播并产生不需要的时钟脉冲。

应该明确的是，任何组合电路都可能是潜在的毛刺信号发生器，而时钟端口、清零和置位端口对毛刺信号十分敏感，任何一点毛刺都可能会使系统出错。

5.基本VHDL编程语法错误：①丢失关键字、符号及端口设置。

②前后不能呼应，丢失结尾等，如if对应end if。

③实体与保存名不一致，调用名与实际名不一致，前后应用名不一致。

④从其它机器或U盘转换到另台机器时，由于版本不一致，致使字符及符号出错。

⑤要求的数据位数与程序中数据位数不一致而出错⑥多个源冲突。

⑦设置端口、信号及变量数据类型出错。

⑧调用的文件必须与主文件在同一个文件包内。

⑨对一些运算及运行转换，必须加载库use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;use ieee.numeric_std.all;6.architecture struc of multi16isbeginprocessbeginif(clock'event and clock='1')thenresult<=dataa*datab;end if;end process;end struc;解决：加敏感量。

quartusii常见的19个错误、28个警告.doc

(一) Q uartus警告解析1.Found clock-sensitive change during active clock edge at time<time> on register"<name>"原因：vector source file中时钟敏感信号（如：数据，允许端，清零，同步加载等）在时钟的边缘同时变化。

而时钟敏感信号是不能在时钟边沿变化的。

其后果为导致结果不正确。

措施：编辑vector source file2.Verilog HDL assignment warning at <location>: truncated with size <number> tomatch size of target (<number>原因:在HDL设计中对目标的位数进行了设定,如:reg[4:0] a;而默认为32位,将位数裁定到合适的大小措施:如果结果正确,无须加以修正,如果不想看到这个警告,可以改变设定的位数3.All reachable assignments to data_out(10) assign '0', register removed byoptimization原因:经过综合器优化后，输出端口已经不起作用了4.Following 9 pins have nothing, GND, or VCC driving datain port -changes to thisconnectivity may change fitting results原因:第9脚，空或接地或接上了电源措施:有时候定义了输出端口，但输出端直接赋…0‟，便会被接地，赋…1‟接电源。

如果你的设计中这些端口就是这样用的，那便可以不理会这些warning5.Found pins functioning as undefined clocks and/or memory enables原因:是你作为时钟的PIN没有约束信息。

quartusii错误信息

quartusii错误信息1.Found clock-sensitive change during active clock edge at time on register ""原因：vector source file中时钟敏感信号（如：数据，允许端，清零，同步加载等）在时钟的边缘同时变化。

而时钟敏感信号是不能在时钟边沿变化的。

其后果为导致结果不正确。

措施：编辑vector source file2.Verilog HDL assignment warning at : truncated with size to match size of target (原因:在HDL设计中对目标的位数进行了设定,如:reg[4:0] a;而默认为32位,将位数裁定到合适的大小措施:如果结果正确,无须加以修正,如果不想看到这个警告,可以改变设定的位数3.All reachable assignments to data_out(10) assign '0', register removed by optimization原因:经过综合器优化后，输出端口已经不起作用了4.Following 9 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results 原因:第9脚，空或接地或接上了电源措施:有时候定义了输出端口，但输出端直接赋…0?，便会被接地，赋…1?接电源。

如果你的设计中这些端口就是这样用的，那便可以不理会这些warning5.Found pins ing as undefined clocks and/or memory enables原因:是你作为时钟的PIN没有约束信息。

可以对相应的PIN做一下设定就行了。

（1）quartus?II的各种警告

（1）quartus II的各种警告1.Verilog HDL information at xxx.v:always construct contains both blocking and non-blocking assignments在一个always块中同时使用了阻塞和非阻塞赋值。

2.Warning: Parallel compilation is not licensed and has been disabled并行编译未获得许可，已经终止。

3.Warning (10227): Verilog HDL Port Declaration warning at v_led.v(4): data type declaration for "out" declares packed dimensions but the port declaration declaration does not 应该在声明引脚输入输出时就写明位宽，否在之后声明就会出现以上错误。

如output out；reg[7:0] out；就会报警告，应该写成output reg[7:0] out;才正确。

4.Warning (10230): Verilog HDL assignment warning at v_led.v(13): truncated value with size 32 to match size of target (8)原因:在HDL设计中对目标的位数进行了设定,如:reg[4:0] a;而默认为32位,将位数裁定到合适的大小措施:如果结果正确,无须加以修正,如果不想看到这个警告,可以改变设定的位数5.Warning: Found 9 output pins without output pin load capacitance assignment输出引脚没用输出引脚负载电容。

Quartus II 常见编译错误锦集

Quartus II常见编译错误锦集在QuartusII下进行编译和仿真的时候,会出现一堆warning,有的可以忽略,有的却需要注意,虽然按F1可以了解关于该警告的帮助,但有时候帮助解释的仍然不清楚,大家群策群力,把自己知道和了解的一些关于警告的问题都说出来讨论一下,免得后来的人走弯路.下面是我收集整理的一些,有些是自己的经验,有些是网友的,希望能给大家一点帮助。

1.Found clock-sensitive change during active clock edge at time on register""原因：vector source file中时钟敏感信号（如：数据，允许端，清零，同步加载等）在时钟的边缘同时变化。

而时钟敏感信号是不能在时钟边沿变化的。

其后果为导致结果不正确。

措施：编辑vector source file2.Verilog HDL assignment warning at:truncated value with size to match size of target(原因:在HDL设计中对目标的位数进行了设定,如:reg[4:0]a;而默认为32位,将位数裁定到合适的大小措施:如果结果正确,无须加以修正,如果不想看到这个警告,可以改变设定的位数3.All reachable assignments to data_out(10)assign'0',register removed by optimization原因:经过综合器优化后，输出端口已经不起作用了4.Following9pins have nothing,GND,or VCC driving datain port--changes to this connectivity may change fitting results原因:第9脚，空或接地或接上了电源措施:有时候定义了输出端口，但输出端直接赋‘0’，便会被接地，赋‘1’接电源。

Quartus常见错误分析Error

Quartus常见错误分析ErrorQuartus常见错误分析ErrorWarning: VHDL Process Statement warning at random.vhd(18): signal reset is in statement, but is not in sensitivity list----没把singal放到process（）中2 Warning: Found pins ing as undefined clocks and/or memory enablesInfo: Assuming node CLK is an undefined clock-=-----可能是说设计中产生的触发器没有使能端3 Error:VHDL Interface Declaration error in clk_gen.vhd(29): interface object "clk_scan" of mode outcannot be read. Change object mode to buffer or inout.------信号类型设置不对，out当作buffer来定义4 Error:Node instance "clk_gen1" instantiates undefined entity "clk_gen"-------引用的例化元件未定义实体－－entity "clk_gen"5 Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated cl ocks -- node(s)analyzed as buffer(s) resulting in clock skewInfo: Detected ripple clock "clk_gen:clk_gen1|clk_incr" as bufferInfo: Detected ripple clock "clk_gen:clk_gen1|clk_scan" as buffer6 Warning: VHDL Process Statement warning at ledmux.vhd(15): signal or variable "datao ut" may not be assigned a new in every possible path through the Process Statement. Signal or variable " dataout" holdsits previous in every path with no new assignment, whichmay create a combinational loo p in the currentdesign.7 Warning: VHDL Process Statement warning at divider_10.vhd(17): signal "cnt" is read i nside the Process Statement but isn't in the Process Statement's sensivitity list -----缺少敏感信号8 Warning: No clock transition on "counter_bcd7:counter_counter_clk|q_sig[3]" register9 Warning: Reduced register "counter_bcd7:counter_counter_clk|q_sig[3]" with stuck clock port to stuckGND10 Warning: Circuit may not operate. Detected 1 non-operational path(s) clocked by clock "class[1]" withclock skew larger than data delay. See Compilation Report for details.11 Warning: Circuit may not operate. Detected 1 non-operational path(s) clocked by clock "sign" withclock skew larger than data delay. See Compilation Report for details.12 Error:VHDL error at counter_clk.vhd(90): actual port "class" of mode "in" cannot be associated withformal port "class" of mode "out"------两者不能连接起来13 Warning: Ignored node in vector source file. Can't find corresponding node name "clas s_sig[2]" indesign.------没有编写testbench文件，或者没有编辑输入变量的值testbench里是元件申明和映射14 Error:VHDL Binding Indication error atfreqdetect_top.vhd(19): port "class"in design entity does not have std_logic_vector type that is specified for the same generic in the associated com ponent---在相关的元件里没有当前文件所定义的类型15 Error:VHDL error at tongbu.vhd(16): can't infer register for signal "gate" because sign al does nothold its outside clock edge16 Warning: Found clock high time violation at 1000.0 ns on register"|fcounter|lpm_counter:temp_rtl_0|dffs[4]"17 Warning: Compiler packed, optimized or synthesized away node "temp[19]". Ignored ve ctor source filenode.---"temp[19]"被优化掉了18 Warning: Reduced register "gate~reg0" with stuck data_in port to stuck GND19 Warning: Design contains 2 input pin(s) that do not drive logicWarning: No output dependent on input pin "clk"Warning: No output dependent on input pin "sign"------输出信号与输入信号无关，20 Warning: Found clock high time violation at 16625.0 ns on register "|impulcomp|gate1"21 Error:VHDL error at impulcomp.vhd(19): can't implement clock enable condition speci fied using binaryoperator "or"22 Error:VHDL Association List error at period_counter.vhd(38): actual parameter assigned to formalparameter "alarm", but formal parameter is not declared-------连接表错误，形参"alarm"赋值给实参，形参没定义，可能是形参与实参的位置颠倒了，规定形参在实参之前。

quartus ii 中常见warning 及解决方法(转载)(Quartus II中常见警告及解决方法(转载))

quartus ii 中常见warning 及解决方法(转载)（Quartus II中常见警告及解决方法（转载））Support original! I reprinted, you can download free1.Found clock-sensitive, change, during, active, clock, edge, at, time, <time>, on, register, <name>"Reason: vector, source, file, clock sensitive signals (such as data, allowing, clearing, synchronization, loading, etc.) change simultaneously on the edge of the clock. A clock sensitive signal cannot change at the edge of the clock. The consequence is that the result is incorrect.Measures: edit vector source file2.Verilog, HDL, assignment, warning, at, <location>: truncated, value, with, size, <number>, to, match,, size, of, target (<number>Reason: in HDL design, the number of targets is set, such as: reg[4:0] a, and default to 32 bits, the number of digits to the right sizeMeasure: if the result is correct, it needs no correction. If you don't want to see this warning, you can change the number of settings3.All, reachable, assignments, to, data_out (10), assign,'0', register, removed, by, optimizationReason: after the optimizer has been optimized, the output port is no longer functional4.Following 9, pins, have, nothing, GND, or, VCC, driving, datain, port - changes, to, this,, connectivity, may, change, results, fittingReason: ninth feet, empty or grounded or connected to the power supplyMeasures: sometimes the output port is defined, but the output is directly assigned to '0', which will be grounded and assigned '1' to the power supply. If these ports are used in your design, you can ignore these warning5.Found, pins, functioning, as, undefined, clocks, and/or, memory, enablesReason: you have no constraint information as the PIN of the clock. You can set the settings for the corresponding PIN. Mainly refers to some of your pin in the circuit played a role in the clock tube, such as the flip-flop CLK pin, and this pin has no clock constraint, so QuartusII CLK as undefined clock.Measures: if CLK is not a clock, can add "not clock" constraint; if it is, can be added in clock setting; in some of the clock requirements are not very high, you can ignore this warning or modified here: Assignments>Timing analysis settings... Individual clocks > >.....6.Timing, characteristics, of, device, EPM570T144C5, are,preliminaryReason: because MAXII is a relatively new component, the timing in QuartusII is not a formal version. Wait for Service PackMeasure: only affects Quartus's Waveform7.Warning:, Clock, latency, analysis, for, offsets, is, supported, for, the, current, device, family, but, is, PLL, not, enabledMeasure: change the on in setting, Requirements&Option-->More, Timing, Setting-->setting-->Enable, Clock, Latency, timing to OFF8.Found, clock, high, time, violation, at,, NS, on, register, |counter|lpm_counter:count1_rtl_0|dffs[11]"Reason: violated the steup/hold time, should be after the simulation, to see whether the waveform settings and the clock edge in line with steup/hold timeMeasure: adding a register in the middle can solve the problem9.warning:, circuit, may, not, operate.detected,non-operational,, paths, clocked, by, clock, clk44, with, clock,, skew, larger, delay, than, dataReason: clock jitter is greater than data delay, when the clock is very fast, and if and other classes of excessive levels of this problem will occur, but this problem is mostly in thedevice's highest frequency will appear措施：设置-->选项-->需要定时要求和改小一些违约，如改到50mhz10。

quartusII常见错误

2 Warning: Found pins ing as undefined clocks and/or memory enables
Info: Assuming node CLK is an undefined clock
-=-----可能是说设计中产生的触发器没有使能端
3 Error: VHDL Interface Declaration error in clk_gen.vhd(29): interface object
outside clock edge
28 Error: Can't elaborate top-level user hierarchy
29 Error: Can't resolve multiple constant drivers for net "cs_in" at
led_key.vhd(32) ----------有两个以上赋值语句，不能确定“cs_in”的值
cannot be associated with formal port "class" of mode "out"
------两者不能连接起来
13 Warning: Ignored node in vector source file. Can't find corresponding node
read inside the Process Statement but isn't in the Process Statement's
sensivitity list
-----缺少敏感信号
8 Warning: No clock transition on "counter_bcd7:counter_counter_clk|q_sig[3]"

QuartusII警告信息解析

QuartusII警告信息解析1.Found clock-sensitive change during activeclockedge at time <time> on register "<name>"原因：vector sourcefile中时钟敏感信号（如：数据，允许端，清零，同步加载等）在时钟的边缘同时变化。

而时钟敏感信号是不能在时钟边沿变化的。

其后果为导致结果不正确。

措施：编辑vector source file2.VerilogHDL assignment warning at <location>: truncated value with size <number> to match size of target (<number>原因:在HDL设计中对目标的位数进行了设定,如:reg[4:0] a;而默认为32位,将位数裁定到合适的大小措施:如果结果正确,无须加以修正,如果不想看到这个警告,可以改变设定的位数3.All reachable assignments to data_out(10) assign '0', register removed by optimization原因:经过综合器优化后，输出端口已经不起作用了4.Following 9 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results原因:第9脚，空或接地或接上了电源措施:有时候定义了输出端口，但输出端直接赋‘0’，便会被接地，赋‘1’接电源。

Quartus常见警告和错误

Quartus常见警告和错误【转】2009-08-07 14:00Quartus常见警告和错误1 Warning: VHDL Process Statement warning at random.vhd(18): signal reset is in statement, but is not in sensitivity list----没把singal放到process（）中2 Warning: Found pins ing as undefined clocks and/or memory enables Info: Assuming node CLK is an undefined clock-=-----可能是说设计中产生的触发器没有使能端3 Error: VHDL Interface Declaration error in clk_gen.vhd(29): interface object "clk_scan" of mode out cannot be read. Change object mode to buffer or inout.------信号类型设置不对，out当作buffer来定义4 Error: Node instance "clk_gen1" instantiates undefined entity "clk_gen" -------引用的例化元件未定义实体－－entity "clk_gen"5 Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skewInfo: Detected ripple clock "clk_gen:clk_gen1|clk_incr" as buffer Info: Detected ripple clock "clk_gen:clk_gen1|clk_scan" as buffer6 Warning: VHDL Process Statement warning at ledmux.vhd(15): signal or variable "dataout" may not be assigned a new in every possible path through the Process Statement. Signal or variable "dataout" holds its previous in every path with no new assignment, which may create a combinational loop in the current design.7 Warning: VHDL Process Statement warning at divider_10.vhd(17): signal "cnt" is read inside the Process Statement but isn't in the Process Statement's sensivitity list-----缺少敏感信号8 Warning: No clock transition on"counter_bcd7:counter_counter_clk|q_sig[3]"register9 Warning: Reduced register "counter_bcd7:counter_counter_clk|q_sig[3]" with stuck clock port to stuck GND10 Warning: Circuit may not operate. Detected 1 non-operational path(s)clocked by clock "class[1]" with clock skew larger than data delay. See Compilation Report for details.11 Warning: Circuit may not operate. Detected 1 non-operational path(s) clocked by clock "sign" with clock skew larger than data delay. See Compilation Report for details.12 Error: VHDL error at counter_clk.vhd(90): actual port "class" of mode "in"cannot be associated with formal port "class" of mode "out"------两者不能连接起来13 Warning: Ignored node in vector source file. Can't find corresponding node name "class_sig[2]" in design.------没有编写testbench文件，或者没有编辑输入变量的值 testbench里是元件申明和映射14 Error: VHDL Binding Indication error at freqdetect_top.vhd(19): port "class"in design entity does not have std_logic_vector type that is specified for thesame generic in the associated component---在相关的元件里没有当前文件所定义的类型15 Error: VHDL error at tongbu.vhd(16): can't infer register for signal "gate"because signal does not hold its outside clock edge16 Warning: Found clock high time violation at 1000.0 ns on register "|fcounter|lpm_counter:temp_rtl_0|dffs[4]"17 Warning: Compiler packed, optimized or synthesized away node "temp[19]".Ignored vector source file node.---"temp[19]"被优化掉了18 Warning: Reduced register "gate~reg0" with stuck data_in port to stuck GND19 Warning: Design contains 2 input pin(s) that do not drive logic Warning: No output dependent on input pin "clk"Warning: No output dependent on input pin "sign"------输出信号与输入信号无关，20 Warning: Found clock high time violation at 16625.0 ns on register"|impulcomp|gate1"21 Error: VHDL error at impulcomp.vhd(19): can't implement clock enable condition specified using binary operator "or"22 Error: VHDL Association List error at period_counter.vhd(38): actual parameter assigned to formal parameter "alarm", but formal parameter is not declared-------连接表错误，形参"alarm"赋值给实参，形参没定义，可能是形参与实参的位置颠倒了，规定形参在实参之前。

quartus仿真出现的问题

quartus仿真出现的问题在QuartusII下进行编译和仿真的时候,会出现一堆warning,有的可以忽略,有的却需要注意,虽然按F1可以了解关于该警告的帮助,但有时候帮助解释的仍然不清楚,大家群策群力,把自己知道和了解的一些关于警告的问题都说出来讨论一下,免得后来的人走弯路.下面是我收集整理的一些,有些是自己的经验,有些是网友的,希望能给大家一点帮助,如有不对的地方,请指正,如果觉得好,请版主给点威望吧,谢谢1.Found clock-sensitive change during active clock edge at time on register ""原因：vector source file中时钟敏感信号（如：数据，允许端，清零，同步加载等）在时钟的边缘同时变化。

而时钟敏感信号是不能在时钟边沿变化的。

其后果为导致结果不正确。

措施：编辑vector source file2.Verilog HDL assignment warning at : truncated value with size to match size of target (原因:在HDL设计中对目标的位数进行了设定,如:reg[4:0] a;而默认为32位,将位数裁定到合适的大小措施:如果结果正确,无须加以修正,如果不想看到这个警告,可以改变设定的位数3.All reachable assignments to data_out(10) assign '0', register removed by optimization原因:经过综合器优化后，输出端口已经不起作用了4.Following 9 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results 原因:第9脚，空或接地或接上了电源措施:有时候定义了输出端口，但输出端直接赋‘0’，便会被接地，赋‘1’接电源。

Quartus II使用常见问题

在Quartus II下进行编译和仿真的时候,会出现一堆warning,有的可以忽略,有的却需要注意,虽然按F1可以了解关于该警告的帮助,但有时候帮助解释的仍然不清楚,大家群策群力,把自己知道和了解的一些关于警告的问题都说出来讨论一下,免得后来的人走弯路.下面是我收集整理的一些,有些是自己的经验,有些是网友的,希望能给大家一点帮助,如有不对的地方,请指正,如果觉得好,请版主给点威望吧,谢谢1.Found clock-sensitive change during active clock edge at time <time> on register "<name>"原因：vector source file中时钟敏感信号（如：数据，允许端，清零，同步加载等）在时钟的边缘同时变化。

而时钟敏感信号是不能在时钟边沿变化的。

其后果为导致结果不正确。

Quartus 2 使用错误集锦

Quartus 2 使用错误集锦4月24日更新....1.Error: Top-level design entity "test" is undefined原因：顶层模块的module名没有和工程名同名解决方法：把顶层模块的module名改成和工程名同名2.Error (10278): Verilog HDL Port Declaration error at test.v(4): input port "clk_in" cannot be declared with type "reg"原因：输入变量不能定义成reg型，必须是wire型，我们做的一个芯片的输入引脚需要是实时采集输入数据的，所以必须是wire（导线），不能是寄存器型解决方法：把输入信号定义成线型wire3.Error (10137): Verilog HDL Procedural Assignment error at test.v(12): object "led" on left-hand side of assignment must have a variable data type原因：数据类型定义错误或者赋值类型错误解决方法：在always 过程块中被赋值的变量必须是reg （寄存器型），用assign 连续赋值的对象必须定义成wire（线型）4.Error: Can't place multiple pins assigned to pin location Pin_108 (IOC_X34_Y2_N0)原因：PIN_108是一个多功能管脚，还有一个功能是nCEO，也是默认的功能。

如果要用它当普通IO，需要提前设置一下解决方法：assignments>device>device and pin options>dual-purpose pins里面把nCEO 设置成use as regular i/o就可以了5.Error (10028): Can't resolve multiple constant drivers for net "key_flag" at clock.v(33)原因：一个变量不能同时被在两个always 过程块中被赋值解决方法：在两个always过程块中用两个不同的变量名，可以在module最后用assign 把变量的值作最后的统一，但是注意wire型和reg型的变量类型定义6.Warning (10230): Verilog HDL assignment warning at SMG_1S.v(21): truncated value with size 32 to match size of target (8)原因：赋值语句的等号两端数据的位宽不一致。

Altera QuartusII警告分析

打造Altera QuartusII警告强帖(原创)在QuartusII下进行编译和仿真的时候,会出现一堆warning,有的可以忽略,有的却需要注意,虽然按F1可以了解关于该警告的帮助,但有时候帮助解释的仍然不清楚,大家群策群力,把自己知道和了解的一些关于警告的问题都说出来讨论一下,免得后来的人走弯路.下面是我收集整理的一些,有些是自己的经验,有些是网友的,希望能给大家一点帮助,如有不对的地方,请指正,如果觉得好,请版主给点威望吧,谢谢1.Found clock-sensitive change during active clock edge at time <time> on register "<name>"原因：vector source file中时钟敏感信号（如：数据，允许端，清零，同步加载等）在时钟的边缘同时变化。

而时钟敏感信号是不能在时钟边沿变化的。

其后果为导致结果不正确。