ATPGpaper D算法和PODEM算法的具体实现过程
合集下载
相关主题
- 1、下载文档前请自行甄别文档内容的完整性，平台不提供额外的编辑、内容补充、找答案等附加服务。
- 2、"仅部分预览"的文档,不可在线预览部分如存在完整性等问题,可反馈申请退款(可完整预览的文档不适用该条件!)。
- 3、如文档侵犯您的权益，请联系客服反馈,我们会尽快为您处理(人工客服工作时间：9:00-18:30)。
A / & T TUTORIAL
ALGORITHMS FOR
PATTERN GENERATION
TOM KIRKLAND Microelectronics and Computer Technology Corp. M. RAY MERCER University of Texas
Three well-known algorithms for the automatic generation of test patterns for digital circuits are the D algorithm, Podem, and Fan. This tutorial introduces the concept of test generation and analyzes the way each algorithm uses search and backtrackingtechniques to sensitize a fault and propagate it to an observable point.
ne task that may be a perfect candidate for automation is test patterngenerationfor combinational digital circuits. Many engineers consider this work more tedious and less rewarding than other aspects of the design process, but they also recognize that it is essential to the quality of the final product. Algorithms for automatic test generation focus primarily on ways to produce tests for combinational circuits.’ Tests for these circuits involve choices from many possibilities, so classical computer search methods are usually the basis for the algorithm. These search techniques use information in the network topology to specify the inputs that form the test pattern. The techniques have become more efficient over time as we have learned more ways to use this information. Three of the best known algorithms for combinational ATPG are the D algorithm;* Podem, short for pathoriented decision making;3and Fan.4 three algorithms All operate only on combinational circuits. Our analysis focuses on the search and control mechanisms of each algorithm. We also look at the heuristics used to guide ATPG search and the notation used to represent circuit values. Fujiwara5and Bottorff‘ give alternative views of the same algorithms.
FAensitize the fault, we must find a pattern o that produces a value of 1 at the output of S for the good circuit. In the faulty circuit,the output of Swill be stuck-at-0(s-a-0),which is different from the good circuit.To set S to 1 in the good circuit, we must set both L and M to 1. The fault is now sensitized, since the good circuit and the faulty circuit have different values at the fault location.
0740-7475/88/0600~43$100s~ 1988
0
June 1988
43
TPG TUTORIAL
GEMERATINC A TEST SET
The obvious reason to test circuits is to separate good ones from faulty ones. Consider the digital circuit in Figure la, which is also represented by the graph in Figure lb. The graph nodes represent circuit devices, or gates, while graph edges represent circuit interconnections, or wires. The inputs to the circuit are called primary inputs. These are the only places we can apply test patterns. The outputs from the circuit are called primary outputs. These are the only places we can observe the effects of the tests. Thus, test patterngeneration is the task of finding a set of input patternsthat will fully test the circuit. These patterns, called the test set, must cause all faulty circuits to exhibit different behavior from good circuits at the primary outputs. A failure is revealed when at least one primary output is different and a failure is present. The test set must be reasonable-that is, we must be able to apply it economically to all circuits produced. Testing that uses all possible input patterns will, of course, revealfaulty circuits but will be too expensive for large circuits with many inputs. For large circuits, the alternativeto exhaustive testing is to start with some simplifying assumptions about the possible failures. First, we assume that only stuck-at faults are failures. This type of fault manifests itself as a node in the circuit, which permanently assumes a value of 0 or 1. If the node’s value is 0, it is called a stuck-at-0 fault; if it is a 1, it is called a stuck-at-1. Second, we assume that only one stuck-at fault is present in a faulty circuit. This singlestuck-at fault model might seem artificialon the
surface, but it has been quite useful in practice. The reason is that if we can detect a large percentage of the single stuck-at faults, we will usually get a test set that detects a correspondingly high percentage of all failures.’ We can also use stuck-at fault models that have been developed for a particular technology with good tracking between predictedand actual results.* To amplify our previous definition of test pattern generation, then, it is the task of generating a test set that reveals all detectablesingle stuckat faults. We say detectablefaults because a circuit can have undetectable faults, also called redundant faults. The test set must consist of binary input patterns that will reveal a difference at the primary outputs. T generate such a test set, we must produce o a differenceat the fault location. This process is called fault sensitizing. We must also propagate this difference to one or more primary outputs. This process is called fault propagation. Consider the circuit in Figure 2a, which we will call a good circuit. If this circuit had a stuck-at-0 fault on the output of gate S, it would be modeled as shown in Figure 2b.
ALGORITHMS FOR
PATTERN GENERATION
TOM KIRKLAND Microelectronics and Computer Technology Corp. M. RAY MERCER University of Texas
Three well-known algorithms for the automatic generation of test patterns for digital circuits are the D algorithm, Podem, and Fan. This tutorial introduces the concept of test generation and analyzes the way each algorithm uses search and backtrackingtechniques to sensitize a fault and propagate it to an observable point.
ne task that may be a perfect candidate for automation is test patterngenerationfor combinational digital circuits. Many engineers consider this work more tedious and less rewarding than other aspects of the design process, but they also recognize that it is essential to the quality of the final product. Algorithms for automatic test generation focus primarily on ways to produce tests for combinational circuits.’ Tests for these circuits involve choices from many possibilities, so classical computer search methods are usually the basis for the algorithm. These search techniques use information in the network topology to specify the inputs that form the test pattern. The techniques have become more efficient over time as we have learned more ways to use this information. Three of the best known algorithms for combinational ATPG are the D algorithm;* Podem, short for pathoriented decision making;3and Fan.4 three algorithms All operate only on combinational circuits. Our analysis focuses on the search and control mechanisms of each algorithm. We also look at the heuristics used to guide ATPG search and the notation used to represent circuit values. Fujiwara5and Bottorff‘ give alternative views of the same algorithms.
FAensitize the fault, we must find a pattern o that produces a value of 1 at the output of S for the good circuit. In the faulty circuit,the output of Swill be stuck-at-0(s-a-0),which is different from the good circuit.To set S to 1 in the good circuit, we must set both L and M to 1. The fault is now sensitized, since the good circuit and the faulty circuit have different values at the fault location.
0740-7475/88/0600~43$100s~ 1988
0
June 1988
43
TPG TUTORIAL
GEMERATINC A TEST SET
The obvious reason to test circuits is to separate good ones from faulty ones. Consider the digital circuit in Figure la, which is also represented by the graph in Figure lb. The graph nodes represent circuit devices, or gates, while graph edges represent circuit interconnections, or wires. The inputs to the circuit are called primary inputs. These are the only places we can apply test patterns. The outputs from the circuit are called primary outputs. These are the only places we can observe the effects of the tests. Thus, test patterngeneration is the task of finding a set of input patternsthat will fully test the circuit. These patterns, called the test set, must cause all faulty circuits to exhibit different behavior from good circuits at the primary outputs. A failure is revealed when at least one primary output is different and a failure is present. The test set must be reasonable-that is, we must be able to apply it economically to all circuits produced. Testing that uses all possible input patterns will, of course, revealfaulty circuits but will be too expensive for large circuits with many inputs. For large circuits, the alternativeto exhaustive testing is to start with some simplifying assumptions about the possible failures. First, we assume that only stuck-at faults are failures. This type of fault manifests itself as a node in the circuit, which permanently assumes a value of 0 or 1. If the node’s value is 0, it is called a stuck-at-0 fault; if it is a 1, it is called a stuck-at-1. Second, we assume that only one stuck-at fault is present in a faulty circuit. This singlestuck-at fault model might seem artificialon the
surface, but it has been quite useful in practice. The reason is that if we can detect a large percentage of the single stuck-at faults, we will usually get a test set that detects a correspondingly high percentage of all failures.’ We can also use stuck-at fault models that have been developed for a particular technology with good tracking between predictedand actual results.* To amplify our previous definition of test pattern generation, then, it is the task of generating a test set that reveals all detectablesingle stuckat faults. We say detectablefaults because a circuit can have undetectable faults, also called redundant faults. The test set must consist of binary input patterns that will reveal a difference at the primary outputs. T generate such a test set, we must produce o a differenceat the fault location. This process is called fault sensitizing. We must also propagate this difference to one or more primary outputs. This process is called fault propagation. Consider the circuit in Figure 2a, which we will call a good circuit. If this circuit had a stuck-at-0 fault on the output of gate S, it would be modeled as shown in Figure 2b.