MB9054X 评估板用户手册
恩智浦MIMXRT1060 1064评估板硬件用户指南说明书
NXP Semiconductors Document identifier: MIMXRT10601064EKBHUG User's Guide Rev. 0, 06/2020MIMXRT1060/1064 Evaluation Kit Board Hardware User's GuideContentsChapter 1 Introduction (3)1.1 Board overview (3)1.2 MIMXRT1060/1064 EVK contents (4)1.3 MIMXRT1060/1064 EVK board revision history (4)Chapter 2 Specifications (5)2.1 i.MX RT1060/1064 processor (7)2.2 Boot mode configurations (7)2.3 Power tree (8)2.4 SDRAM memory (11)2.5 SD card slot (11)2.6 Hyper flash (11)2.7 QSPI flash (11)2.8 Ethernet connector (12)2.9 USB PHY connector (12)2.10 Audio input/output connector (12)2.11 OpenSDA circuit (DAP-Link) (12)2.12 JTAG connector (12)2.13 Arduino expansion port (13)2.14 Camera module connector (14)2.15 User interface switch (14)2.16 Sensor (15)2.17 User interface LED indicator (15)2.18 LCD interface (15)Chapter 3 PCB information (16)Chapter 4 EVK design files (17)Chapter 5 EVK contents (18)Chapter 1IntroductionThis document describes MIMXRT1060/1064 Evaluation Kit (EVK) based on the i.MX RT1060/1064 processor from NXP Semiconductor. The document includes system setup, debugging, and provides detailed information on the overall design and usage of the EVK board from a hardware system.1.1Board overviewThis EVK board is a platform designed to showcase the commonly used features of the i.MX RT1060/1064 Processor in a small, low-cost package. The MIMXRT1060/1064 EVK board is an entry level development board that familiarizes the developer to the processor before investing on resources for specific designs.The features of the MIMXRT1060/1064 EVK board are listed in Board features.The features of the MIMXRT1060/1064 EVK board are listed in Table 1.Table 1.Board featuresProcessor NXP Processor MIMXRT1062DVL6AMIMXRT1064DVL6ADRAM Memory SDRAM 256 Mbit, 166 MHz IS42S16160J-6BLIDCDC MPS MP2144GJLDO UNION UM1550S-18UM1750S-00Mass Storage TF Card Slot64 Mbit Quad SPI flash512 Mbit Hyper flashDisplay Interface LCD connectorEthernet10/100 Mbit/s Ethernet connector. PHY chip: KSZ8081RNBUSB USB 2.0 OTG connectorUSB 2.0 host connectorAudio Connector 3.5 mm audio stereo headphone jackBoard-mounted microphoneLeft and right speaker out connectorsS/PDIF interface (unpopulated )Power Connector 5 V DC-jackDebug Connector JTAG 20-pin connector (SWD by default)OpenSDA with DAP-LinkSensor FXOS8700CQ: 6-Axis Ecompass (3-Axis Mag, 3-Axis Accel)(Some boards are unpopulated)Table continues on the next page...IntroductionTable 1.Board features (continued)Camera CMOS sensor interfaceCAN CAN bus connectorUser Interface Button ON/OFF, POR Reset, Reset, USER buttonLED Indicator Power Status, Reset, OpenSDA, USER LEDExpansion Port Arduino interfacePCB 3.937 inch x 5.9055 inch (10 cm x 15 cm), 4-layer board1.2MIMXRT1060/1064 EVK contentsThe MIMXRT1060/1064 EVK contains the following items:•MIMXRT1060/1064 EVK board•USB cable (Micro B)•Camera1.3MIMXRT1060/1064 EVK board revision historyEVK: Mass ProductChapter 2SpecificationsThis section provides detailed information about the electrical design and practical considerations of the EVK board. The document describes each block shown in Block diagram.The document describes each block shown in Figure 1.Figure 1.Block diagramThe overview of the MIMXRT1060 EVK board is shown in Figure 2 and Figure 3.Figure 2.Overview of the MIMXRT1060 EVK board (Front side)Figure 3.Overview of the MIMXRT1060 EVK board (Back side)2.1i.MX RT1060/1064 processorThe i.MX RT1060/1064 is a new processor family featuring NXP advanced implementation of the Arm Cortex-M7 Core. It provides high CPU performance and best real-time response. i.MX RT1060/1064 provides various memory interfaces, including SDRAM, Raw NAND flash, NOR flash, SD/eMMC, Quad SPI, HyperBus, and a wide range of other interfaces for connecting peripherals, such as WLAN, Bluetooth™, GPS, displays, and camera sensors. i.MX RT1060/1064 has rich audio and video features, including LCD display, basic 2D graphics, camera interface, S/PDIF, and I2S audio interface.The i.MX RT1060/1064 applications processor can be used in areas such as industrial HMI, IoT, motor control, and home appliances. The flexibility of the architecture enables it to be used in a wide variety of other general embedded applications too. The i.MX RT processor provides all interfaces necessary to connect peripherals such as WLAN, Bluetooth™, GPS, camera sensors, and multiple displays.The more detail information about i.MX RT1060/1064 can be found in the Datasheet and Reference Manual.2.2Boot mode configurationsThe device has four boot modes (one is reserved for NXP use). The boot mode is selected based on the binary value stored in the internal BOOT_MODE register.Switch (SW7-3 and SW7-4) is used to select the boot mode on the MIMXRT1060/1064 EVK board.Table 2.Boot mode pin settingsBOOT_MODE[1:0] (SW7-3 SW7-4)BOOT TypeTable continues on the next page...Table 2.Boot mode pin settings (continued)00Boot From Fuses 01Serial Downloader 10Internal Boot 11ReservedTypically, the internal boot is selected for normal boot, which is configured by external BOOT_CFG GPIOs. Table 3 shows the typical Boot Mode and Boot Device settings.Table 3.Typical boot mode and boot device settings for RT1060SW7-1SW7-2SW7-3SW7-4Boot Device OFF ON ON OFF Hyper flash OFFOFF ON OFF QSPI flash ONOFFONOFFSD cardFor more information about boot mode configuration, see the System Boot chapter of the MIMXRT1060 Reference Manual .For more information about MIMXRT1060 EVK boot device selection and configuration, see the main board schematic .Table 4.Typical boot mode and boot device settings for RT1064SW7-1SW7-2SW7-3SW7-4Boot Device OFF OFF ON OFF QSPI flash ONOFFONOFFSD card2.3Power treeA DC 5 V external power supply is used to supply the MIMXRT1060/1064 EVK board at J2, and a slide switch SW1 is used to turn the Power ON/OFF. J41 and J9 is used to supply the EVK board.Table 5 lists different J1 jumper settings for different power supply.Table 5.Jumper settings for power supply Power Supply J1 Setting J21-2J93-4J415-6The power tree is shown in the following figure.Figure 4.Power treeThe power control logic of the MIMXRT1060/1064 EVK board is shown in the Figure 5.•SNVS is powered first and then PMIC_REQ_ON is switched on to enable external DC/DC to power up other power domains.•ON/OFF button is used to switch ON/OFF PMIC_REQ_ON to control power modes.•RESET button and WDOG output are used to reset the system power.Figure 5.Power control diagramThe power rails on the board are shown in Table 6.Table 6.Power railsTable continues on the next page...Table 6.Power rails (continued)2.4SDRAM memory256 Mbit, 166 MHz SDRAM (IS42S16160J-6BLI) is used on the EVK board.2.5SD card slotThere is an SD card slot (J39) on the MIMXRT1060/1064 EVK board. J39 is the Micro SD slot for USDHC1 interface. To boot from the SD card, the boot device switch (SW7) settings should be: ON, OFF, ON, OFF, as shown in Typical boot mode and boot device settings.2.6Hyper flashOn the MIMXRT1060/1064 EVK board, there is one 512 Mbit hyper flash device. To boot from the Hyper Flash, the boot device switch (SW7) settings should be: OFF, ON, ON, OFF, as shown in Table 3. By default, this hyper flash is disabled on the EVK. To enable the onboard hyper flash, update the following settings.1.Weld resistors: R356, R361 - R366.2.Removed 0Ωresistors: R153 - R158.The boot from hyper flash only supports RT1060.2.7QSPI flashA 64 Mbit QSPI flash is used on the MIMXRT1060/1064 EVK board. If the developer wants to boot from the QSPI flash, the boot device switch (SW7) settings should be: OFF, OFF, ON, OFF, as shown in Table 3. The QSPI flash is the default onboard flash.The boot from QSPI flash only supports RT1060.2.8Ethernet connectorThere are two Ethernet Mac controllers in the MIMXRT1060/1064 processor. The Ethernet subsystem of the MIMXRT1060/1064 EVK board is provided by the KSZ8081RNB 10/100 M Ethernet Transceiver (U16) and an RJ45 (J19) with integrated magnetic.2.9USB PHY connectorMIMXRT1060/1064 contains two integrated USB 2.0 PHYs capable of connecting USB host/device systems at:•USB low-speed (LS) rate of 1.5 Mbits/s•USB full-speed (FS) rate of 12 Mbits/s•USB 2.0 high-speed (HS) rate of 480 Mbits/s2.10Audio input/output connectorThe audio codec used on the MIMXRT1060/1064 EVK board is Wolfson’s low power, high-quality stereo codec, WM8960. The MIMXRT1060/1064 EVK board includes:•one headphone interface (J12)•one onboard MIC (P1)•two speaker interfaces (J16, J17)•S/PDIF interface (J14 and J18, DNP).J12 is a 3.5 mm audio-stereo headphone jack, which supports jack detect.2.11OpenSDA circuit (DAP-Link)The OpenSDA circuit (CMSIS–DAP) is an open-standard serial and debug adapter. It bridges serial and debug communications between a USB host and an embedded target processor.CMSIS-DAP features a mass storage device (MSD) bootloader, which provides a quick and easy mechanism for loading different CMSIS-DAP applications such as flash programmers, run-control debug interfaces, serial-to-USB converters, and more.Two or more CMSIS-DAP applications can run simultaneously. For example, run-control debug application and serial-to-USB converter run in parallel to provide a virtual COM communication interface while allowing code debugging via CMSIS-DAP with single USB connection.For the MIMXRT1060/1064 EVK board, J41 is the connector between the USB host and the RT1060/1064. To update the Open SDA firmaware, press the SW8 and Power on the board. There is a disk named "MAINTENANCE". Drag/drop the new firmware to the "MAINTENANCE" and re-power the board. The firmware is updated.2.12JTAG connectorJ21 is a standard 20-pin/2.54 mm box header connector JTAG. The pin definitions are shown in Figure 6. It supports SWD by default.Figure 6.JTAG pin definitions2.13Arduino expansion portJ22 – J25 is defined as Arduino interface. Table 7 lists the pin definitions of Arduino interface. Table 7.Arduino Interface pin definitionsJ22J23UART_RX/D0A0/ADC0UART_TX/D1A1/ADC1D2/INT0A2/ADC2D3/INT1/PWM/OC2B A3/ADC3D4/T0/XCK A4/ADC4/SDAD5/TI/PWM A5/ADC5/SCLD6/AIN0/PWM/OC0AD7/AIN1/PWMJ24J25D8/CLKO/ICP1NCD9/OC1A/PWM IOREFD10/SPI_CS RESETD11/OC2A/PWM/SPI_MOSI 3.3 VD12/SPI_MISO 5 VD13/SPI_CLK GNDGND GNDAREFD14/I2C_SDAD15/I2C_SCL2.14Camera module connectori.MX RT1060/1064 supports one parallel CSI (Camera Sensor Interface). There is a camera module connector (J35) on the MIMXRT1060/1064 EVK board. The CA031C based on OV7725 and CA111C based on MT9M114 are used directly.J35 supports both MT9M114 and OV7725 camera module, but 3.3 V is a violation to MT9M114 spec 3.1 V. Itproved fine for evaluation/demo with 3.3 V supply, but in product design, it is recommended to adjust DCDC outputor add level shifter.2.15User interface switchThere are four user interface switches on the MIMXRT1060/1064 EVK board.•Power switch•ON/OFF button•Reset button•USER button2.15.1Power switchSW1 is a slide switch to control the power of the MIMXRT1060/1064 EVK board when the power supply is from J2.•Sliding the switch to the ON position connects the 5 V power supply to the evaluation board main power system.•Sliding the switch to the OFF position immediately removes all power from the board.2.15.2ON/OFF buttonSW2 is the ON/OFF button for MIMXRT1060/1064 EVK board. A short pressing in OFF mode causes the internal power management state machine to change state to ON. In ON mode, a short pressing generates an interrupt as a software-controllable power-down. An approximate 5 seconds or more pressing causes a forced OFF. However, you can disconnect both the boot mode inputs.2.15.3Reset buttonThere are two Reset buttons on the EVK board. SW3 is the power-on reset button. Pressing SW3 in the power on state forces to reset the system power except SNVS domain. The processor immediately turns off and reinitiates a boot cycle from the processor power off state. SW9 is a reset button.2.15.4USER buttonSW8 is a USER button (GPIO5-00). Pressing the USER button can produce changes in high and low levels.2.16SensorU32 on the EVK board is a 6-Axis Ecompass (3-Axis Mag, 3-Axis Accel) sensor FXOS8700CQ. The Ecompass is connected to i.MX RT1060/1064 I2C1 port.The sensor is not populated on some boards.2.17User interface LED indicatorThere are four LED status indicators on the EVK board.The functions of these LEDs include:•Main Power Supply (D3)—Green: DC 5 V main supply is normal.—Red: J2 input voltage is over 5.6 V.—Off: Board is not powered.•Reset RED LED (D21)•OpenSDA LED (D20)•USER LED (D18)2.18LCD interfaceThe enhanced Liquid Crystal Display Interface (eLCDIF) is a general-purpose display controller.The eLCDIF block supports the following:•Displays that support moving pictures and require the RGB interface mode (DOTCLK interface).The eLCDIF provides fully programmable functionality to supported interfaces:•Bus master interface to source frame buffer data for display refresh.•8/16/18/24/32 bit LCD data bus support available depending on I/O MUX options.•Programmable timing and parameters for DOTCLK LCD interfaces.To use the LCD, NXP provides an optional LCD module RK043FN02H-CT. RK043FN02H-CT has a 4.3 inches touch screen and supports a resolution of up to 480*3(RGB)*272. This module contains two FPC cables. The LCD interface is connected to J8 (A1-A40) and the CPT interface can be connected to J8 (B1-B6). You can purchase LCD modules from .PCB informationThe MIMXRT1060/1064 EVK board is uses the standard 4-layer technology. The material used is FR-4. The PCB stack-up information is shown in Table 8.Table 8.Board stack-up informationEVK design filesYou can download, the schematics, layout files, and gerber files (including Silkscreen) from /MIMXRT1060-EVK.EVK contentsThe following table lists the contents on the evaluation kit.Table 9.EVK contentsItem DescriptionEVK board EVK board with processor, memory, interfaces and so on. USB cable USB cable (Micro-B to Standard-A).Camera CA111C based on MT9M114.Power adapter, micro-SD card, and LCD module are not standard parts of the evaluation kit.How To Reach Us Home Page: Web Support: /support Information in this document is provided solely to enable system and software implementers to use NXP products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. 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NB7NPQ1004MMTGEVB评估板用户手册说明书
NB7NPQ1004MMTGEVB NB7NPQ1004MMTGEVB Evaluation Board User's ManualIntroductionThe NB7NPQ1004MMTGEVB evaluation board was developed to provide a convenient platform to quickly verify the operation of the NB7NPQ1004M redriver in a USB type −A system environment.This evaluation board manual contains:•Information on the NB7NPQ1004M Evaluation Board •Board Schematics •Bill of MaterialsFeatures•Accommodates the Functional Evaluation of the Device•Acts as a Reference Design that can Easily be Modified for Active Cables, UFP (Upstream Facing Port), DFP (Downstream Facing Port), and DRP (Dual Role Port) Applications•Type −A Plug and Receptacle to Easily Place in the Existing System Environment•On Board Control Pins for Adjusting Settings without Compromising Form FactorPart DescriptionThe NB7NPQ1004M is a 3.3 V quad channel, linear redriver for USB 3.1 applications that supports both 5 and 10 Gbps data rates.Signal integrity degrades from PCB traces and transmission cables which may cause inter symbol interference (ISI). The NB7NPQ1004M compensates for these losses by engaging varying levels of equalization at the input receiver. The output transmitter circuitry provides user selectable flat gain settings to create the best eye openings for the outgoing data signals. The flexibility of this part allows it to fit into many system applications.After power up, the NB7NPQ1004M periodically checks both of the TX output pairs of each port for a 50 W termination for a Super Speed USB receiver. When the receiver is detected on either channel of a port, the internal RX termination will be enabled of that respective channel. The port becomes active once both TX outputs have detected 50 W termination, and the NB7NPQ1004M is set to perform the redriver function. Port AB (channels A & B) and port CD (channels C & D) are independent of each other.This manual should be used in conjunction with the device datasheet NB7NPQ1004M which contains full technical details on the devicespecifications and operation.EVAL BOARD USER’S MANUALFigure 1. NB7NPQ1004M Demo Board(Top View)BOARD MAP AND FUNCTIONAL SUMMARYJumper J75 to J82: These are forEQ/FG Gain control (H/F/R/L). Refer Datasheet for Pin setting andassociated EQ and FGJumper J83 to J84: These are EN Pin Jumpers for each the Channel A/B and C/D. Connecting to thelow will disable the ChannelVcc and GND Pins: These Pins can be used to Power the 1004 Device directly with 3.3 V supply and tomeasure the device currentCh C & DCh C & DCh A & BCh A & BResistor R2, R17, (R18, R19 on the Bottom Side):These are 0 W that connects to the USB 2.0 data line.These can be removed to ensure that only SuperSpeed data lines are active+Figure 2. NB7NPQ1004M Evaluation Board(Top View)Jumper J15: This Jumper enables the LDO when High. When Jumperis Low, the LDO is ShutdownJumper J14: This Jumper connects the 5 V USB Bus to theInput of the LDO3.3 V LDONB7NPQ1004MCh C & DCh C & DCh A & BCh A & BFigure 3. NB7NPQ1004M Evaluation Board(Bottom View)Jumper J13: This Jumperconnects the 3.3 V LDO Output tothe VCC of the 1004 DeviceSelect Power SourceThe NB7NPQ1004MMTGEVB has the flexibility to be powered through USB’s VBUS, or an external power supply. Table 1 and Figure 4 describe the jumper settings for each of the configuration.Monitoring Current / PowerThere are two easy ways to monitor the current consumed by the redriver. If you are using an external power supply, you can simply use the current meter commonly found on the power supplies. If you would like to use a current probe, simply solder the probe between the VCC pin and the power supply. This will allow monitoring of the NB7PQ1004M’s current consumption.USB 2.0 Data LinesThe USB 2.0 lines can be disconnected by removing the 0 W resistors R2, R17, R18 and R19 on the D+ and D− lines.This is useful if you cannot easily tell whether the downstream facing port has acknowledged a Super Speed(+) connection with the inserted loss, or if it stepped down to High Speed data rates. When a receiver is detected through RxDetect, the DFP will initialize link training. It will send a test signal out at the highest data rate and expect to see the same signal sent back by the UFP. If the signals do not match due to ISI (or any other connection issues) then it will drop down the data rate to USB 2.0 speeds.On Windows machines, an easy way to tell that a Super Speed connection was not established is to look for a pop up in the task bar letting the user know that “This device can perform faster”. A disk benchmarking tool like Crystal Disk Mark that lets you test read and write speeds to a peripheralstorage can also be used.USB 5 V VBUSLDO 5 V InputLDO5 V OutputJ14J13VCC Test Pt.GND Test Pt.LDO3.3 VFigure 4. Power Source SelectionTable 1. SELECTING A POWER SOURCEUSB VBUS Place jumper on J14 and J13EXTERNAL SUPPLY Open J14 and connect a positive lead of an external supply to VCC and apply 3.3 V.Ensure that GND is connected to ground and that current limit is set to 300 mA.COMPLETE BOARD SCHEMATICS Figure 5. RE−DriverFigure 6. NB7NPQ1004M USB Type−A EvaluationBoard Schematics Figure 7. Power Supply SectionTEST POINTGNDTEST POINT1J13EQATXn1TXp1RXn1RXp1RXp2RXn2TXp2TXn2 RXp2RXn2TXp2TXn2TXn1TXp1RXn1RXp1BILL OF MATERIALSTable 2. BILL OF MATERIALSSl. No.Qty Description Reference Manufacturer Manufacturer PN 11USB 3.1 Redriver U4ON Semiconductor NB7NPQ1004M21 3.3 V Voltage Regulator U3ON Semiconductor NCP3335ADM330R2GGSB4111312HR 32USB Type−A Receptacle CN1_B, CN2_A AmphenolCommercial ProductsGSB416445CHR42 USB Type−A Plug CN1_A, CN2_B AmphenolCommercial Products52Capacitor 1 m F (0603)C21, C22 Samsung CL10A105KA5LNNC 68Capacitor 0.220 m F (0402)C4, C8, C15, C18, C23,TDK C1005X5R1C22M050BBC24, C25, C26TDK C1005X5R1C334K050BB 78Capacitor 0.33 m F (0402)C27, C28, C29, C30,C38, C39, C40, C4181Blue LED D1Rohm Semiconductor SMLE12BC7TT86 911Header, 0.100”J75 to J84, J15Amphenol FCI68001−203HLF 107Header, 0.100”J13, J14Amphenol FCI 77311−118−02LF 114Resistor 0.0 W (0402)R2, R17, R18, R19 YAGEO RC0402JA−070RLPanasonic ERJ−2RKF6802X 128Resistor 68 k W (0402)R3, R8, R9, R10, R11,R12, R13138Resistor 200 k W (0402)R20 to R23, R28 to R31Panasonic ERJ−2RKF2003X 141Resistor 1 k W (0402)R7Panasonic ERJ−2RKF1001X 152TEST POINT TP1, TP2 Keystone5016ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed atON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.PUBLICATION ORDERING INFORMATION。
VSC8584芯片评估板用户指南说明书
VSC8584User Guide VSC8584 Evaluation BoardJanuary 2014Contents1Revision History (1)1.1Revision 1.0 (1)2Introduction (2)3General Description (3)3.1Key Features (3)3.1.1Copper Port RJ45 Connections (3)3.1.2SGMII/QSGMII MAC SMA (3)3.1.3Switch Block Control (3)3.1.4Zarlink ZL30343 SyncE G.8262/SETS (3)3.1.5External 1588 Clock Option (4)3.1.6External RefClk Option (4)3.1.71588 Daisy-Chain SPI Time-Stamping Connection (4)3.1.8Network Interface Microcontroller Card (5)4Quick Start (6)4.1Connecting the Power Supply (6)4.2PC Software Installation (6)4.3Connecting to the Board to the PC (6)4.3.1Changing the IP Address of the Board (6)4.4Using the Control Software (7)4.4.1CAT5 to SGMII with Clause 37 AutoNeg Enabled (7)4.4.2Board Initialization and Running PGY Scripts (8)4.4.3Copper Media Operation (1000BASE-T) (9)4.4.4Fiber Media Operation (1000BASE-X) (10)4.4.5Fiber Media Operation (100BASE-FX) (10)4.5Useful Registers (10)4.5.1Ethernet Packet Generator (10)4.5.2Copper PHY Error Counters (10)4.5.3Fiber PHY Error Counters (10)4.5.4Configuring 1588 Daisy-Chain SPI Time-Stamping (11)5Additional Information (12)1Revision HistoryThe revision history describes the changes that were implemented in this document. The changes arelisted by revision, starting with the most current publication.1.1Revision 1.0Revision 1.0 of this datasheet was published in January 2014. This was the first publication of thedocument.2IntroductionThe VSC8584 device is a low-power, quad-port Gigabit Ethernet transceiver with four SerDes interfacesfor quad-port dual media capability. It also includes an integrated quad port I2C multiplexer (MUX) tocontrol SFPs or PoE modules. The VSC8584 supports IEEE 802.1AE 128/256-bit MACsec protocols tomeet the security requirements for protecting data traversing Ethernet LANs, and also includes Vitesse’spatent-pending distributed timing technology VeriTime™ that delivers the industry’s most accurate IEEE1588v2 timing implementation. The VSC8584 device offers a seamless integration between IEEE 1588v2and the MACsec engine with no loss of precision. The VSC8584 also supports a ring resiliency featurethat allows a 1000BASE-T connected PHY port to switch between master and slave timing withouthaving to interrupt the 1000BASE-T link.This document describes the architecture and usage of the VSC8584 Evaluation Board (VSC8584EV). TheVSC8584EV may be used to evaluate a family of devices which include VSC8584. These devices vary withrespect to the number of ports, supported interfaces, and available features. This document specificallyThe Quick Startaddresses the VSC8584 device. section describes how to bring-up the evaluation boardalong with install and run the graphical user interface (GUI), used to control the evaluation board.Figure 1 • VSC8584EV Evaluation BoardThe following reference documents provide additional information about the operation of the VSC8584evaluation board.https:///products/product.php?number=VSC8564VSC8564 Datasheet ()VSC8582 Datasheet ()https:///products/product.php?number=VSC8582https:///products/product.php?number=VSC8575VSC8575 Datasheet ()VSC8584 Datasheet ()https:///products/product.php?number=VSC8584IEEE1588v2 and SyncE – Applications and Operation Using Vitesse’s Synchronization Solution/products/download.php?fid=4767&number=VSC8574()https:///products/product.php?number=VSC8584VSC8584 GUI ()3General DescriptionThe evaluation board in Figure 1 provides the user a way to evaluate the VSC8584 device in multipleconfigurations. Four RJ-45 connectors are provided for copper media interfaces. The four SFP cagesallow for evaluation of the fiber media interconnects. The MAC interface is provided via SMAconnectors.For access to all of the features of the device, an external microcontroller is used to configure the on-board clock chip via a two-wire serial bus and the VSC8584 via the MDIO bus. The graphical userinterface (GUI) enables the user to access the registers.The evaluation board uses a Zarlink device to synthesize a 125 MHz reference clock signal from a 20MHz crystal which serves as the REFCLK input.3.1Key Features3.1.1Copper Port RJ45 ConnectionsPHY Ports 2 and 3 use UDE RTA 1648BAK1A with integrated magnetic while PHY Ports 0 and 1 usegeneric RJ45 connectors with discrete Pulse H5008 magnetics.3.1.2SGMII/QSGMII MAC SMASGMII SMA connections are provided for all PHYs while the QSGMII SMA connection is available only onPHY0.3.1.3Switch Block ControlSet the SW1 switch as shown in the figure below.Figure 2 • SW1 Switch Control3.1.4Zarlink ZL30343 SyncE G.8262/SETSThe Zarlink ZL30343 is initialized by default to provide a 125 MHz differential LVPECL clock to VSC8584REFCLK inputs. (Note: the ZL30343 can be programmed to provide LVDS differential clock in conjunctionwith an LVDS termination provided for REFCLK, please refer to the Zarlink manual for programming itsoutput drive).Also, the ZL30343 can support synchronization with the VSC8584 PHY recovered clock for SyncEoperation. The ZL30343 is initialized to lock a recovered clock output if one is enabled and availablefrom the VSC8584 PHY. If no recovered clock signal is available, then the ZL30343 will select the crystaloscillator (U16) as default reference source for holdover operation. ZL30343 will indicate locked versusholdover status by driving LED D33 or D34. See the Zarlink documentation for more discussionconcerning its operation. See the VSC8584 datasheet for configuring recovered clock output pinbehavior.Please ensure three-way resistive connections R19 and R22 are appropriately connected to feedback theVSC8584’s recovered clock outputs into the ZL30343 device, if synchronization to a recovered clocksource is desired.3.1.5External 1588 Clock OptionThe user may choose to provide an external 1588 REFCLK via SMA connections to J65 and J66. Zero ohmjumpers may need to be removed and or installed to connect via these clock inputs. The board is builtwith connections for external 1588 REFCLK, unless otherwise indicated in documentation accompanyingthe specific board delivered.3.1.6External RefClk OptionThe user may choose to provide an external PHY REFCLK via SMA connections to J21 and J23. Zero ohmjumpers may need to be removed and or installed to connect via these clock inputs. As per section 2.1.4,and unless otherwise indicated in documentation accompanying the specific board, the board is builtwith a REFCLK connection driven by the ZL30343, instead of using an external REFCLK source.3.1.71588 Daisy-Chain SPI Time-Stamping ConnectionThe VSC8584 device enables daisy-chaining multiple devices to reduce the number of pins required totransmit time stamping information to system ASICs gathering IEEE 1588 time stamps. For users withtwo or more 8584EV boards, the following single-ended connections shown below are required fromthe master device to slave device:J75 pin 6 to J77 pin 6 (1588_SPI_CLK output → input)J75 pin 4 to J77 pin 4 (1588_SPI_CS ouput → input)J75 pin 2 to J77 pin 2 (1588_SPI_MISO output → 1588_SPI_MOSI input)See section 3.5.4 for register programming to enable this interface.Recommendation: for SPI daisy chaining use a Molex 10 pin ribbon cable with one-to-one connectionsFigure 3 • 1588 Daisy-Chain SPI InterconnectOnce enabled along with proper initialization of the 1588 IP block, time-stamped 1588 traffic in theegress direction will generate a similar sequence on the serialized timestamp daisy-chain as shown inthe following illustration. See the VSC8584 datasheet section about Serial Time Stamp Output Internfacefor a more detailed functional description.Figure 4 • 1588 Daisy-Chain SPI Traffic Pattern (PHY port 3 egress)3.1.8Network Interface Microcontroller CardA “Rabbit” microcontroller card is included to facilitate a software interface to the registers on theVSC8584. The controller card has a hard coded static IP address. Refer to the label on the card for thevalue. This address is required by the user to initiate communications via the board and the GUI.Note: The factory programmed Rabbit board IP address is 10.9.70.193.1. 2. 3. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 4Quick Start This section shows the quick start for the VSC8584.4.1Connecting the Power SupplyThe evaluation board uses 5 VDC to power the on-board regulators creating the 3.3 V, 2.5 V, and 1.0 V rails which drive the devices as well as modules. The evaluation board can be powered up using the power pack which provides the 5 VDC. Simply plug the AC adaptor into a wall socket and the barrel end into J67 (see the upper right corner of Figure 1). Immediately the user should see several LEDs turn on.4.2PC Software InstallationDownload the ZIP file to the PC’s root directory, normally C:\.Extract to C:\Double-click the icon to launch the GUI (It is acceptable to drag the icon to the desktop)4.3Connecting to the Board to the PCThe Rabbit board can interface with a PC either through a direct connection to the PC or if configured properly through a local area network. The latter option requires the user to configure the Rabbit’s IP address so as to properly reside on the user’s network.The IP address of the board should be written on the Rabbit network interface daughter board card. The default value should be 10.9.70.193. Use this IP address to initially access the board for operation or to change its IP address.4.3.1Changing the IP Address of the BoardDetermine and write down the new unique IP address you wish to change the board to.Directly connect an Ethernet cable from a PC to the Rabbit board.: Some older PCs do not support auto-crossover on the Ethernet connection so a cross-over NOTE cable may be unch a DOS command window by clicking on the Start->Run button and typing “cmd”.Within the DOS command window type "Telnet."In Telnet, connect to the Rabbit board’s address using the open command by typing “open 10.9.70.^XXX”.10.9.70.xxx where xxx is the value on your board from the factory (typically 193).You should have a prompt and be able to type help to get a list of commands available on the Rabbit.a) If you are unable to connect, then most likely you will need to change the IP address of the connected PC to have the first 3 octets similar to the board by following the subsequent steps.b) On the PC under Windows -> Control Panel ->Network Connections -> Local Area Connection, right mouse-click for properties. Under the General tab highlight Internet Protocol (TCP/IP) and click on Properties. From there enter the new PC IP address such as 10.9.70.yyy where yyy is a unique value and NOT the same as the Rabbit board. Once complete, return to step mand the board to change its IP address to the new one by typing into Telnet now connected to the board the command: set ip <new IP address> <Enter> where <new IP address> is in the form xxx.xxx.xxx.xxx. Once you hit <Enter> the IP address will be changed and the Rabbit will save the value and reboot which may take approximately 1 minute. The Telnet session will disconnect from the board.Change your PC IP address to the same IP network as the Rabbit board.Telnet to the Rabbit e the following commands to complete configuration of the Rabbit board:a) set netmask xxx.xxx.xxx.xxx b) set gateway xxx.xxx.xxx.xxx c) save env Please record and inform Microsemi of the new IP address of the board when you return so that Microsemi can connect to and reconfigure the board.Re-label the Rabbit board with the new IP.4.4Using the Control Software4.4.1CAT5 to SGMII with Clause 37 AutoNeg EnabledConnect the VSC8584EV Rabbit microcontroller RJ-45 directly to the PC or through a network switch ifproperly configured. Apply 5 VDC to the EVB.Launch the GUI by double-clicking the GUI shortcut located in C:\ViperGUI_4_67 or on the desktop if ithas been moved there. The GUI connection window shown in the following figure should appear.Figure 5 • GUI Connection WindowTo make a connection to the EVB, click “Rabbit” and enter the IP address of the EVB, then click on"Connect." The display next to the IP address window should change to "Connected." If it does not,check the IP address, or your network configuration until connection with the EVB can be successfullyestablished.Double-click on “MII Registers” and the window shown in Figure 6 should appear:Figure 6 • MII Registers GUI WindowBe sure the device is up and running by reading MII Register 0. It should read back 0 × 1040. Readingback all 0’s or all 1’s indicates a problem. A checked box means the bit is set to “1,” if unchecked it is“0.”4.4.2Board Initialization and Running PGY ScriptsOnce the evaluation board connectivity has been established and confirmed, the PHY should beinitialized. Initialization can be accomplished by running an init-script sequence, such as performed bythe pre- and post-reset functions of the PHY API standalone app.While the init-script sequence may not required for specific operational modes, an init-script sequenceis highly recommended to ensure correct performance over the greatest set of user scenarios for thePHY. After initialization is performed, refer to the PHY Datasheet section on Configuring of the PHY andPHY Interfaces for the desired application.In order to execute an init-script, double-click on “Run PHY Script” within the GUI Connection Windowto launch the Run PHY Script window as shown in Figure 7. This enables a user to load a script toconfigure the device rather than navigating through Registers pages. Click “Load” button, browse to adesired script file via the pop-up panel, finally click “Run” button. After execution is completed, youshould see read-back values in decimal as shown in the following figure.The script syntax is command, phy address (in decimal), register address (in decimal), and registercontent (in either hexadecimal or decimal).1. 2. 3. 4. 5. 6. content (in either hexadecimal or decimal).Figure 7 • Run PHY Script GUI Window (after script is loaded)Figure 8 • Run PHY Script GUI Window (after script is loaded)4.4.3Copper Media Operation (1000BASE-T)A single register write and some external coax cables enables 1G Ethernet traffic to be received by the VSC8584 RJ-45 port, routed through the VSC8584 and externally via coax loopback cables through the SGMII interface and transmitted back to the traffic source on the same copper port. First configure the SerDes in SGMII mode by writing to Micro page 18’d. This is a global setting and does not need to be applied per port.Steps for external SGMII loopback:Set up the copper traffic source (i.e., IXIA or Smartbits)Connect an Ethernet cable to an RJ-45 Port 0.Connect two matched coax cables, J1 - J4 and J2 - J5.Write using the "Micro Page Registers" window: 18'd 0 × 80F0When "Micro Page" 18'd is read back, bit 15 will clear.Linkup bit is in MII Reg 1, bit 2 (MII 1.2), read twice to update.Traffic should be the following:Steps for SGMI forwarding port 0 ↔ port 1:1. 2. 3. 4. 5. 6. 1. 2. 3. 4. 5. 6. 1. 2. 3. 4. 5. 6. Steps for SGMI forwarding port 0 ↔ port 1:Set up the Copper traffic source (i.e., IXIA or Smartbits)Connect an Ethernet cable to an RJ-45 Port 0.Connect two matched coax cables as follows:J1 <TDIN0+> to J6 <RXDOUT1+>J2 <TDIN0-> to J7 <RXDOUT1→J5 <RXDOUT0-> to J10 <TXDIN1→J4 <RXDOUT0+> to J9 <TXDIN1+>Write using the "Micro Page Registers" window: 18'd 0 × 80F0.When “Micro Page” 18’d is read back, bit 15 will clear.Linkup bit is in MII Reg 1, bit 2 (MII 1.2), read twice to update4.4.4Fiber Media Operation (1000BASE-X)Follow all steps in section 3.4.2 with fiber media connection to (IXIA) and add the following steps.Write using the “Micro Page Registers” window: 18’d 0 × 8FC1. (Global)When “Micro Page” 18’d is read back, bit 15 will clear.Write “MII Register” (PHY 0) 23’d 0 × 0204 (Sets Media Mode)Write “MII Register” (PHY0) 0’d 0 × 9040 (SW Reset for media mode setting to have effect)Write “Extended MII Register” (PHY0) 19’d 0 × 0001 (Flip SIGDET polarity if necessary)Write “MII Register” (PHY0) 0’d 0 × 0004 (Disable Auto Neg if necessary)Traffic should be flowing.4.4.5Fiber Media Operation (100BASE-FX)Follow all steps in section 3.4.2 with fiber media connection to (IXIA) and add the following steps.Write using the “Micro Page Registers” window: 18’d 0x8FD1. (Global)When “Micro Page” 18’d is read back, bit 15 will clear.Write “MII Register” (PHY 0) 23’d 0x0304 (Sets Media Mode)Write “MII Register” (PHY0) 0’d 0x9040 (SW Reset for media mode setting to have effect)Write “Extended MII Register” (PHY0) 19’d 0x0001 (Flip SIGDET polarity if necessary)Write “MII Register” (PHY0) 0’d 0x0004 (Disable Auto Neg if necessary)Traffic should be flowing.4.5Useful Registers 4.5.1Ethernet Packet GeneratorExtMII 29E is the Ethernet Packet Generator register. Refer to datasheet for configuration options.A Good CRC packet counter is in ExtMII 18.13:0. A read of the register reads back the good CRC packets and then clears the register so the subsequent reads will be 0 if no traffic has been received. If traffic has been received since the last read, bit 15 will be set.4.5.2Copper PHY Error CountersIdle errors = MII 10.7:0RX errors = MII 19.7:0False carrier = MII 20.7:0Disconnects = MII 21.7:0CRC errors = ExtMII 23.7:04.5.3Fiber PHY Error CountersGood RX CRC packets = Ext3MII 28.13:0Bad RX CRC packets = Ext3MII 29.7:0Good TX CRC packets = Ext3MII 21.13:0Bad TX CRC packets = Ext3MII 22.7:04.5.4Configuring 1588 Daisy-Chain SPI Time-StampingFor Master VSC8584EV, run these instructions for each port 0-3, as indicated by the “phy” variablebelow:smiwrite phy 31 4smiwrite phy 17 133smiwrite phy 18 0smiwrite phy 16 45088smiwrite phy 17 133smiwrite phy 18 0smiwrite phy 16 47136smiwrite phy 31 0Note:the accesses above can be pasted into a text file and loaded via the customer GUI “Run PHY Script” feature, after substituting the desired port number 0-3 for “phy”above.For Slave VSC8584EV, run the same instructions listed above for Master VSC8584EV for each port 0-3.Then, run the following write only on port 0:smiwrite 0 31 4smiwrite 0 26 0 × c0f7smiwrite 0 31 05Additional InformationFor any additional information or questions regarding the devices mentioned in this document, contactyour local sales representative.Microsemi HeadquartersOne Enterprise, Aliso Viejo,CA 92656 USAWithin the USA: +1 (800) 713-4113Outside the USA: +1 (949) 380-6100Sales: +1 (949) 380-6136Fax: +1 (949) 215-4996Email:***************************© Microsemi. All rights reserved. Microsemi and the Microsemi logo are trademarks of Microsemi Corporation. All other trademarks and service marks are the property of their respective owners.Microsemi makes no warranty, representation, or guarantee regarding the information contained herein or the suitability of its products and services for any particular purpose, nor does Microsemi assume any liability whatsoever arising out of the application or use of any product or circuit. The products sold hereunder and any other products sold by Microsemi have been subject to limited testing and should not be used in conjunction with mission-critical equipment or applications. Any performance specifications are believed to be reliable but are not verified, and Buyer must conduct and complete all performance and other testing of the products, alone and together with, or installed in, any end-products. Buyer shall not rely on any data and performance specifications or parameters provided by Microsemi. It is the Buyer's responsibility to independently determine suitability of any products and to test and verify the same. The information provided by Microsemi hereunder is provided "as is, where is" and with all faults, and the entire risk associated with such information is entirely with the Buyer. Microsemi does not grant, explicitly or implicitly, to any party any patent rights, licenses, or any other IP rights, whether with regard to such information itself or anything described by such information. Information provided in this document is proprietary to Microsemi, and Microsemi reserves the right to make any changes to the information in this document or to any products and services at any time without notice.Microsemi, a wholly owned subsidiary of Microchip Technology Inc. (Nasdaq: MCHP), offers a comprehensive portfolio of semiconductor and system solutions for aerospace & defense, communications, data center and industrial markets. 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芯通芯片评估板用户指南 UG-553说明书
Evaluation Board User GuideUG-553One Technology Way • P .O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • Evaluating the ADM7150 and ADM7151 Linear RegulatorsPLEASE SEE THE LAST PAGE FOR AN IMPORTANT WARNING AND LEGAL TERMS AND CONDITIONS.Rev. 0 | Page 1 of 8REGULATOR FEATURESInput voltage range: 4.5 V to 16 V Maximum output current: 800 mA Low noise1.2 µV RMS total integrated noise from 100 Hz to 100 kHz 2 µV RMS from 10 Hz to 100 kHz Initial accuracy: ±1%Fixed 5 V (ADM7150) and adjustable (ADM7151) output versions8-lead LFCSP package and SOIC packageEVALUATION KIT CONTENTSADM7150CP-EVALZ or ADM7151CP-02-EVALZ evaluation boardADDITIONAL EQUIPMENT NEEDEDDC power supplyMultimeters for voltage and current measurements Electronic or resistive loadsGENERAL DESCRIPTIONThe ADM7150CP-EV AL Z and ADM7151CP-02-EV AL Z evaluation boards are used to demonstrate the functionality of the ADM7150 and ADM7151 linear regulators, respectively. Simple device measurements, such as line and load regulation, dropout, and ground current, can be demonstrated with just a single voltage source, a voltmeter, an ammeter, and load resistors. For more details about the linear regulators, refer to theADM7150 and ADM7151 data sheets.EVALUATION BOARD11481-001Figure 1. ADM7150CP-EVALZ /ADM7151CP-02-EVALZLFCSP Evaluation BoardUG-553Evaluation Board User GuideRev. 0 | Page 2 of 8TABLE OF CONTENTSRegulator Features ............................................................................ 1 Evaluation Kit Contents ................................................................... 1 Additional Equipment Needed ....................................................... 1 General Description ......................................................................... 1 Evaluation Board .............................................................................. 1 Revision History ............................................................................... 2 Evaluation Board Hardware ............................................................ 3 Evaluation Board Configurations .............................................. 3 Output Voltage Measurements ....................................................... 4 Line Regulation ..............................................................................4 Load Regulation ............................................................................5 Dropout Voltage ............................................................................5 Ground Current Measurements ......................................................6 Ground Current Consumption ...................................................6 Schematic ............................................................................................7 Ordering Information .......................................................................8 Bill of Materials (8)REVISION HISTORY11/13—Revision 0: Initial VersionEvaluation Board User GuideUG-553Rev. 0 | Page 3 of 8EVALUATION BOARD HARDWAREEVALUATION BOARD CONFIGURATIONSThe evaluation boards arrive supplied with differentcomponents depending on which version is ordered. Components common to both versions are C1, C2, R3, J1, and J2.Resistors R1 and R2 are used for the ADM7151 adjustable output option. The output voltage is set byV OUT = 1.5 V × (1 + R1/R2).Table 1. Evaluation Board Hardware ComponentsComponent FunctionDescriptionU11 Linear regulator ADM7150ACPZ-5 or ADM7151ACPZ-02 linear regulator. C1 Input capacitor 10 μF input bypass capacitor.C2 Output capacitor 10 μF output capacitor. Required for stability and transient performance. C3 V REF capacitor 1 μF V REF bypass capacitor. C4 BYP capacitor 1 μF bypass capacitor.C5V REG capacitor 10 μF V REG bypass capacitor. C6 and C7 Output capacitor Optional output capacitors.R1 Output divider Sets output voltage with R2 in adjustable option. Short R1 for fixed output voltages. R2 Output divider Sets output voltage with R1 in adjustable option. JP1Jumper Jumper. Connects EN to VIN for automatic startup.1Component varies depending on the evaluation board ordered.UG-553Evaluation Board User GuideRev. 0 | Page 4 of 8OUTPUT VOLTAGE MEASUREMENTSFigure 2. Output Voltage Measurement, LFCSPFigure 2 shows how the evaluation board can be connected to a voltage source and a voltmeter for basic output voltage accuracy measurements. A resistor can be used as the load for the regulator.Ensure that the resistor has a power rating adequate to handle the power expected to be dissipated across it. An electronic load can also be used as an alternative. Ensure that the voltage source can supply enough current for the expected load levels. Use the following steps to connect to a voltage source and voltmeter:1. Connect the negative terminal (−) of the voltage source toone of the GND pads on the evaluation board.2. Connect the positive terminal (+) of the voltage source tothe VIN pad of the evaluation board.3. Connect a load between the VOUT pad and one of theGND pads.4. Connect the negative terminal (−) of the voltmeter to oneof the GND pads.5. Connect the positive terminal (+) of the voltmeter to theVOUT pad. The voltage source can now be turned on. If JP1 is inserted (connecting EN to VIN for automatic startup), the regulator powers up.If the load current is large, the user needs to connect the voltmeter as close as possible to the output capacitor to reduce the effects of IR drops.LINE REGULATIONFor line regulation measurements, the regulator’s output is monitored while its input is varied. For good line regulation, the output must change as little as possible with varying input levels. To ensure that the device is not in dropout during this measurement, V IN must be varied between V OUTNOM + 1.5 V (or 4.5 V , whichever is greater) and V INMAX . For example, for an ADM7150 with fixed 5 V output, V IN needs to be variedbetween 6.5 V and 16 V . This measurement can be repeated under different load conditions. Figure 3 shows the typical line regu-lation performance of an ADM7150 with fixed 5 V output.V O U T (V )V IN (V)16121410864.954.964.974.984.995.005.015.025.035.045.0511481-006Figure 3. Output Voltage vs. Input VoltageEvaluation Board User GuideUG-553Rev. 0 | Page 5 of 8LOAD REGULATIONFor load regulation measurements, the regulator’s output is monitored while the load is varied. For good load regulation, the output must change as little as possible with varying loads. The input voltage must be held constant during this measurement. The load current can be varied from 0 mA to 800 mA. Figure 4 shows the typical load regulation performance of an ADM7150 with fixed 5 V output for an input voltage of 6.5 V .V O U T (V )I LOAD (mA)10001001014.954.964.974.984.995.005.015.025.035.045.0511481-007Figure 4. Output Voltage vs. Load CurrentDROPOUT VOLTAGEDropout voltage can be measured using the configuration shown in Figure 2. Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only for output voltages greater than 4.5 V . Dropout voltage increases with larger loads. For more accurate measurements, a second voltmeter can be used to monitor the input voltage across the input capacitor. The input supply voltage may need to be adjusted to account for IR drops, especially if large load currents are used. Figure 5 shows a typical curve of dropout voltage measurements with different load currents.D R O P O U T V O L T A GE (m V )I LOAD (mA)100010010170060050040030020010011481-008Figure 5. Dropout Voltage vs. Load CurrentUG-553Evaluation Board User GuideRev. 0 | Page 6 of 8GROUND CURRENT MEASUREMENTS11481-009Figure 6. Ground Current Measurement, LFCSPFigure 6 shows how the evaluation board can be connected to a voltage source and an ammeter for ground currentmeasurements. A resistor can be used as the load for theregulator. Ensure that the resistor has a power rating adequate to handle the power expected to be dissipated across it. An electronic load can be used as an alternative. Ensure that the voltage source used can supply enough current for the expected load levels.Use the following steps to connect to a voltage source and ammeter:1. Connect the positive terminal (+) of the voltage source tothe VIN pad on the evaluation board.2. Connect the positive terminal (+) of the ammeter to one ofthe GND pads of the evaluation board.3. Connect the negative terminal (−) of the ammeter to thenegative (−) terminal of the voltage source.4. Connect a load between the negative (−) terminal of thevoltage source and the VOUT pad of the evaluation board. The voltage source can now be turned on. If JP1 is inserted (connecting EN to VIN for automatic startup), the regulator powers up.GROUND CURRENT CONSUMPTIONGround current measurements can determine how much current the regulator’s internal circuits are consuming while the circuits perform the regulation function. To be efficient, the regulator needs to consume as little current as possible. Typically, the regulator uses the maximum current when supplying its largest load level (800 mA). Figure 7 shows the typical ground current consumption for various load levels at an input voltage of 6.5 V for an output voltage of 5 V .G R O U N D C U R R E N T (m A )I LOAD (mA)10001001011234567891011481-011Figure 7. Ground Current vs. Load CurrentWhen the device is disabled (EN = GND), the ground current drops to less than 1 µA.Evaluation Board User GuideUG-553Rev. 0 | Page 7 of 8SCHEMATICC311481-003UG-553Evaluation Board User GuideRev. 0 | Page 8 of 8ORDERING INFORMATIONBILL OF MATERIALSTable 2.Quantity Reference Designator DescriptionManufacturer/Vendor Vendor Part Number 1 U1 ADM7150ACPZ-5 or ADM7151ACPZ-02 Analog Devices, Inc. ADM7150ACPZ-5 or ADM7151ACPZ-02 3 C1, C2, C5 Capacitor, MLCC, 10 μF, 25 V, 0805, X5R Murata (or equivalent) GRM216R61E106KA12 2 C3, C4 Capacitor, MLCC, 1 μF, 25 V, 0805, X5R Murata (or equivalent)GRM216R61E105KA12 1 JP1 Header, single, STR, 2 pins Sullins Connector Solutions PEC02SAAN 1R1, R2Resistor, 1%, 0603 caseVishay DaleCRCW0603xxxxFESD CautionESD (electrostatic discharge) sensitive device . Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality.Legal Terms and ConditionsBy using the evaluation board discussed herein (together with any tools, components documentation or support materials, the “Evaluation Board”), you are agreeing to be bound by the terms and conditions set forth below (“Agreement”) unless you have purchased the Evaluation Board, in which case the Analog Devices Standard Terms and Conditions of Sale shall govern. Do not use the Evaluation Board until you have read and agreed to the Agreement. Your use of the Evaluation Board shall signify your acceptance of the Agreement. This Agreement is made by and between you (“Customer”) and Analog Devices, Inc. (“ADI”), with its principal place of business at One Technology Way, Norwood, MA 02062, USA. Subject to the terms and conditions of the Agreement, ADI hereby grants to Customer a free, limited, personal, temporary, non-exclusive, non-sublicensable, non-transferable license to use the Evaluation Board FOR EVALUATION PURPOSES ONLY. Customer understands and agrees that the Evaluation Board is provided for the sole and exclusive purpose referenced above, and agrees not to use the Evaluation Board for any other purpose. Furthermore, the license granted is expressly made subject to the following additional limitations: Customer shall not (i) rent, lease, display, sell, transfer, assign, sublicense, or distribute the Evaluation Board; and (ii) permit any Third Party to access the Evaluation Board. As used herein, the term “Third Party” includes any entity other than ADI, Customer, their employees, affiliates and in-house consultants. The Evaluation Board is NOT sold to Customer; all rights not expressly granted herein, including ownership of the Evaluation Board, are reserved by ADI. CONFIDENTIALITY . This Agreement and the Evaluation Board shall all be considered the confidential and proprietary information of ADI. Customer may not disclose or transfer any portion of the Evaluation Board to any other party for any reason. Upon discontinuation of use of the Evaluation Board or termination of this Agreement, Customer agrees to promptly return the Evaluation Board to ADI. ADDITIONAL RESTRICTIONS. Customer may not disassemble, decompile or reverse engineer chips on the Evaluation Board. Customer shall inform ADI of any occurred damages or any modifications or alterations it makes to the Evaluation Board, including but not limited to soldering or any other activity that affects the material content of the Evaluation Board. Modifications to the Evaluation Board must comply with applicable law, including but not limited to the RoHS Directive. TERMINATION. ADI may terminate this Agreement at any time upon giving written notice to Customer. Customer agrees to return to ADI the Evaluation Board at that time. L IMITATION OF L IABIL ITY . THE EVALUATION BOARD PROVIDED HEREUNDER IS PROVIDED “AS IS” AND ADI MAKES NO WARRANTIES OR REPRESENTATIONS OF ANY KIND WITH RESPECT TO IT. ADI SPECIFICALL Y DISCLAIMS ANY REPRESENTATIONS, ENDORSEMENTS, GUARANTEES, OR WARRANTIES, EXPRESS OR IMPLIED, RELATED TO THE EVALUATION BOARD INCLUDING, BUT NOT LIMITED TO, THE IMPL IED WARRANTY OF MERCHANTABILITY, TITLE, FITNESS FOR A P ARTICUL AR PURPOSE OR NONINFRINGEMENT OF INTELLECTUAL PROPERTY RIGHTS. IN NO EVENT WILL ADI AND ITS LICENSORS BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT, OR CONSEQUENTIAL DAMAGES RESULTING FROM CUSTOMER’S POSSESSION OR USE OF THE EVALUATION BOARD, INCLUDING BUT NOT LIMITED TO LOST PROFITS, DELAY COSTS, LABOR COSTS OR LOSS OF GOODWILL. ADI’S TOTAL LIABILITY FROM ANY AND ALL CAUSES SHALL BE LIMITED TO THE AMOUNT OF ONE HUNDRED US DOLLARS ($100.00). EXPORT. Customer agrees that it will not directly or indirectly export the Evaluation Board to another country, and that it will comply with all applicable United States federal laws and regulations relating to exports. GOVERNING LAW. This Agreement shall be governed by and construed in accordance with the substantive laws of the Commonwealth of Massachusetts (excluding conflict of law rules). Any legal action regarding this Agreement will be heard in the state or federal courts having jurisdiction in Suffolk County, Massachusetts, and Customer hereby submits to the personal jurisdiction and venue of such courts. The United Nations Convention on Contracts for the International Sale of Goods shall not apply to this Agreement and is expressly disclaimed. ©2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. UG11481-0-11/13(0)。
Richtek RT9054 双通道低噪声低掉电电源说明书
RT9054®©Copyright 2017 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.Ordering InformationGeneral DescriptionThe RT9054 is a dual channel, low noise, and low dropout regulator sourcing up to 300mA at each channel. The range of output voltage is from 1.2V to 3.5V by operating from 2.5V to 5.5V input.The RT9054 offers 3% accuracy, extremely low dropout voltage (240mV @ 300mA), and extremely low ground current, only 27μA per LDO. The shutdown current is near zero current which is suitable for battery-power devices.Other features include current limiting, over temperature and output short circuit protection.The RT9054 is short circuit thermal folded back protected.The IC lowers its OTP trip point from 165°C to 110°C when output short circuit occurs (V OUT < 0.4V) providing maximum safety to end users.The RT9054 can operate stably with very small ceramic output capacitors, reducing required board space and component cost. The RT9054 is available in fixed output voltages in the WDFN-6L 1.6x1.6 packages.Portable Power Management 300mA Dual LDO RegulatorFeatures●Wide Operating Voltage Ranges : 2.5V to 5.5V ●Low-Noise for RF Application●No Noise Bypass Capacitor Required ●Fast Response in Line/Load Transient ●TTL-Logic-Controlled Shutdown Input ●Low Temperature Coefficient●Dual LDO Outputs (300mA/300mA)●Ultra-low Quiescent Current 27μA/LDO ●High Output Accuracy 3%●Short Circuit Protection●Thermal Shutdown Protection ●Current Limit Protection●Short Circuit Thermal Folded Back Protection ●Tiny 6-Lead WDFN Packages●RoHS Compliant and Halogen FreeApplications●CDMA/GSM Cellular Handsets ●Battery-Powered Equipment●Laptop, Palmtops, Notebook Computers ●Hand-Held Instruments ●PCMCIA Cards●Portable Information AppliancesMarking InformationFor marking information, contact our sales representative directly or through a Richtek distributor located in your area.VOUT2 > VOUT1 is RecommendedNote :Richtek products are :❝ RoHS compliant and compatible with the current require-ments of IPC/JEDEC J-STD-020.❝ Suitable for use in SnPb or Pb-free soldering processes.RT9054©Copyright 2017 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.Typical Application CircuitPin ConfigurationV OUT2V OUT1VIN EN2VOUT1GNDVOUT2EN1(TOP VIEW)WDFN-6L 1.6x1.6RT9054©Copyright 2017 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.Functional Block DiagramVOUT1VINGNDVOUT2GNDRT9054©Copyright 2017 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.Electrical Characteristics(V IN = V OUTx + 1V, V ENx = V IN , C IN = 1μF, C OUT = 4.7μF, T A = 25°C, unless otherwise specified.)Recommended Operating Conditions (Note 4)●Supply Input Voltage ------------------------------------------------------------------------------------------------------2.5V to 5.5V ●Enable Input Voltage ------------------------------------------------------------------------------------------------------0V to 5.5V●Junction T emperature Range --------------------------------------------------------------------------------------------−40°C to 125°C ●Ambient T emperature Range --------------------------------------------------------------------------------------------−40°C to 85°CAbsolute Maximum Ratings (Note 1)●Supply Input Voltage ------------------------------------------------------------------------------------------------------−0.3V to 7V ●Other I/O Pin Voltages ---------------------------------------------------------------------------------------------------−0.3V to 7V ●Power Dissipation, P D @ T A = 25°CWDFN-6L 1.6x1.6---------------------------------------------------------------------------------------------------------0.571W ●Package Thermal Resistance (Note 2)-----------------------------------------------------------------------------WDFN-6L 1.6x1.6, θJA ----------------------------------------------------------------------------------------------------175°C/W ●Junction T emperature -----------------------------------------------------------------------------------------------------150°C ●Lead Temperature (Soldering, 10 sec.)-------------------------------------------------------------------------------260°C●Storage T emperature Range --------------------------------------------------------------------------------------------−65°C to 150°C ●ESD Susceptibility (Note 3)HBM (Human Body Mode)----------------------------------------------------------------------------------------------2kV MM (Machine Mode)------------------------------------------------------------------------------------------------------200VRT9054©Copyright 2017 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.Note 1. Stresses beyond those listed “Absolute Maximum Ratings ” may cause permanent damage to the device. These arestress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect device reliability.Note 2. θJA is measured at T A = 25°C on a low effective thermal conductivity single-layer test board per JEDEC 51-3. θJC ismeasured at the exposed pad of the package.Note 3. Devices are ESD sensitive. Handling precaution recommended.Note 4. The device is not guaranteed to function outside its operating conditions.Note 5. The dropout voltage is defined as V IN -V OUT , which is measured when V OUT is V OUT(NORMAL) − 100mV.Note 6. It is guaranteed by design.RT9054©Copyright 2017 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.Typical Operating CharacteristicsOutput Voltage vs. Temperature1.71.751.81.851.9-50-25255075100125Temperature O u t p u t V o l t a g e (V )(°C)Output Voltage vs. Temperature3.23.253.33.353.4-50-25255075100125Temperature O u t p u t V o l ta g e (V )(°C)RT9054-GS, Both I LOAD = 1mA V IN = 3.8V to 4.8VV IN (V)Time (100μs/Div)V OUT1(10mV/Div)4.83.8V OUT2(10mV/Div)Quiescent Current vs. Temperature5055606570-50-25255075100125Temperature Q u i e s c e n t C u r r e n t (u A )(°C)Power On from V INTime (10μs/Div)RT9054-FM, V EN1 = V EN2 = 1.5V Both I LOAD = 10mAV IN (5V/Div)V OUT2(2V/Div)V OUT1(1V/Div)Dropout Voltage vs. Load Current050100150200250300350050100150200250300Load Current (mA)D r o p o u t V o l ta g e (m V )RT9054©Copyright 2017 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.RT9054-GS, Both I LOAD = 100mA V IN= 3.8V to 4.8VV IN (V)Time (100μs/Div)V OUT1(10mV/Div)4.83.8V OUT2(10mV/Div)RT9054-GS, Both I LOAD = 10mA V IN = 3.8V to 4.8VV IN (V)V OUT1(10mV/Div)4.83.8VOUT2(10mV/Div)Time (100μs/Div)RT9054-GS, Both I LOAD = 50mA V IN = 3.8V to 4.8VV IN (V)Time (100μs/Div)V OUT1(10mV/Div)4.83.8V OUT2(10mV/Div)Time (250μs/Div)I OUT(50mA/Div)V OUT2(20mV/Div)V OUT1(20mV/Div)RT9054-GS, I LOAD = 10mA to 50mA V IN = V EN = 4.3VLoad Transient ResponseTime (250μs/Div)I OUT(100mA/Div)V OUT2(20mV/Div)V OUT1(20mV/Div)RT9054-GS, I LOAD = 10mA to 100mA V IN = V EN = 4.3VPower On from ENTime (5μs/Div)RT9054-FM, V IN = 5V I OUT1 = I OUT2 = 50mA(5V/Div)(1V/Div)V EN1 = V EN2V OUT1V OUT2RT9054©Copyright 2017 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.-80-60-40-2020101001000100001000001000000Frequency(Hz)P S R R (d B )1M100k 10k 1k NoiseTime (10ms/Div)RT9054-GS, No LOADV IN = V ENx = 4.5V(By battery)N o i s e (μV /D i v )150100500-50-100-150NoiseTime (10ms/Div)RT9054-GS, I LOAD = 50mA V IN = V ENx = 4.5V(By battery)N o i s e (μV /D i v )3002001000-100-200-300EN Pin Shutdown ResponseTime (50μs/Div)RT9054-FM, V IN = 5V I OUT1 = I OUT2 = 50mA(5V/Div)(1V/Div)V EN1 = V EN2V OUT1V OUT2V EN1(2V/Div)(1V/Div)V EN1V OUT1V OUT2EN1 Pin Shutdown ResponseV EN2V EN2(2V/Div)Time (10ms/Div)EN2 Pin Shutdown Response(1V/Div)V EN1V OUT1V OUT2V EN2V EN1(2V/Div)V EN2(2V/Div)Time (10ms/Div)RT9054©Copyright 2017 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.Application InformationLike any low-dropout regulator, the external capacitors used with the RT9054 must be carefully selected for regulator stability and performance. Using a capacitor value is >1μF on the RT9054 input, and the amount of capacitance can be increased without limit. The input capacitor must be located at a distance of not more than 0.5 inch from the input pin of the IC and returned to a clean analog ground.Any good quality ceramic or tantalum can be used for this capacitor. The capacitor with larger value and lower ESR (equivalent series resistance) provides better PSRR and line-transient response.The output capacitor must meet both requirements for minimum amount of capacitance and ESR in all LDO applications. The RT9054 is designed specifically to work with low ESR ceramic output capacitor under space-saving and performance consideration. Using a ceramic capacitor with value at least 4.7μF and ESR is > 20m Ω on the RT9054 output ensures stability. The RT9054 still works well with output capacitor of other types due to the wide stable ESR range. Figure 1. shows the curves of allowable ESR range as a function of load current for various output capacitor values. Output capacitor of larger capacitance can reduce noise and improve load transient response,stability, and PSRR. The output capacitor should be located not more than 0.5 inch from the VOUT pin of the RT9054and returned to a clean analog ground.Figure 1. Stable Cout ESR RangeThermal ConsiderationsThermal protection limits power dissipation in RT9054.When the operation junction temperature exceeds 170°C,the OTP circuit starts the thermal shutdown function and turns the pass element off. The pass element turns on again after the junction temperature cools by 40°C. The RT9054 lowers its OTP trip level from 170°C to 110°C when output short circuit occurs (V OUT < 0.4V) as shown in Figure 2. It limits the IC case temperature to under 100°C and provides maximum safety to customer while output short circuit occurs.For continuous operation, do not exceed absolute maximum operation junction temperature 125°C. The power dissipation definition in device is :P D = (V IN -V OUT ) x I OUT + V IN x I QThe maximum power dissipation depends on the thermal resistance of the IC package, PCB layout, rate of surrounding airflow and temperature difference between junction to ambient. The maximum power dissipation can be calculated by the following formula :P D(MAX) = (T J(MAX) − T A ) /θJAwhere T J(MAX) is the maximum operation junction temperature, T A is the ambient temperature and θJA is the junction to ambient thermal resistance.Figure 2. Short Circuit Thermal Folded Back Protectionwhen Output Short Circuit Occurs (Patent)V OUT Short to GNDV OUTI OUTT SDRegion of Stable C OUT ESR vs. Load Current0.0010.010.111010050100150200250300Load Current (mA)R e g i o n o f S t a b l e C O U TE S R (Ω)R e g i o n o f S t a b l e C O U T E S R (Ω)RT9054©Copyright 2017 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.For recommended operating conditions specification of the IC, the maximum junction temperature is 125°C. The junction to ambient thermal resistance ( θJA is layout dependent ) for WDFN-8L 1.6x1.6 is 175°C/W on the standard JEDEC 51-3 single-layer thermal test board. The maximum power dissipation at T A = 25°C can be calculated by the following formula :P D(MAX) = ( 125°C − 25°C ) / (175°C/W) = 0.571W for WDFN-6L 1.6x1.6 packagesThe maximum power dissipation depends on the operating ambient temperature for fixed T J(MAX) and thermal resistance θJA . For the IC packages, the Figure 3 of de-rating curves allows the designer to see the effect of rising ambient temperature on the maximum power dissipation.Figure 3. Derating Curve of Maximum Power Dissipation00.10.20.30.40.50.60.70.80.910255075100125Ambient Temperature (°C)P o w e r D i s s i p a t i o n (W )W-Type 6L DFN 1.6x1.6 PackageRichtek Technology Corporation5F, No. 20, Taiyuen Street, Chupei CityHsinchu, Taiwan, R.O.C.Tel: (8863)5526789Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.DS9054-04 July 11。
庞力泰(M4)评估板说明书
3) User Manual- Please download user manual on Powertip website. https:///products_2.php?uID=323#userm
4) TFT- 4 in 1 A series is available for both Sitronix OGS and Hycon GG types. Please refer to price list for the models with border and borderless CTP. https:///products_2.php?uID=323#tftd
CPU Memory Display
Interface Power Input
RISC Processor
On Board RAM On Board ROM External Storage
Resolution Touch Panel
USB COM Port CAN BUS
Alarm Ethernet
GPIO
RGB TFT
CTP
RTP
RS232
DC 9V
Ethernet
Micro SD
CAN BUS
RS458
STMThe M4 evaluation board is an all-in-one embedded solution with features indicated below.
RTC GPIO DC
Cortex-M4 -- STM32F429IGT6 (180MHz)
8MB SDRAM 16MB SPI Flash 1x Micro SD (under 32G) Up to 1024 RGB x 768 Projected Capacitive Touch 1x USB2.0 Host 1x RS485 or RS232
麦克西姆maxq1004评估板说明书
MAXQ1004 Evaluation KitEvaluates: MAXQ1004General DescriptionThe MAXQ1004 evaluation kit (EV kit) provides a proven platform for conveniently evaluating the capabilities of the MAXQ1004 1-Wire M /SPI™ authentication micro-controller. The EV kit includes the MAXQ1004 EV kit board, which contains an on-board USB-to-JTAG loader/debugger interface using the MAXQ610 microcontroller, off-board connectors for the 1-Wire and SPI communica-tions interfaces, two GPIO-controlled pushbuttons and two LED indicators for application use, and headers providing access to all I/O pins on the MAXQ1004. With the included software and a USB cable connected to a Windows M PC, the EV kit provides a complete, functional system ideal for developing and debugging applica-tions as well as evaluating the overall capabilities of the MAXQ1004 RISC microcontroller.EV Kit ContentsS MAXQ1004 EV Kit Board with 16-Pin TQFN MAXQ1004 InstalledAdditional Documentation/SoftwareThis EV kit must be used with the following documents:• MAXQ1004 IC Data Sheet • MAXQ1004 User’s Guide• MAXQ1004 EV Kit Data Sheet (this document)• MAXQ1004-KIT Quick Start GuideThese documents are included in the MAXQ1004 EV kit software package, along with additional documentation and application notes. Download the latest version of the EV kit software package at /MAXQ1004-KIT .FeaturesS Easily Loads and Debugs Code Using On-Board USB-to-JTAG Interface S JTAG Interface Provides In-Application Debugging Features✧ Step-by-Step Execution Tracing✧ Up to Four Simultaneous Hardware Breakpoints by Code Address✧ Data Memory or Register Content View and Edit S On-Board 3.3V (Powered by USB) and 2.5V (Powered by 1-Wire Bus) Voltage Supplies S Two GPIO-Connected Pushbuttons for Application Use S Two GPIO-Connected LEDs for Application Use S 1-Wire and SPI Connectors for Off-Board UseOrdering Information appears at end of data sheet.Component List1-Wire is a registered trademark of Maxim Integrated Products, Inc.SPI is a trademark of Motorola, Inc.Windows is a registered trademark of Microsoft Corp.DESIGNATION QTYDESCRIPTIONCN11USB Mini-B connectorTE Connectivity 1734035-2 C1110nF, 50V ceramic capacitor (0603)C21 4.7F F, 10V ceramic capacitor (0805)C3, C4, C8, C9, C10, C11, C137100nF, 16V ceramic capacitors (0603)C5110F F, 10V ceramic capacitors (0805)C6, C7, C1231.0F F, 10V ceramic capacitors (0603)DN11Dual fast-switching diode, 200mW 75VDiodes Inc. MMBD4448DW-7-F DS1, DS22Surface-mount, 660nm red LEDs (1206)Lumex SML-LX1206SRC-TR D11 5.6V Zener diode, 200mWON Semiconductor MM5Z5V6ST1G JH1, JH2, JH4, JH5, P3, P462x1 header pins, 0.100in spaced Sullins PEC02SAANJH311x3 header pins, 0.100in spaced Sullins PEC03SAANJ11Right-angle PCB mount RJ11 jack Molex 95009-2447P1, P222x5 header pins, 0.100in spaced Sullins PEC05DAANComponent List (continued)Figure 1. MAXQ1004 EV Kit Board +Denotes a lead(Pb)-free/RoHS-compliant package.T = Tape and reel.*EP = Exposed pad.DESIGNATION QTYDESCRIPTIONP511x6 header pins, 0.100in spaced Sullins PEC06SAAN Q11SOT23 n-channel MOSFET Fairchild FDV301NR1110I Q 1%, 1/10W SMD resistor (0603)R2, R3, R12,R134475k I Q 1%, 1/10W SMD resistors (0603)R4, R8210k I Q 1%, 1/10W SMD resistors (0603)R5, R6, R7, R9, R10, R116182I Q 1%, 1/10W SMD resistors (0603)SW1, SW2, SW33SPST normally-open pushbutton switchesOmron B3FS-1000PDESIGNATION QTY DESCRIPTIONTP1–TP55Test pointsU11USB-to-serial translation IC FTDI FT232RL 28-SSOPU212.5V LDO regulatorMaxim MAX1726EUK25+T (5 SOT23)U311-Wire and SPI authentication microcontrollerMaxim MAXQ1004-B01+ (16 TQFN-EP*)U4116-bit microcontroller (used for JTAG interface)Maxim MAXQ610B-0000+ (40 TQFN-EP*)—1PCB: MAXQ1004 Evaluation KitDetailed Description of HardwarePower Supply The EV board should normally be powered by connect-ing a standard USB interface cable (A-to-mini-B) from connector CN1 on the EV board to a PC. This allows the board to draw power directly over the +5V supply on the USB port. The built-in +3.3V linear regulator on the FT232RL IC (U1) is normally used to generate the V DD power rail used by the MAXQ1004 and the MAXQ610.If the MAXQ1004 kit is “free-running,” that is, the user is running an application that has been previously loaded on the MAXQ1004, and does not need to use the loader or debugger, it is not necessary to connect the USB cable. In this configuration, the EV kit can be powered by connecting a regulated DC bench supply to pin JH3.2 (MAXQ1004 VDD/AVDD). Refer to the MAXQ1004 IC data sheet for allowable power-supply range values.GPIO Pushbuttons and Indicator LEDs The two pushbuttons on the bottom side of the EV kit (SW2 and SW3) are connected to the MAXQ1004 GPIO pins P0.1 (SW3) and P0.0 (SW2). If the pushbutton is pressed, it pulls the attached port pin low. The label indi-cating which port pin is connected to the switch is found on the board below the switch.If jumper JH4 is closed, the GPIO pin P0.2 can be used to drive LED DS1. If P0.2 is driven low, then LED DS1 lights; otherwise, it is dark.If jumper JH5 is closed, the GPIO pin P0.3 can be used to drive LED DS2. If P0.3 is driven low, then LED DS2 lights; otherwise, it is dark.Figure 2. MAXQ1004 EV Kit Board Functional LayoutMAXQ610 and the JTAG Loader/Debug Interface The MAXQ610 microcontroller (U4) is preloaded with interface firmware that provides a link between the JTAG loader/debug interface on the MAXQ1004 and the serial port output from the FTDI USB-to-serial bridge IC. This firmware handles commands that are transmitted by application development and debugging software running on the PC, such as MTK, MAX-IDE, or IAR M Embedded Workbench environment.Under normal circumstances, the firmware in the MAXQ610 should not be altered. If it is necessary to update or change the JTAG loader/debug firmware, the standard MAXQ JTAG loader tools (such as MTK) can be used to do so, using any of the available MAXQ JTAG interface boards and the P2 JTAG connector.FTDI USB-to-Serial Bridge The FTDI USB-to-serial interface IC (U1, FT232RL) pro-vides an interface between a virtual COM port running on the PC and the MAXQ610 over a USB-to-serial link. Refer to the MAXQ1004-KIT Quick Start Guide for details on installing and configuring the FTDI drivers required for this interface to operate correctly. The FT232RL also provides the +3.3V regulated supply (used by all devices on the EV kit) and a direct 12MHz digital clock (used by the MAXQ610 only).Reset Pushbutton Pushbutton SW1 can be used to manually reset the MAXQ1004. Normally, this should only be done when the part is free-running, that is, when the loader/debug interface is not in use, or when the part is running with a breakpoint set in the debugger (not during step-by-step tracing mode). Triggering a manual reset when code is being loaded to the part or during active debugging mode can cause the development environment to lose communications with the part, which means that the proj-ect session may have to be restarted and the application reloaded in order to continue.1-Wire Interface and Power Over 1-Wire The EV kit can optionally be configured to operate using a “parasite power” supply mode, where all power to operate the MAXQ1004 is drawn from the 1-Wire signal line. Using this supply scheme, power is “captured” from the 1-Wire line during high signal periods using diode DN1, and energy is stored in capacitor C4. This supply voltage (which is at the 1-Wire line voltage) is regulated down to +2.5V by linear regulator U2.To configure the MAXQ1004 to run using this power sup-ply, set JH3 to pins 2+3 (VDD+V25). However, this only powers the MAXQ1004. The MAXQ610 (and the accom-panying FTDI device) does not operate from this supply, which means that the application code must already be loaded into the MAXQ1004 (the MAXQ1004 must be free-running).There are additional considerations when using this type of power supply. If a standard 1-Wire pullup is being used, the energy stored in the parasite power capacitor can only power the MAXQ1004 for a brief time. The length of time that the MAXQ1004 can run before exhausting the parasite power supply varies depending on the operating frequency and activity of the MAXQ1004, as well as the resistance of the pullup on the 1-Wire line.For a more detailed discussion of this topic, refer to Application Note 4255: How to Power the Extended Features of 1-Wire® Devices.IAR Embedded Workbench is a registered trademark of IAR Systems AB.Jumper Function ListTable 1 details the functions of the EV kit's configurablejumpers. Settings marked with “✓” indicate jumper place-ments that should be used for most normal operation(default settings).Table 1. Configurable Jumper Setting FunctionsJUMPER SETTING EFFECTJH1OpenNo supply is connected to the V DD pin on the MAXQ1004. This setting should notnormally be used.✓ ClosedThe VDD on-board supply (normally +3.3V) is connected to the V DD pin on theMAXQ1004.JH2OpenNo supply is connected to the AVDD pin on the MAXQ1004. This setting should notnormally be used.✓ ClosedThe VDD on-board supply (normally +3.3V) is connected to the AVDD pin on theMAXQ1004.JH3OpenNo power supply source is connected to the VDD on-board supply. If this setting is used,an appropriate DC bench supply should be connected to pin JH3.2 (VDD) and GND.✓ Closed(1+2, MVDD+VDD)The VDD on-board supply is powered by the +3.3V regulated output from the FT232RLIC (which is also the MVDD supply used by the MAXQ610).Closed(2+3, VDD+V25)This setting should not normally be used, unless the parasite power option is required.This setting leaves the MAXQ610 and the FT232RL unpowered.JH4Open LED DS1 is disabled.✓ Closed LED DS1 can be lit by driving GPIO pin P0.2 low.JH5Open LED DS2 is disabled.✓ Closed LED DS2 can be lit by driving GPIO pin P0.3 lowP3N/A Not a configuration jumper. Pin P3.1 provides access to the 1-Wire data line on the MAXQ1004.P4N/A Not a configuration jumper. Pin P4.2 provides access to the AN0 pin (ADC input) on the MAXQ1004.Figure 3. MAXQ1004 EV Kit SchematicOrdering InformationPART TYPEMAXQ1004-KIT#EV Kit#Denotes a RoHS-compliant device that may include lead(Pb) that is exempt unde the RoHS requirements.Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time.Revision HistoryREVISION NUMBERREVISION DATE DESCRIPTIONPAGES CHANGED6/11Initial release—。
ON Semiconductor NB4N855S评估板用户手册说明书
NB4N855SMEVB Evaluation Board User's Manual for NB4N855SDescriptionON Semiconductor has developed an evaluation board for the NB4N855S device as a convenience for the customers interested in performing their own device engineering assessment. This board provides a high bandwidth 50W controlled impedance environment. The pictures in Figure 1show the top and bottom view of the evaluation board, which can be configured in several different ways.This NB4N855S evaluation board manual contains:•Appropriate Lab Setup •Assembly Instructions •Bill of MaterialsThis manual should be used in conjunction with the NB4N855S device data sheet, which contains full technical details on the device specifications and operation.Board Lay −UpThe NB4N855S evaluation board is implemented in four layers with split (dual) power supplies (Figure 6, Evaluation Board Lay −up). For standard lab setup, a split (dual) power supply is essential to enable the 50 W internal impedance in the oscilloscope as a devices termination. The first layer or primary trace layer is 0.005″ thick Rogers RO4003 material,which is designed to have equal electrical length on all signal traces from the device under the test (DUT) to the sense output. The second layer is the 1.0 oz copper ground plane.The FR4 dielectric material is placed between second and third layer and between third and fourth layer. The third layer is also 1.0 oz copper ground plane. The fourth layer is the secondary trace layer.Top View Bottom ViewFigure 1. Top and Bottom View of the NB4N855S Evaluation BoardEVAL BOARD USER’S MANUALFigure 2. Evaluation Board Lay −upConnecting Power and Ground PlanesThe side launch 9 pin power supply connector is wired as shown in Figure 3. Test points can be soldered on the top ofthe PCB to accommodated easier connections. Exact values that need to be applied can be found in Table 1.Table 1. Power Supply LevelsPower Supply SpanV CC (Pin 10)V EE / GND (Pin 5)DUT_GND(PCB SMA Ground))3.0 V1.75 V −1.25 V 0 V 3.3 V2.05 V −1.25 V0 V 3.6 V2.35 V−1.25 V0 VEE Figure 3. Power Supply Connector − 9 Pin SideView (Left) and PCB Top View (Right)V EE Stimulus (Generator) TerminationAll ECL outputs need to be terminated to V TT (V TT = V CC –2.0 V = GND) via a 50 W resistor. The current board design utilizes the space for placement of the external termination resistors. (More information on termination is provided in AN8020). The 0402 chip resistor pads are provided on the bottom side of the evaluation board. Solder the chip resistors to the bottom side of the board between the appropriate input of the device pin pads and the ground pads as shown in Figure 4 (for split power supply setup, PCB is assembled in this configuration).Figure 4. Expanded Bottom ViewLikewise for CML outputs, CML stimulus signal need to be terminated to V CC via a 50 W resistor. To accomplish this configuration the external termination resistor has to be moved from DUT_GND ring to V CC ring on the bottom of the board.For the LVDS configuration Input pin pads of the D0 or D1 input has to be shorted using 100 W resistor across differential lines.DUT TerminationFor standard lab setup and test, a split (dual) power supply is required enabling the 50 W internal impedance in the oscilloscope to be used as a termination of the signals (in split power supply setup DUT_GND is the system ground, V CC is varied, and V EE is –1.25 V; see Table 1, Power Supply Levels).Board Components ConfigurationThe NB4N855SMEVB evaluation board requires eight side SMA connectors. Placement locations are described in the Table 2 below.Table 2. SMA Connectors and Jumpers PlacementDevice J1/D0J2/D0b J3/D1J4/D1b J5J6/Q1b J7/Q1J8/Q0J9/Q0b J10 Pin #12345678910 Connector Yes Yes Yes Yes No Yes Yes Yes Yes NoResistor (bottom)040250 W040250 W040250 W040250 W04020.01m FNo No No No04020.01m FWire No No No No to V EE/GND No No No No to V CCPIN 1Figure 5. Lab SetupD0D0D1D1Q0Q0Q1Q11.Connect appropriate power supplies to V CC , V EE /GND and DUT_GND (See Table 1)2.Connect a signal generator to the input SMA connectors via matched cables. Setup input signal according to the device data sheet.3.Connect a test measurement device on the device output SMA connectors via matched cables.NOTE: The test measurement device must contain 50 W termination.Figure 6. Evaluation Board SchematicQ0Q0Q1Q1D0D0D1D1Table 3. Bill of MaterialsComponents Manufacturer Description Part Number Qty.Web SiteSMA Connector Johnson*SMA Connector − SideLaunch142−0701−85189 Pin D−Sub Receptacle Amphenol Connector, Female,9−Pin, Right Angle788796−11Surface Mount Test Points{Keystone*SMT Miniature TestPoint50153SMT Compact TestPoint5016Chip CapacitorAVCCorporation*0402 0.01 m F " 10%04025C103KAT2A410 m F " 10%T491C106K016AS2Chip Resistor Panasonic*0402 50 W" 1%Precision Thick FilmChip ResistorERJ−2RKF49R9X4Evaluation BoardONSemiconductorMicro−10 EvaluationBoardN/A1Device SamplesONSemiconductorMicro−10 PackageDeviceNB4N855SM1*Components are available through most distributors, i.e. , †Surface Mount Test Points can be used for power supply connection in place of power supply cable connector. See Figure 3 for test point placement.PACKAGE DIMENSIONSMicro −10CASE 846B −03ISSUE DDIM MIN MAX MIN MAX INCHESMILLIMETERS A 2.90 3.100.1140.122B 2.90 3.100.1140.122C 0.95 1.100.0370.043D 0.200.300.0080.012G 0.50 BSC 0.020 BSC H 0.050.150.0020.006J 0.100.210.0040.008K 4.75 5.050.1870.199L0.400.700.0160.028NOTES:1.DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.2.CONTROLLING DIMENSION: MILLIMETER.3.DIMENSION “A” DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006)PER SIDE.4.DIMENSION “B” DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION.INTERLEAD FLASH OR PROTRUSIONSHALL NOT EXCEED 0.25 (0.010) PER SIDE.5.846B −01 OBSOLETE. NEW STANDARD 846B −0210X*For additional information on our Pb −Free strategy and solderingdetails, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.SOLDERING FOOTPRINT*ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.PUBLICATION ORDERING INFORMATION。
905中文说明书
手册
8.905.8001CN
Metrohm AG CH-9101 Herisau Switzerland Phone +41 71 353 85 85 Fax +41 71 353 89 01 info@
905 Titrando
连接蓝牙®适配器 ................................................................. 20
3.5 3.5.1 3.5.2 3.5.3 3.5.4 3.5.5
连接传感器 ........................................................................... 21 一般说明 .............................................................................. 21 连接 pH、Redox 或 ISE 电极 ................................................ 21 连接参比电极 ...................................................................... 22 连接极化电极 ...................................................................... 22 连接温度传感器或带集成温度传感器的电极 ..................... 23
2 仪器概览
7
3 安装
9
3.1 3.1.1 3.1.2 3.1.3
设备组装 ................................................................................. 9 包装 ........................................................................................ 9 检查 ........................................................................................ 9 场地 ........................................................................................ 9
9054中文资料
PCI总线接口芯片9054及其应用【摘 要】PCI9054是PLX公司推出的一种PCI主模式桥芯片。
本文主要介绍了它的特性、功能及应用，说明了以PCI9054作为接口芯片，开发PCI总线扩展卡的硬件框架图，最后给出一个简单的实例。
关键词：PCI总线；局部总线；PCI9054一、 引言PCI 总线是英特尔公司推出的一种高性能局部总线，其数据总线为32 位，且可扩展成64 位，最大数据传输速率为128- 256MB/ s，远远大于ISA总线5Mbyte/s的速度，是目前使用广泛的一种总线，可以支持突发传送。
PCI总线与CPU无关，与时钟频率也无关，因此它可以应用于各种平台，支持多处理器和并发工作。
PCI总线协议比较复杂，用户可以根据具体实际需求选择相应的开发方式，一般，PCI总线开发采用两种方式，一是采用CPLD来设计控制接口。
它的最大好处是比较灵活，用户可以根据自己的需要开发出适合于特定功能的芯片，而不必实现PCI的全部功能。
现在有许多生产可编程逻辑器件的厂商，如Xilinx的LogiCore 和Altera的AMPP都提供经过严格测试的PCI接口功能模块，用户只要进行组合设计即可。
由于PCI总线协议复杂，设计PCI控制接口难度较大，对于产品不大又有时限的工程项目来说，成本巨大，不划算。
二是采用通用PCI接口芯片，例如南京沁恒公司的CH365，AMCC 公司的AMCC S5920、AMCC S5933，PLX 公司的PLX9054、PLX9080 等，通过专用芯片可以实现完整的PCI主控模块和目标模块的功能，将复杂的PCI总线接口转换为相对简单的用户接口，用户只要设计转换后的总线接口即可，它能实现PCI 规范所要求的所有硬件接口信号和配置空间寄存器，专用接口芯片具有较低的成本和通用性，能够有效降低接口设计的难度，缩短开发时间，并能获得较好的数据传输性能。
下面将主要介绍PLX公司的PCI9054接口芯片。
MB9054X EVA使用说明
MB9054X EV A 使用说明一．“MB9054X EV A”Demo 板几乎适用于所有FPT-100P-M06 封装的FFMC-16LX 系列微处理器。
此装置分为两部分，主板及串行下载器。
二．开发“MB9054X EV A”Demo 板是为了使用户能对FFMC-16LX 系列单片机各种功能进行测试，并且当自己应用该系列单片机进行硬件及软件方面设计时可用此Demo 板作为参考，使自己开发的产品快速上市。
富士通的仿真器要求目标系统提供Vcc 和Gnd及时钟电路，此外大多数富士通的Flash 微处理器都支持烧写内部Flash 的编程算法。
注意：本Demo 板只适于在实验室环境使用。
三．支持的微处理器系列该Demo 板可以适用于大多数FFMC-16LX 系列微处理器。
因其允许在线或离线编程并且支持高速CAN 总线及RS485接口，故该板是您在开始自己的项目设计时一个很好的选择，下列微处理器系列可适用于本Demo 板：MB90590 系列：MB90V590，MB90F594/A，MB90594/A，MB90591 等；MB90595 系列：MB90V595，MB90F598，MB90598 等；MB90580 系列：MB90V580，MB90F583，MB90583 等；MB90550 系列：MB90V550，MB90F553A，MB90553A 等；MB90540 系列：MB90V540，MB90F543/549 等。
按下列步骤设置Demo 板（勿上电！）1．将随DEMO板附带的五针插头与J1相连，（注意勿插反）为系统提供电源。
红线接+5V，黑线接GND。
2．将串行下载器与PC机的串口相连；用附带的串口线将串行下载器和主DEMO板的J2连接。
3．根据你的MCU 工作模式设置拨码开关SW上的模式管脚1～5，ON 对应0，OFF 对应1，例如，MB90F543 在工作模式时，SW 的3 脚设为ON，1，2，4，5 脚都设置为OFF；而在编程模式时，1，4，5 脚设为ON，2，3 脚都设置为OFF；四．对于异步引导装载软件：富士通公司专用的异步引导装载软件可用于对以上型号的Flash 微处理器进行在线串行编程，该工具软件随Demo 板提供，按照下列步骤设置硬件（勿接电源!）1．插座上放置Flash 微处理器（注意脚1 位置）；2．设置拨码开关SW的管脚2，3为OFF，1，4，5设为ON；3．打开电源；4．开始异步引导装载软件。
PCI9054的详细设计过程及注意要点
做PCI卡无非是这三步：硬件原理图及PCB布板、写驱动程序、写上层应用程序第一步应该算是比较简单。
首先是PCI协议处理芯片的选型。
现在最常用的有两款：即PLX公司的PCI9052和PCI9054。
其区别就是9052不支持DMA传输，而9054支持DMA传输。
如果你的应用对带宽要求较高的话，建议采用9054，这样比较有把握。
如果带宽要求较低而又想缩减成本的话，9052是个不错的选择。
这两种芯片的可参考的设计资料也比较多。
我们的产品对带宽要求其实并不算高，仅为10MB/s 左右，但考虑到PCI传输的效率，谨慎起见，我还是选了9054，这样带宽会有比较多的富裕，就算设计当中驱动的效率打点折扣，也还是够用的。
这里明确一下带宽的问题，如果PCI总线的速率是33MHz的话，那么它的理论传输带宽就是33Mx32b=1.056Gb/s，如果换算成字节的话，那就是1.056Gb/8=132MB/s。
请注意这是理论带宽，实际设计不会达到的，因为一方面是硬件设计的原因，另一方面是驱动设计的效率会多少打点折扣。
所以如果能用9054的DMA方式达到接近100MB/s的带宽的话，已经是相当不错了。
在据我所知的实际应用中，通常却并不需要PCI卡达到如此高的带宽，十几M或者几十M就足够用了，所以选用9054还是有较多富余的，设计风险比较小。
芯片选定后，就要开始原理图的设计了，其实9054这端的原理图做起来比较简单，无非是一些引脚上拉下拉的问题。
其中要注意的地方主要有这几个：1．TEST引脚要下拉，这是正常操作模式。
如果上拉则是进入芯片测试模式。
2．PCI金手指处的PRSNT1#和PRSNT2#引脚一定至少要有一个下拉，或者两个都下拉（具体可参照PCI协议V2.3），否则找不到卡。
3．模式选择引脚MODE0和MODE1如果都下拉，是C模式，即LOCAL端的地址线和数据线是分开的；如果MODE0上拉，MODE1下拉，则是J模式，即LOCAL端的地址线和数据线复用。
LM49250 评估板用户指南说明书
User's GuideSNAA048A–March2010–Revised May2013AN-1680LM49250Evaluation Board1IntroductionThe LM49250evaluation board is a fully-integrated audio subsystem designed for stereo cell phoneapplications.The LM49250combines2.5W stereo Class D speaker drivers with stereo ground referenced headphone drivers,a class AB earpiece driver,TI3D enhancement,volume control and input mixer into a single device.The filterless class D amplifiers deliver1.19W/channel into an8Ωload with<1%THD+N from a5V supply.The LM49250features a new circuit technology that utilizes a charge pump to generate a negative supply voltage.This allows the outputs to be biased about ground,thereby eliminating output-coupling capacitors typically used with normal single-ended loads.To supply the required voltage level to the groundreferenced amplifier,an LDO has been integrated.For improved noise immunity,the LM49250features fully differential left,right and mono inputs.The three inputs can be mixed/multiplexed to either theloudspeaker,headphone or earpiece amplifiers.The left and right differential inputs can be used asseparate single-ended inputs,mixing multiple stereo audio sources.The mixer,volume control,and device mode select are controlled through an I2C compatible interface.Output short circuit and thermal overload protection prevent the device from being damaged during fault conditions.Superior click and pop suppression eliminates audible transients on power-up/down and during shutdown.The LM49250evaluation board(shown in Figure1)allows the user to easily evaluate the performance and characteristics of the LM49250device.It provides connectors for audio inputs,audio outputs,I2Ccontrol,power supply,and shutdown control.2Quick StartThe following procedures are needed to begin the1.Connect a shunt across the center pin(I2C VDD)and the VDD pin of J9(I2CVDD=VDD).2.Connect a shunt across the center RESET pin and the“+”terminal of J4(I2C reset pin).3.Connect a4Ωor8Ωspeaker across the“+”and“-”pins of J2(left loudspeaker output)and J3(rightloudspeaker output).4.Connect stereo headphones to the headphone jack(U2).5.Connect a16Ωor32Ωspeaker across the“+”and“-”pins of J1(earpiece output).6.Connect a3.6V power supply to the VDD pin of J8,and the power supply ground source to the GNDpin of J8.7.Apply a positive audio signal source to the“+”terminals of J5(right input),J6(left input),and J7(monoinput),and a negative audio signal source to the“-”terminals of J5(right input),J6(left input),and J7(mono input).8.Connect the USB interface card to a PC with the USB cable.Connect cable attached to USB interfacecard to the I2C interface jumper(J10)on demo board.9.Open LM49250I2C interface software.10.Turn on the power supply and audio source.11.In the LM49250I2C interface software(see Figure2)select:•“ON”for Earpiece,Left Loudspeaker,Right Loudspeaker,Left Headphone,and Right Headphone•Mode“2”for Loudspeaker Output Mode,Headphone Output Mode,and Earpiece Output ModeAll trademarks are the property of their respective owners.1 SNAA048A–March2010–Revised May2013AN-1680LM49250Evaluation Board Submit Documentation FeedbackCopyright©2010–2013,Texas Instruments IncorporatedQuick Start 12.Select Chip Power to“ON”to enable the device.13.Adjust the Left,Right,and Mono Volume Control to obtain the desired output level.Table1.Operating Conditions•Temperature Range–40°C≤T A≤+85°C•Supply Voltage(V DD=V DD(LS)=V DD(CP))2.7V≤V DD≤5.5V•I2C Supply Voltage 1.7V≤I2CV DD≤5.5VI2CV DD≤V DDFigure1.Evaluation Board SchematicTable2.Board ConnectorsDesignator Label FunctionJ1EP Mono BTL earpiece audio outputJ2LS_L Left loudspeaker class D audio outputJ3LS_R Right loudspeaker class D audio outputJ4RESET I2C Reset Pin-For normal operation short the center RESET pin to the“+”pin.To reset the PWR_ON bit in the shutdown control register short the centerRESET pin to the“-”terminal.J5IN_R Right,single ended or differential,audio input terminal2AN-1680LM49250Evaluation Board SNAA048A–March2010–Revised May2013Submit Documentation FeedbackCopyright©2010–2013,Texas Instruments Incorporated I2C Software InterfaceTable2.Board Connectors(continued)Designator Label FunctionJ6IN_L Left,single ended or differential,audio input terminalJ7IN_M Mono differential audio input terminalJ8V DD GND Power Supply ConnectionIf a separate I2C power supply voltage is used:Connect the positive voltagesource to the center I2CV DD terminal and the ground source to the pin on J9 J9I2CV DDlabeled GND.If a separate I2C power supply is not used:Connect the centerI2CV DD to the pin on J9labeled V DD.I2C signal terminals.Pin1is for the SCL signal,pin2is for the ADR signal,pin J103is for the SDA signal,pin4is for I2C V DD,and pin5is ground(as labeled onthe evaluation board).J11HP_R Right ground referenced headphone output terminalJ12HP_L Left ground referenced headphone output terminalTable3.Evaluation Board Bill of MaterialsDesignator Part Description Manufacturer Part NumberC1–C6Ceramic capacitor1μF16V X7R120610%muRata GRM319R71C105KC11D C7,C13,C14,C15Ceramic capacitor2.2μF16V X5R0805muRata GRM21BR61C225KA88L C8,C9,C10Ceramic capacitor2.2μF16V X5R0805muRata GRM21BR61C225KA88LC11,C12Ceramic capacitor68nF16V X7R0805muRata GRM188R71C683KA01D C16Ceramic capacitor1μF16V X7R0805muRata GRM21BR71C105KA01LR1,R2Resistor0W1/8W5%0805SMD3I2C Software InterfaceThe LM49250evaluation board is controlled through an I2C compatible USB interface.The LM49250I2C interface software provides a user friendly interface to easily evaluate the functionality of the device.Each button corresponds to bits in an I2C command byte.For detailed I2C information,see the LM49250data sheet.Figure2.LM49250I2C Software Interface3 SNAA048A–March2010–Revised May2013AN-1680LM49250Evaluation Board Submit Documentation FeedbackCopyright©2010–2013,Texas Instruments IncorporatedDefault 4DefaultThe DEFAULT button sets the LM49250and the interface software to its default state.In the default state all output amplifiers,spread spectrum,and3D controls are off,all output modes are set to0,the fullydifferential input mode is selected,all input gains are set to-64dB,right and left loudspeaker output gain is 6dB,and headphone and earpiece output gain are set to0dB.Each time the power supply to the device is cycled,the interface must be reset to its default state.5Chip PowerThe Chip Power button enables or disables the entire device.Even if an individual amplifier channel is enabled,the device will not output any audio if the Chip Power button is set to“OFF”.6LDOHThe LDOH button enables and disables the internal LDO.The LDO is used to drive the ground referenced headphone amplifiers.This allows the speaker and headphone amplifiers to operate from separate power supplies.The separate power supplies allow the speaker amplifiers to operate from a higher voltage for maximum headroom,while the headphone amplifiers operate from a lower voltage,improving powerdissipation.If the LDO and the Chip Power is enabled,2.25V will be seen at the VO(LDO)pin.However,if the LDO is disabled but either headphone output is enabled,2.25V will be seen at the VO(LDO)pin(see Table3).Table4.LDO Disabling OptionsLDOH HPR_ON/HPL_ON PWR_ON V O(LDO)(V)00X0011 2.251X0VDD110 2.250107Spread SpectrumThe LM49250features a filterless spread spectrum modulation scheme.The switching frequency varies which reduces the wideband spectral content.This improves EMI emissions radiated by the speaker and associated cables and traces.The spread spectrum function can be turned on and off through the“SS”section of the interface software.8Input Audio Signal SelectionThe LM49250has a single mono differential input and left and right stereo inputs that can be configured for both single-ended and differential audio signals.The stereo input configurations can be set in the“STEREO INPUT CONFIGURATION”portion of the software interface.•Select“FULLY DIFFERENTIAL INPUT MODE”to configure the left and right inputs for differential operation.•Select“L2and R2SINGLE-ENDED STEREO PAIR”to configure the device to accept single ended audio inputs connected to L2and R2.•Select“L1and R1SINGLE-ENDED STEREO PAIR”to configure the device to accept single ended audio inputs connected to L1and R2.•Select“(L1mix L2)and(R1mix R2)SINGLE ENDED STEREO PAIR”to configure the device to accept two single ended stereo sources,connected to both input pairs.4AN-1680LM49250Evaluation Board SNAA048A–March2010–Revised May2013Submit Documentation FeedbackCopyright©2010–2013,Texas Instruments Incorporated Volume Control and Gain Setting 9Volume Control and Gain SettingEach channel of the LM49250has two separate gain stages.Each input stage(mono,left and right)features a32step volume control that can be configured through the“INPUT VOLUME CONTROL”section of the interface software.The output gain settings can be set under the“Output Gain Settings”tab in the interface software.The loudspeaker output gain for the left and right channels are setindependently,while the headphone gain is the same for both left and right channels.The earpiece output stage has two gain settings,0dB and6dB.Each loud speaker output stage has two gain settings,6dB and12dB.The headphone output stage has8gain settings,0dB,-1.2dB,-2.5dB,-4dB, -6dB,-8.5dB,-12dB and-18dB.In single-ended input mode with only one stereo signal applied,theloudspeaker and headphone output stage gain settings are increased by6dB.The total gain for a given signal path can be calculated by adding the input volume control gain to the output gain setting.10Demonstration Board LayoutFigure3.Top Silkscreen5 SNAA048A–March2010–Revised May2013AN-1680LM49250Evaluation Board Submit Documentation FeedbackCopyright©2010–2013,Texas Instruments IncorporatedDemonstration Board Layout Figure4.Top Layeryer26AN-1680LM49250Evaluation Board SNAA048A–March2010–Revised May2013Submit Documentation FeedbackCopyright©2010–2013,Texas Instruments Incorporated Revision Historyyer3Figure7.Bottom Layer11Revision HistoryRev Date Description1.003/09/10Initial WEB released.7 SNAA048A–March2010–Revised May2013AN-1680LM49250Evaluation Board Submit Documentation FeedbackCopyright©2010–2013,Texas Instruments IncorporatedRevision History 8AN-1680LM49250Evaluation Board SNAA048A–March2010–Revised May2013Submit Documentation FeedbackCopyright©2010–2013,Texas Instruments IncorporatedIMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries(TI)reserve the right to make corrections,enhancements,improvements and other changes to its semiconductor products and services per JESD46,latest issue,and to discontinue any product or service per JESD48,latest issue.Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.All semiconductor products(also referred to herein as“components”)are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.TI warrants performance of its components to the specifications applicable at the time of sale,in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products.Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty.Except where mandated by applicable law,testing of all parameters of each component is not necessarily performed.TI assumes no liability for applications assistance or the design of Buyers’products.Buyers are responsible for their products and applications using TI components.To minimize the risks associated with Buyers’products and applications,Buyers should provide adequate design and operating safeguards.TI does not warrant or represent that any license,either express or implied,is granted under any patent right,copyright,mask work right,or other intellectual property right relating to any combination,machine,or process in which TI components or services are rmation published by TI regarding third-party products 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TI is not responsible or liable for any such statements.Buyer acknowledges and agrees that it is solely responsible for compliance with all legal,regulatory and safety-related requirements concerning its products,and any use of TI components in its applications,notwithstanding any applications-related information or support that may be provided by TI.Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures,monitor failures and their consequences,lessen the likelihood of failures that might cause harm and take appropriate remedial actions.Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in safety-critical applications.In some cases,TI components may be promoted specifically to facilitate safety-related applications.With such components,TI’s goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements.Nonetheless,such components are subject to these terms.No TI components are authorized for use in FDA Class III(or similar life-critical medical equipment)unless authorized officers of the parties have executed a special agreement specifically governing such use.Only those TI components which TI has specifically designated as military grade or“enhanced plastic”are designed and intended for use in military/aerospace applications or environments.Buyer acknowledges and agrees that any military or aerospace use of TI components which have not been so designated is solely at the Buyer's risk,and that Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use.TI has specifically designated certain components as meeting ISO/TS16949requirements,mainly for automotive use.In any case of use of non-designated products,TI will not be responsible for any failure to meet ISO/TS16949.Products ApplicationsAudio /audio Automotive and Transportation /automotiveAmplifiers Communications and Telecom /communicationsData Converters Computers and Peripherals /computersDLP®Products Consumer Electronics /consumer-appsDSP Energy and Lighting /energyClocks and Timers /clocks Industrial /industrialInterface Medical /medicalLogic Security /securityPower Mgmt Space,Avionics and Defense /space-avionics-defense Microcontrollers Video and Imaging /videoRFID OMAP Applications Processors /omap TI E2E Community Wireless Connectivity /wirelessconnectivityMailing Address:Texas Instruments,Post Office Box655303,Dallas,Texas75265Copyright©2013,Texas Instruments Incorporated。
PCI9054详细资料
本文介绍近期工程用到了CPCI，便上网搜集了一下PCI的资料，CPCI是PCI的子集，所用桥接芯片分主从两种，在此不赘述了。
至于PCI，本人整理介绍如下：随着Windows图形用户界面的迅速发展，以及多媒体技术的广泛应用，要求系统具有高速图形处理和I/O吞吐能力，这使原有的ISA、EISA总线远远不能适应而成为整个系统的主要瓶颈。
为此，1991年下半年，Intel公司首先提出PCI概念，并联合IBM、Compaq、AST、HP Apple、NCR、DEC 等100多家公司共谋计算机总线发展大业，成立了PCI集团。
PCI：Peripheral Component Interconnect，外围设备互联总线，是一种局部总线，已成为局部总线的新标准，广泛用于当前高档微机、工作站，以及便携式微机。
主要用于连接显示卡、网卡、声卡。
PCI总线是32位同步复用总线。
其地址和数据线引脚是AD31～AD0。
PCI的工作频率为33MHz。
一PCI总线特性1.PCI总线特点(1)传输速率高最大数据传输率为132MB/s，当数据宽度升级到64位，数据传输率可达264MB/s。
这是其他总线难以比拟的。
它大大缓解了数据I/O瓶颈，使高性能CPU的功能得以充分发挥，适应高速设备数据传输的需要。
(2)多总线共存采用PCI总线可在一个系统中让多种总线共存，容纳不同速度的设备一起工作。
通过HOST-PCI桥接组件芯片，使CPU总线和PCI总线桥接；通过PCI-ISA/EISA 桥接组件芯片，将PCI总线与ISA/EISA总线桥接，构成一个分层次的多总线系统。
高速设备从ISA/EISA总线卸下来，移到PCI总线上，低速设备仍可挂在ISA/EISA总线上，继承原有资源，扩大了系统的兼容性。
(3)独立于CPU PCI总线不依附于某一具体处理器，即PCI总线支持多种处理器及将来发展的新处理器，在更改处理器品种时，更换相应的桥接组件即可。
(4)自动识别与配置外设用户使用方便。
PCI9054卡的安装与使用
PCI9054卡的安装与使用请先安装PCI9054卡，然后完成演示程序说明中的1–10项的测试，如果通过，说明PCI卡设备是完好的。
请尽快在淘宝网上确认。
接下来就可以进行PCI学习与开发了。
1、先将PCI9054卡与实验板连好，（一根是16芯扁平线，一根是26芯扁平线，一根是34芯扁平线。
两块卡上的J1、J2、J3对应相连接，注意方向）；然后进行跳线设置：（1）PCI9054卡：SW1：模式选择。
M0（Mode0）、M1(Mode1)往上拔，（拉低=’0’，C 模式）；J4：BIGEND#引脚电平选择。
默认拉高（请参看原理图）。
短路口不需要连接（默认），如需要拉低时，2、3短接。
C、J模式下可作为Big Endian/Little Endian选择，也可通过设置寄存器位的值（0或1）来配置；M模式下作为WAIT#引脚使用。
J5：LA[29]（C mode）或LA[2]（M mode）时，拉高，即2、3短接；ALE（J mode）时，拉低，即1、2短接。
（2）实验卡：S1：往上拔到‘0’。
模式及总线宽度选择。
本卡只用到总线宽度选择。
S1_2=‘0’为8位总线；S1_2=‘1’为16位总线；J7：1、2短接时，USER0引脚连接LED；2、3短接时，USER0引脚与LED断开；当USER0作为IO口输出时，将1、2短接，可观察到LED闪烁。
J8：1、2短接时，LRESET#引脚连接LED；2、3短接时，LRESET#引脚与LED断开；当1、2短接时，复位时，可观察到LED点亮。
X1：可安装晶振。
当实验卡与PCI9054卡相连时，时钟信号由PCI9054卡提供。
不需安装晶振。
当实验卡不与PCI9054卡相连时，可作为FPGA开发板，此时需要安装晶振。
晶振频率自定。
2、将电脑机箱平放（确保PCI9054卡能垂直插入插槽），打开电脑机箱，将PCI9054卡插入PCI插槽中，（最好选择第一、或第二插槽）。
将实验板放在一个合适的位置。
ESDPS用户手册
工程测量数据处理系统用户手册
5-1 道路测设功能及适用范围............................................................................. 43 5-2 作业流程......................................................................................................... 43 5-3 道路测设数据录入方法................................................................................. 44 5-4 道路测设报表成果输出................................................................................. 48 5-5 道路测设图形成果输出................................................................................. 50 5-6 关于路线测量断链......................................................................................... 51 第六章 公路设计...................................................................................................................53 6-1 路基超高及加宽计算.............................
MSM9059使用手册MSM9059_UserManual(TC)
內容1.前言 (3)2. MSM9059外觀圖 (3)3. ISP簡介 (4)4.使用ISP功能之Configuration設定 (5)5.進入ISP機制說明 (6)5.1硬體ISP (6)5.2軟體ISP (6)6. ICP簡介 (8)7.ICP與ISP差異比較表 (9)8.安裝Prolific USB驅動程式 (10)9. SMAP設定說明 (11)10.1設定燒錄器 (11)10.2自動更新韌體 (12)10.3手動更新韌體 (13)10. SMAP操作介面簡介 (15)10.1燒錄模式 (15)10.2連接COM Port (15)10.3選擇燒錄檔案 (15)10.4晶片組態 (16)10.4.1晶片組態介面 (16)10.4.2讀取組態 (16)10.4.3組態選單 (17)10.5燒錄選單 (18)10.6訊息視窗 (18)10.7緩存區 (18)11. ISP燒錄教學 (20)11.1硬體連接方式 (20)11.2手動燒錄 (21)11.3上電燒錄 (21)11.4自定義下載 (23)USB PlugICP Interface VCC GNDN/AOCI_SCL OCI_SDA ISP InterfaceVCCGNDN/ARxDTxDButtonPOWER(Red LED)GOOD(Green LED)BUSY(Yellow LED)FAIL(Red LED)COM Port使用者程式判斷執行ISP();ISP系統圖新茂提供上圖中Windows應用程式、ISP韌體程式的hex/bin和原始碼供客戶使用，以縮短客戶開發時間。
為方便開發者使用，新茂公司在 SM59R04A2與SM59R02/03/04A1系列IC，出廠前已將ISP韌體程式燒入IC。
4.2依所使用的IC型號載入ISP code，出廠ISP code在程式集中的SMAP路徑找到。
SM59R02A1SM59R03A1SM59R04A1SM59R04A2各IC型號支援硬體ISP機制一覽表5.1.1 “第一個位置的值 $0000=FFH”：當IC為空片時，PC Counter可自行跳躍到ISP code。
UXN14M9PE 评估板用户手册说明书
UXN14M9PE - datasheetSMD-00189 Rev-B N o n C o n f i d e n t i a l February 2016Specifications Subject to Change without Notice© 2016 Microsemi Corporation 1UXN14M9PE Eval BoardUXN14M9PE is an evaluation board for the UXN14M9P DC-14 GHz programmable integer divider.The divide ratio N is given by the following formula:N =∑P k ∗2k 8k=0=P 0+P 1∗2+P 2∗22+P 3∗23+⋯+P 8∗28where P k = 0 (LO) or 1 (HI); valid for N = 8, 9, …, 511DimensionsWith connectors: 2.707” x 2.261” (68.76 mm x 57.43 mm)Without connectors: 2.432” x 1.508” (61.77 mm x 38.30 mm)Microsemi Corporate Headquarters One Enterprise, Aliso Viejo,CA 92656 USAWithin the USA: +1 (800) 713-4113 Outside the USA: +1 (949) 380-6100 Sales: +1 (949) 380-6136Fax: +1 (949) 215-4996E-mail: ***************************© 2016 Microsemi Corporation. All rights reserved. Microsemi and the Microsemi logo are trademarks of Microsemi Corporation. All other trademarks and service marks are the property of their respective owners. Microsemi makes no warranty, representation, or guarantee regarding the information contained herein or the suitability of its products and services for any particular purpose, nor does Microsemi assume any liability whatsoever arising out of the application or use of any product or circuit. The products sold hereunder and any other products sold by Microsemi have been subject to limited testing and should not be used in conjunction with mission-critical equipment or applications. Any performance specifications are believed to be reliable but are not verified, and Buyer must conduct and complete all performance and other testing of the products, alone and together with, or installed in, any end-products. Buyer shall not rely on any data and performance specifications or parameters provided by Microsemi. It is the Buyer’s responsibility to independently determine suitability of any products and to test and verify the same. The information provided by Microsemi hereunder is provided “as is, where is”and with all faults, and the entire risk associated with such information is entirely with the Buyer. Microsemi does not grant, explicitly or implicitly, to any party any patent rights, licenses, or any other IP rights, whether with regard to such information itself or anything described by such information. Information provided in this document is proprietary to Microsemi, and Microsemi reserves the right to make any changes to the information in this document or to any products and services at any time without notice.SMD-00189 Rev-B/2.16 Microsemi Corporation (Nasdaq: MSCC) offers a comprehensive portfolio of semiconductor and system solutions for communications, defense & security, aerospace and industrial markets. Products include high-performance and radiation-hardened analog mixed-signal integrated circuits, FPGAs, SoCs and ASICs; power management products; timing and synchronization devices and precise time solutions, setting the world’s standard for time; voice processing devices; RF solutions; discrete components; security technologies and scalable anti-tamper products; Power-over-Ethernet ICs and midspans; as well as custom design capabilities and services. Microsemi is headquartered in Aliso Viejo, Calif., and has approximately 3,400 employees globally. Learn more at .。
双通道高速运算放大器评估板 用户指南说明书
评估板用户指南UG-082 One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106 • Tel: 781.329.4700 • Fax: 781.461.3113 • 双通道高速运算放大器评估板（16引脚、4 mm×4 mm LFCSP封装，带专用反馈引脚）特性可快速实现试验板试验/原型操作用户自定义电路配置支持边缘安装型SMA连接器可轻松连接至测试设备和其它电路两个独立电路可增强灵活性概述EB-O16CP44-2Z旨在帮助用户评估双通道高速运算放大器。
EB-O16CP44-2Z是裸板（即评估板上未焊接任何器件），用户可以快速完成各种运算放大器电路的原型设计，从而最大程度地降低风险，加快产品上市。
EB-O16CP44-2Z评估板支持ADI公司所有采用16引脚、4 mm×4 mm引脚架构芯片级封装(LFCSP)并带专用反馈引脚的双通道高速运算放大器。
图1和图2分别显示的是评估板的器件侧和电路侧。
图3显示的是评估板原理图。
该4层评估板的输入端和输出端支持边缘安装型SMA连接器，可高效快速连接至测试设备或其它电路。
评估板接地层、器件放置和电源旁路经过优化设计，可以最大程度地提高电路的灵活性和性能。
评估板支持多种SMT元件尺寸：0402、0508、0603和7343。
图4和图6显示的是评估板装配图。
图5和图7显示的是将评估板连接到运算放大器和支持电路的金属布局图。
评估板的器件侧和电路侧图片图1. EB-O16CP44-2Z PCB的器件侧图2. EB-O16CP44-2Z PCB的电路侧UG-082 评估板用户指南目录特性 (1)概述 (1)评估板的器件侧和电路侧图片 (1)修订历史......................................................................................2评估板原理图. (3)装配图和布局图 (4)订购信息 (5)物料清单 (5)修订历史2010年5月—修订版0至修订版A更改图1 (1)增加图2；重新按序编号 (1)增加表1 (5)2010年1月—修订版0：初始版评估板用户指南 UG-082评估板原理图图3.通用评估板原理图UG-082评估板用户指南装配图和布局图图4.评估板器件侧装配图图5.评估板器件侧布局图图6.评估板电路侧装配图图7.评估板电路侧布局图评估板用户指南 UG-082订购信息物料清单表 1数量索引标识符描述封装6 +IN1, +IN2, −IN1, −IN2, OUT1, OUT2 SMA/SMT SMA/SMT6 C1, C2, C3, C4, C15, C16 0.1 μF电容C05082 C17, C18 用户自定义电容C06032 C19, C20 用户自定义电容C04024 C11, C12, C13, C14 10 μF电容C603214 R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14 用户自定义电阻R04024 R17, R18, R19, R20 0 Ω，两个电源短接在一起R06034 R15, R16, R21, R22 1 kΩR06039 PD1/DIS1, PD2/DIS2, GND1 to GND3, +VS1, −VS1, +VS2, −VS2 测试点TP1 P1 3位接头Molex 22-23-20312 W1, W2 3引脚直插接头Molex 22-03-2031 2 JP1, JP2 用户自定义跳线焊接跳线1 U1 放大器SOICUG-082 评估板用户指南注释评估板用户指南 UG-082注释UG-082评估板用户指南ESD警告ESD（静电放电）敏感器件。
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富士通微型电子亚太有限公司FMALMCU-UG-20030001-10用户手册F²MC-16LX FAMILYMB90F54X评估板用户手册版本历史日期 版本 更改内容/备注 更改人2003年5月15日 1.0 1.0 版完成 David目 录版本历史目录1 总论 (1)1.1 概况 (1)1.2 简介 (1)2 板上功能 (2)3 评估板支持的单片机 (2)4 评估板的配置 (2)4.1 基本配置 (2)4.2 CAN控制器配置 (2)4.3 A/D功能的使用配置 (3)5 用Accemic MDE调试评估板 (3)6 接口 (4)6.1电源接口(X1) (4)6.2 引脚排针(J1, J2, J3, J4) (4)6.3 UART通用异步口 (X2, X3) (4)6.4 CAN 接口 (X4, X5) (4)7 物品清单 (5)8 相关网址及联系方式 (6)附录：A. PCB丝印图 (7)B. 电路原理图............................................................ (8)1 总论1.1 概况本手册概括介绍了MB90F54X 评估板。
本板可以用来评估富士通的16LX系列单片机中的MB90F540、MB90F545系列, MB90F443和MB90F598。
1.2 简介MB90F54X 评估板是为了支持开发人员进行低成本和快速开发而设计的。
其特性如下：• 支持Accemic MDE调试环境。
Accemic MDE这是一个低成本的并简单易用的硬件调试环境，由富士通的第三方公司Accemic开发，支持富士通的大多数16位和部分32位单片机。
• 内部集成的CAN控制器。
CAN是一个串行、异步、多主通讯协议，在汽车和工业控制中被广泛应用于电子控制单元之间的通讯。
• 支持Flash的在线烧写。
不需烧写器，可方便进行软件在线升级。
• 支持Flash加密。
有效防止盗版。
注意：本评估板仅可在实验室环境中供测试评估使用！2 功能～直流电源供电• 914V个高速收发器• 2CAN• 2RS232Accemic MDE个接口（其中一个用于）• 2套芯片引脚引出排针• 可选的副晶振• RST HST和的按钮• 8个用户发光二极管• A/D测试功能• 3个数字量输入开关随板提供MB90F543单片机芯片，片内带2个CAN控制器，128K字节的Flash。
如您需要其他系列的单片机或相关工具请联系您附近的富士通单片机支持中心或富士通的代理公司。
3 评估板支持的单片机本评估板支持的单片机有：• MB90F443G• MB90F543G(S)• MB90F546G(S),MB90F547G(S),MB90F548G(L)(S), MB90F549G• MB90F598G4 评估板的设置4.1 基本设置下面以MB90F543为例介绍评估板基本设置步骤：1. 断开电源！2. 把模式管脚（Mode pin）的拨动开关S1拨到“PROG”模式，即sw2是“off”，其他都是“on”，参见pcb板丝印层上的说明。
3. 用附带的串口线把评估板和PC连接起来。
4.2 CAN控制器设置如果使用CAN请做以下步骤：1. 顺时针调整电位器P1，P2到底，通过测量U3和U4的引脚8接地予以确认。
2. 通过设置跳线JP2-JP3选择相应CAN接口。
丝印层上的p inxx即代表单片机的管脚，如是MB90F543就短接pin73，pin74，即短接到如丝印层所示位置，“CAN of 54x 443”。
如单片机是MB90F598就短接pin74，pin75，即短接到“CAN o f 598”。
表1 富士通单片机CAN 控制器引脚注意：MB90F443有3个CAN 控制器，第三个CAN 控制器没有在板上扩展出来，如需使用，可自行扩展。
4.3 A/D 功能的使用设置把S2上的相关开关按丝印层上指示拨到相应位置，即sw1～sw5“on ”。
这样即把 A VCC 和 A VR+ 连到 5V , A VSS 和 A VR- 到 GND ，AN0连到电位器P3。
（sw6～sw8分别连接P61～P63口，可作开关量的输入口）。
5 用Accemic MDE 调试评估板注意：在开始本步骤前请确认你已完成第4部分“评估板的设置”1. 给评估板加电（9~12V ）2. 打开Accemic MDE ，在Perference…System…菜单中选择相应的单片机型号，计算机的串口号。
3. 给单片机复位（JP1默认是连起来的，表示系统的RST 和HST 在电路上相连，详见电路原理图，你可以使用其中的任何一个）4. 单击“Download Monitor”按钮，系统自动完成monitor kernel 的下载和烧写工作。
如不成功请依次检查下面状态： a 系统是否上电，红色LED 灯是否点亮 b 拨动开关S1是否在PROG 状态c 串口电缆是否连好，串口号是否有冲突，例如是否已被其他程序占用 如一切正常，请按RST 键后再重复第4步5. 下载monitor kernel 成功后，请按住RST 按钮，同时按软件提示，拨动S1到“RUN ”状态，如即丝印层S1 Setting for MDE 所示，sw1 off sw2 on sw3 随意 sw4 随意即使：MD0 = High MD2 = Low P00 = don’t care P01 = don’t care注意：MD1已在电路上接为常高。
6. 放掉单片机的RST 按钮，按“Connect ”键进行连接，即可开始调试。
7. 下载例程进行调试。
依次选择菜单File - Load File…，并选择需下载的文件，例如CD 中的文件“…\Sample for EVA\IOPort\Abs \IOPort.abs ”，CAN0 CAN1Target MCURX0 TX0RX1TX1 MB90F443 Pin 74 Pin 73 Pin 76 Pin 75 MB90F543 Pin 74 Pin 73 Pin 76 Pin 75 MB90F548 Pin 74 Pin 73 n.a n.a MB90F549 Pin 74 Pin 73 n.a n.a MB90F598Pin 75 Pin 74 n.a n.a打开，将例程下载到目标单片机中。
8. 按 F9 键即开始运行程序。
要了解Accemic MDE 的详细使用方法，请参阅MDE Manual 。
您同样可在我们附带的光盘中找到。
6 接口6.1 电源接口(X1)下图所示是电源接口X1。
它被用来评估板连接外部直流供电（9V-12V DC ） Connector X1:推荐使用9V 直流电源以使电源消耗达到最小。
否则，集成稳压器7805可能需要额外的散热器。
6.2 引脚排针(J1, J2, J3, J4)评估板上单片机的所有引脚都被直接连到2X25的排针J1, J2, J3 和J4上，分配如下6.3 UART 通用异步口 (X2, X3)两个9针的D-Sub 的雄连接器被用来作为异步通讯接口TXD 是发送，RXD 是接受。
请用1:1的串口线进行和PC 的连接 其中：X2是MDE 占用的串口 X3是通用串口6.4 CAN 接口 (X4, X5)9两个针的D-Sub CAN P1,P2雌接口是接口。
使用时先顺时针调整电位器到U3U48P1P2CAN U3U48底，即使和的第脚都接地。
，是的速率电阻，，的第CAN 82C250脚接地表示速率最大，关于收发器的详细资料可查阅相关资料，PAC82C250光盘中有一篇的应用手册，供参考。
Connector MCU Pins J2, J4 (1 – 50) 1 – 50 J1, J3 (51 – 100) 51 – 1007 清单• MB90F54X评估板，板上安装MB90F543 - 128KB flash 单片机。
• 一对一的9针串口线• 富士通16位单片机开发环境及相关资料光盘一张光盘内容：富士通16位单片机集成开发环境SOFTUNE V3 Professional（带C编译器）评估板用户手册（本手册）与评估板配合使用的C例程Accemic MDE 试用版和相关文档富士通16位单片机Flash烧写软件富士通16位单片机相关资料（Data sheet，Hardware Manual，Application Note等）CAN相关资料如您需要其他系列的单片机或相关工具请联系您附近的富士通单片机支持中心或富士通的代理公司。
8相关网址及联系方式富士通微型电子亚太有限公司/富士通单片机资料大全http://www.fme.gsdc.de/gsdc.htm / Accemic 公司/富士通微型电子亚太有限公司上海代表处上海市延安东路222号外滩中心 3102室邮编：200002电话：021-6335 1560 传真：021-6335 1610Email: David.du@北京代表处北京市建国门外大街1号国贸大厦1座 2701室邮编：100004电话：010-6505 9750 传真：010-6505 9751Email: Leon.wang@深圳代表处深圳市深南东路5002号地王商业中心 4509室邮编：518008电话：0755-8246 1662 传真：0755-8246 1510Email: Norman.yang@- 8 -。