CD4023 CMOS 三3输入与非门

TL F 5956CD4023BM CD4023BC Buffered Triple 3-Input NAND Gate CD4025BM CD4025BC Buffered Triple 3-Input NOR Gate

February 1988

CD4023BM CD4023BC

Buffered Triple 3-Input NAND Gate CD4025BM CD4025BC

Buffered Triple 3-Input NOR Gate

General Description

These triple gates are monolithic complementary MOS (CMOS)integrated circuits constructed with N-and P-chan-nel enhancement mode transistors They have equal source and sink current capabilities and conform to standard B se-ries output drive The devices also have buffered outputs which improve transfer characteristics by providing very high gain All inputs are protected against static discharge with diodes to V DD and V SS

Features

Y Wide supply voltage range 3 0V to 15V Y High noise immunity 0 45V DD (typ )Y

Low power TTL fan out of 2driving 74L compatibility or 1driving 74LS Y 5V–10V–15V parametric ratings Y Symmetrical output characteristics

Y

Maximum input leakage 1m A at 15V over full temperature range

Connection Diagrams

CD4023BM CD4023BC Dual-In-Line Package

TL F 5956–1Top View

CD4025BM CD4025BC Dual-In-Line Package

TL F 5956–2

Top View

Order Number CD4023B or CD4025B

C 1995National Semiconductor Corporation RRD-B30M105 Printed in U S A

Absolute Maximum Ratings (Notes 1 2)

If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications DC Supply Voltage (V DD )b 0 5V DC to a 18V DC Input Voltage (V IN )

b 0 5V DC to V DD a 0 5V DC

Storage Temp Range (T S )b 65 C to a 150 C

Power Dissipation (P D )Dual-In-Line 700mW Small Outline 500mW Lead Temperature (T L )(Soldering 10seconds)

260 C

Recommended Operating Conditions

DC Supply Voltage (V DD )5V DC to 15V DC Input Voltage (V IN )

0V DC to V DD V DC

Operating Temperature Range (T A )CD4023BM CD4025BM b 55 C to a 125 C CD4023BC CD4025BC

b 40 C to a 85 C

DC Electrical Characteristics CD4023BM CD4025BM (Note 2)

Symbol Parameter

Conditions

b 55 C

a 25 C

a 125 C

Units Min Typ Min Typ Max Min Max I DD

Quiescent Device Current V DD e 5V

0 250 0040 257 5m A V DD e 10V 0 50 0050 515m A V DD e 15V 1 00 0061 030m A V OL

Low Level Output Voltage V DD e 5V

0 0500 050 05V V DD e 10V 0 0500 050 05V V DD e 15V 0 05

0 05

0 05

V V OH

High Level Output Voltage V DD e 5V

4 954 9554 95V V DD e 10V 9 959 95109 95V V DD e 15V 14 95

14 951514 95

V

V IL

Low Level Input Voltage

V DD e 5V V O e 4 5V 1 521 51 5V V DD e 10V V O e 9 0V l I O l k 1m A

3 043 03 0V V DD e 15V V O e 13 5V (

4 0

6

4 0

4 0

V V IH

High Level Input Voltage

V DD e 5V V O e 0 5V 3 53 533 5V V DD e 10V V O e 1 0V l

I O l k 1m A

7 07 067 0V V DD e 15V V O e 1 5V

(11 011 0911 0V I OL

Low Level Output Current V DD e 5V V O e 0 4V 0 640 510 880 36mA (Note 3)V DD e 10V V O e 0 5V

1 61 3

2 20 90mA V DD e 15V V O e 1 5V

4 2

3 4

8

2 4

mA I OH

High Level Output Current V DD e 5V V O e 4 6V b 0 64b 0 51b 0 88b 0 36mA (Note 3)V DD e 10V V O e 9 5V

b 1 6b 1 3b 2 2b 0 90mA V DD e 15V V O e 13 5V b 4 2

b 3 4b 8

b 2 4

mA

I IN

Input Current

V DD e 15V V IN e 0V b 0 10

b 10b 5b 0 10

b 1 0

m A

V DD e 15V V IN e 15V

0 10

10b 5

0 101 0

m A

Schematic Diagram

CD4023BC CD4023BM

TL F 5956–3

Device Shown All Inputs Protected

by Standard CMOS Input Protection Circuit

2