Systems In Package 系统级封装

Project Statistics•Design for Manufacture Methodology for SiP –Academic partners : Lancaster University & Greenwich–Industrial partners : NXP, Flowmerics, Coventor& Selex –£206K –Nov 2005 –Nov 2007–Focus : Reliability Engineering of SiP assemblies •Integrated Health Monitoring of MNT Enabled Integrated Systems “I-Health”–Academic partners : Lancaster University & Heriot WattUniversity–Industrial partners : NXP, QinetiQ, Coventor, MCE–Focus : Embedded Test & Health Monitoring of SiP based systemsSiP-Design•Design for Manufacture Methodology for SiP –Realise algorithms and associated code to generate anintegral thermal map across a behavioural model of anSiP structure.–Realise algorithms and associated code to model andcouple electromagnetic and electrostatic fields intofunctional devices and materials within an SiPstructure.–Realise a method of injecting defects and degradationinto structural SiP models. Address the Test Issue.–Demonstrate the above advances in an industrial Virtual Prototype environment“I-Health”project SP/05/01/03•Integrated Health Monitoring of MNT Enabled Integrated Systems–The potential to realise low cost temperature, stress, humidity and EM field sensors for integration in a health monitoring architecture.–Electrical only strategies that requires low performance electronics to monitor non-electrical functions both on-line and in production.– A solution for embedding both sensing and electrical monitoring functions within a SiP level test access and control architecturetogether with decision making functions based on re-use and / orreconfiguration of existing functions and both fault tolerance and self-repair through redundancy and emulation.–Implementation solutions including on-chip, on-substrate and through dedicated low cost health inserts for both silicon and LTCC platforms.University of Greenwich •Centre for Numerical Modelling and Process Analysis– 5 Profs, 20+ Post Docs, 40 + PhD’s–One of largest groups in UK•Electronics and Microsystems– 2 Profs, 3 Post Doc’s, 5 PhD’s–Over £2m of support since 1998 in electronics and microsystems modelling.Device FabricationNitrogenLead-Free Wave SolderingOptical interconnects Thermo-mechanical (alignment)Laser SolderingAccelerated Life Testing Fatigue, etcLancaster University•Centre for Microsystems Engineering–4 academic staff, 5 RA’s, 4 PhD’s–Delivered against £3.4M in grant income over the past 10years–Leads the European Design for Micro & Nano Manufacture community through the FP6 Network of Excellence(PATENT-DfMM)What is System-in-Package, or SiP?•The integration of several Integrated Circuits and components of various technologies (RF, analogue, digital, in Si, in GaAs) in a single package, resulting in one or several electronic systems•Related key words:–Heterogeneous Integration, System-on-Chip, SoPStacked StructuresSide-by-Side Structures EmbeddedStructuresSiP key drivers and benefits•Size reduction•Functional performance improvement •Combination of several functions•Cost reduction•Speed-to-market due to the reuse of existing ICs •Complete system integrationIntegrated Discretes(ESD protection + EMI No redistribution layer (RDL) needed: direct bump on IO.FM radio (2005) RDL needed (higher cost than directStill few product linesActive die d d f hyearMCM + discrete passives on laminate MCM + discretepassives on laminate + Integrated Passive Multi-Chip Modules (MCM)100%silicon -based SiP 199019992004P r o p o r t i o n o f S i Pyear MCM + discrete passives on laminateMCM + discrete passives on laminate + Integrated PassivesMultiChip Modules (MCM)100%Silicon-basedSiP199019992004= leadframe based+ WL-CSPWL-SiP: challenges•Larger WL-CSP modules (because SiP are larger than current WL-CSP parts)–Board Level Reliability(solder fatigue issue)•Larger WL-CSP modules–Board Level Reliability(solder fatigue issue)•Assembly flow–Final Test–Marking–Packing–Storing•Customer acceptance–Customers and assemblers (pick & place, under fill dispensing on PCB)–Designers (sockets for evaluation boards)–PCB makers: downwards CTE curve to be supportedNumber of TMC cycles% u n i t s f a i l i n gImproved Si technologies,lower PCB CTE’sLarger WLP modulesBoard Level Reliability: solder fatigue (1)•Visible by thermal cyclingSimulation and Modelling Requirements•Accurate simulation and modelling is useful–In the short term•To assess reliability of current WL-CSP technologies withrespect to larger sizes•To compare possible technology options–New materials (underfills, bump alloys, PCB’s)–New balling layout rules–In the longer term•To “virtually qualify”WL-CSP parts:–How to make sure a new product has every chance to first timepass qualification stresses according to the company specificGeneral Quality System?One-eight of the SiPBalls (SAC105-Sn)UF2 UF3SiP Parameters:Test Passive die thicknessUF Size Test Passive dieUF SizeInelastic material behaviour of solder (Creep Rate Equation);Different SiP PackagesUF3Stacked Die SiPEmbedded Die SiPP a s s i v e Di eA c t i v e D iePCBA c t i v e D ieP a s s i v e Di eMold CompoundUF3Dielectric2Dielectric1CopperIn ModelMold CompoundFixed Chip Thickness80μmMold Thickness20μmMold Thickness120μmMold Thickness320μmMoldEffect of Mold Compound ThicknessChipMold Compound Properties:CTE:α1=10ppm/ºC, α2=45ppm/ºC(T g =130ºC)Young Modulus = 20.E+9Pa Poisson’s Ratio = 0.35Embedded Die SiP without UnderfillHealth Monitoring – embedded conceptTemperature sensor EMI probeMEMSCarrier substrate Passives: test response read out & stimulus injectionActive: Health monitor central unit- Integrated sensors: temperature, EMI probes etc… - MEMS testing - System reconfigurationHealth Monitor – Insert ConceptLoop antenna Temperature sensor + passive componentsCMOS die MEMSActive dieLow cost plastic insert• Possibility for stacked SiP • Standard pin-out / foot print for test interface? • Dependent on advances in polymer electronicsNon-electrical functions – bias superposition•100 µmElectrical only test & monitoring techniques for MNT systems9 Feasibility on magnetometer, accelerometer, conductance sensorPhysical inputTranducer Interface ElectronicsDSPTransducer outputBiasingElectrical Test signal Test signal filter comparatorOn-line-test outputIs it possible to use this method as a generic method to test MEMS structures?Implementation – embedded accelerometersTest output is unstable under acceleration conditions – on-line applicability??fluctuationDemonstrator board with QinetiQ accelerometerTest output with no accelerationTest output with 10g acceleration @ 100Hz• • •Step 1: Identify the causes of the fluctuation Step 2: Develop solutions to solve the issue of the test output fluctuation Step 3: Evaluate the fault coverage capability using fault simulationSolution – encoding of test stimuli• Encoding the test stimulusModulation of the test sine wave by the codeAccelerationLFSR LFSR LP LP2 2 LP1 HPOperational outputVout VdemLP3 Cov. Cov. Cor. Cor.×El/Acc El/Acc+Sensor × Cov CorGeneration of a pseudo-random bit code sequenceCarrierDemod.VcodeTest outputsNovel architecture • • • • • A pseudo-random code sequence modulates the test sine wave The code is retrieved by demodulation at the output Covariance and correlation algorithms are applied The covariance gives a value related to the sensor sensitivity The correlation gives information on the integrity of the covarianceApplication to RF MEMS switchBridge UP Dielectric DOWNSubstrate ConductorVbias RF choke RF in DC block DC block RF outRaytheon/TI* switch: Cup = 35fF (Insertion loss@10GHz = 0.025 dB) Cdown = 3.5pF (Isolation@10GHz = 15 dB)Cup / CdownSwitch model with the biasing circuitry in a shunt configuration*Raytheon/TI switchTest implementation strategyCtf Vtr Rtf Ract Vact Actuation generator RF in Vin RF switch controller Cp Lch Cbl Vs Cbl Vout Cup / Cdown Health Monitor RF out Vbias Cstim Test generator Vstim Enveloppe detector Test response analyserSwitch with passive componentsPassive components integrated on the substrateConclusions• Work to date focused around silicon based WLSiP– Embedded health monitoring – Strategies for non-electrical functions – Reliability simulation – structure & assembly • Impact of underfill on solder reliability • Impact of moulding process • Impact of fan-out • Analytical reliability prediction strategies developed – Extend to SoP – eg. Ceramic based – Investigate integration into EDA tools。