EDA实验七波形图
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use ieee.std_logic_1164.all;
entity lol is
port(a:in std_logic_vector(3 downto 0); b:in std_logic_vector(2 downto 0);
c:out std_logic_vector(7 downto 0);
led7s:out std_logic_vector(6 downto 0)); end;
architecture one of lol is
begin
process(b)
begin
case b is
when"000"=>c<="00000001"; when"001"=>c<="00000010"; when"010"=>c<="00000100"; when"011"=>c<="00001000"; when"100"=>c<="00010000"; when"101"=>c<="00100000"; when"110"=>c<="01000000"; when"111"=>c<="10000000";
when others=>null;
end case;
end process;
process(a)
begin
case a is
when"0000"=>led7s<="1000000"; when"0001"=>led7s<="1111001"; when"0010"=>led7s<="0100100"; when"0011"=>led7s<="0110000"; when"0100"=>led7s<="0011001"; when"0101"=>led7s<="0010010"; when"0110"=>led7s<="0000010"; when"0111"=>led7s<="1111000"; when"1000"=>led7s<="0000000"; when"1001"=>led7s<="0010000"; when"1010"=>led7s<="0001000"; when"1011"=>led7s<="0000011"; when"1100"=>led7s<="1000110"; when"1101"=>led7s<="0100001"; when"1110"=>led7s<="0000110"; when"1111"=>led7s<="0001110"; when others=>null;
end process; end;