eda实验

实验一
module add8_tp;
reg[7:0] a,b;
reg cin;
wire[7:0] sum;
wire cout;
parameter DELY=100;
add8 u1(sum,cout,a,b,cin);
initial begin
a=8'd0;b=8'd0;cin=1'b0;
#DELY a=8'd100;b=8'd200;cin=1'b1;
#DELY a=8'd200;b=8'd88;
#DELY a=8'd210;b=8'd18;cin=1'b0;
#DELY a=8'd12;b=8'd12;
#DELY a=8'd100;b=8'd154;
#DELY a=8'd255;b=8'd255;cin=1'b1;
#DELY $finish;
end
initial $monitor($time,,,"%d+%d+%b={%b,%d}",a,b,cin,cout,sum); endmodule
module add8(sum,cout,a,b,cin);
input[7:0] a,b;input cin;
output[7:0] sum;output cout;
assign {cout,sum}=a+b+cin;
endmodule
实验二
module qjadd(x,y,z,d,b);
input x,y,z;
output d,b;
assign d=((~x)&(~y)&(z))|((~x)&y&(~z))|(x&(~y)&(~z))|(x&y&z); assign b=((~x)&y)|((~x)&z)|(y&z);
endmodule
`timescale 1ns/1ns
module qjadd_tp;
reg x,y,z;
wire d,b;
parameter DELY=100;
qjadd u1(x,y,z,d,b);
initial begin
x=1'b0; y=1'b0; z=1'b0;
#DELY x=1'b0; y=1'b0; z=1'b1;
#DELY x=1'b1; y=1'b0; z=1'b0;
#DELY x=1'b1; y=1'b0; z=1'b1;
#DELY x=1'b1; y=1'b1; z=1'b0;
#DELY x=1'b1; y=1'b1; z=1'b1;
#DELY x=1'b0; y=1'b1; z=1'b0;
#DELY x=1'b0; y=1'b1; z=1'b1;
#DELY $finish;
end
initial $monitor($time,,,"%b-%b-%b={%b,%b}",x,y,z,d,b); endmodule
实验三
module count4(clk,reset,out);
input clk,reset; output reg[3:0] out;
always @(posedge clk)
begin
if(reset) out<=0;
else if(out<16) out<=out+1;
else out<=0;
end
endmodule
module count4_tp;
reg clk,reset;
wire[3:0] out;
parameter DELY=100;
count4 u1(clk,reset,out);
always #(DEL Y/2) clk=~clk;
initial
begin clk=0;reset=0;
#DELY reset=1;
#DELY reset=0;
#(DELY*20) $finish;
end
initial $monitor($time,,,"clk=%d reset=%d out=%d",clk,reset,out); endmodule
实验五
module acc16(a,reset,clk,c);
input [15:0] a;
input reset,clk;
output reg[15:0] c;
always@(posedge clk or negedge reset)
if(!reset) c=0;
else c=c+a;
Endmodule
`timescale 1ns/1ns
module acc16_tp;
reg[15:0] a;
reg clk,reset;
wire[15:0]c;
parameter DELY=100;
acc16 u1(a,reset,clk,c);
always #(DEL Y/2) clk=~clk;
initial fork clk=0;reset=0;a=1'd1;
#DELY reset=1;
#(DEL Y*10) a=1'd5;
#(DELY*20) $finish;
join
initial $monitor($time,,,"clk=%d reset=%d a=%d c=%d",clk,reset,a,c); endmodule。