3-8译码器(2)

三八译码器的设计与实现

一．实验内容

用FPGA设计一个3-8译码器，采用基本门结构化描述

二.实验原理

3-8译码器的真值表如下所示:

根据这个真值表，我们画出卡诺图，化简之后就得到每个输出对应的组合逻辑，即得到如下的电路图

根据这个电路图我们就可以写出3-8译码器的门电路的实现。

三.实验过程

从上面的电路图我们可以看出需要若干个四输入与非门和三输入的非与门。四输入与非门源程序如下:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity and4not is

Port ( in1 : in STD_LOGIC;

in2 : in STD_LOGIC;

in3 : in STD_LOGIC;

in4 : in STD_LOGIC;

out1 : out STD_LOGIC);

end and4not;

architecture Behavioral of and4not is

signal temp1: STD_LOGIC;

signal temp2: STD_LOGIC;

signal temp3: STD_LOGIC;

begin

temp1 <= in1 and in2;

temp2 <= in3 and in4;

temp3 <= temp1 and temp2;

out1 <= not temp3;

end Behavioral;

三输入的非与门源程序如下:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity and3not is

Port ( in1 : in STD_LOGIC;

in2 : in STD_LOGIC;

in3 : in STD_LOGIC;

out1 : out STD_LOGIC);

end and3not;

architecture Behavioral of and3not is

signal temp1: STD_LOGIC;

begin

temp1 <= in1 and (not in2);

out1 <= temp1 and (not in3);

end Behavioral;

再在顶层模块里把这些器件按原理图连接起来就行了. 源程序如下:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity decoder is

Port ( A : in STD_LOGIC;

B : in STD_LOGIC;

C : in STD_LOGIC;

S1 : in STD_LOGIC;

S2 : in STD_LOGIC;

S3 : in STD_LOGIC;

Y0 : out STD_LOGIC;

Y1 : out STD_LOGIC;

Y2 : out STD_LOGIC;

Y3 : out STD_LOGIC;

Y4 : out STD_LOGIC;

Y5 : out STD_LOGIC;

Y6 : out STD_LOGIC;

Y7 : out STD_LOGIC);

end decoder;

architecture Behavioral of decoder is COMPONENT and4not

Port ( in1 : in STD_LOGIC;

in2 : in STD_LOGIC;

in3 : in STD_LOGIC;

in4 : in STD_LOGIC;

out1 : out STD_LOGIC);

end COMPONENT;

COMPONENT and3not

Port ( in1 : in STD_LOGIC;

in2 : in STD_LOGIC;

in3 : in STD_LOGIC;

out1 : out STD_LOGIC);

end COMPONENT;

signal temp1:STD_LOGIC;

begin

U0:and3not PORT MAP(S1,S2,S3,temp1);

U1:and4not PORT MAP(not A,not B,not C,temp1,y0); U2:and4not PORT MAP(A,not B,not C,temp1,y1);

U3:and4not PORT MAP(not A,B,not C,temp1,y2);

U4:and4not PORT MAP(A,B,not C,temp1,y3);

U5:and4not PORT MAP(not A,not B,C,temp1,y4);

U6:and4not PORT MAP(A,not B,C,temp1,y5);

U7:and4not PORT MAP(not A,B,C,temp1,y6);

U8:and4not PORT MAP(A,B,C,temp1,y7);

end Behavioral;

由于有5个输入量，因此输入共有32种情况，仿真程序如下: LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY decoderwb IS

END decoderwb;

ARCHITECTURE behavior OF decoderwb IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT decoder

PORT(

A : IN std_logic;

B : IN std_logic;

C : IN std_logic;

S1 : IN std_logic;

S2 : IN std_logic;

S3 : IN std_logic;

Y0 : OUT std_logic;

Y1 : OUT std_logic;

Y2 : OUT std_logic;

Y3 : OUT std_logic;

Y4 : OUT std_logic;

Y5 : OUT std_logic;

Y6 : OUT std_logic;

Y7 : OUT std_logic

);

END COMPONENT;

--Inputs

signal A : std_logic := '0';

signal B : std_logic := '0';

signal C : std_logic := '0';

signal S1 : std_logic := '0';

signal S2 : std_logic := '0';

signal S3 : std_logic := '0';

--Outputs

signal Y0 : std_logic;

signal Y1 : std_logic;

signal Y2 : std_logic;