0-9999计数器程序
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2、0-9999计数器的低层设计（VHDL语言代码）
分频器程序：
l ibrary ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity div is
generic(n: integer := 50000000);
port(
clk :in std_logic;
q :out std_logic
);
end div;
architecture bhv of div is
signal count :integer range n - 1 downto 0 := n - 1; begin
process(clk)
begin
if clk'event and clk='1' and clk'last_value = '0' then count <= count - 1;
if count >= n / 2 then
q <= '0';
else
q <= '1';
end if;
if count <= 0 then
count <= n - 1;
end if;
end if;
end process;
end;
计数器程序：
l ibrary ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt_10 is
port(clk,en,reset :in std_logic;
cnt1,cnt2 :out std_logic_vector(3 downto 0)); end;
architecture bhv of cnt_10 is
signal temp1,temp2:std_logic_vector(3 downto 0);
signal c:std_logic;
begin
cnt1 <= temp1;cnt2<= temp2;
p1:process(clk,reset)
begin
if reset='1'then temp1 <="0000";
elsif clk'event and clk='1'then
if en='1'then
if temp1 <"1001"then temp1 <=temp1+1;c<='0';
else temp1 <="0000";c <='1';
end if;
end if;
end if;
end process p1;
p2:process(reset,c)
begin
if reset = '1' then temp2<="0000";
elsif c'event and c = '1' then
if en = '1' then
if temp2<"1001"then temp2<= temp2+1;
else temp2<="0000";
end if;
end if;
end if;
end process p2;
end;
数码管显示程序：
library ieee;
use ieee.std_logic_1164.all;
entity display is
port(clk_s :in std_logic;
data1, data2 :in std_logic_vector(3 downto 0);
dig :out std_logic_vector(1 downto 0);
seg :out std_logic_vector(7 downto 0) );
end;
architecture bhv of display is
signal cnt :std_logic;
signal d :std_logic_vector(3 downto 0);
begin
p0: process(clk_s)
begin
if clk_s'event and clk_s = '1' then cnt <= not cnt;
end if;
end process p0;
p1: process(cnt)
begin
case cnt is
when '0' => dig <= "10"; d <= data1;
when '1' => dig <= "01"; d <= data2;
end case;
end process p1;
p2: process(d)
begin
case d is
when "0000" => seg <= "11000000";
when "0001" => seg <= "11111001";
when "0010" => seg <= "10100100";
when "0011" => seg <= "10110000";
when "0100" => seg <= "10011001";
when "0101" => seg <= "10010010";
when "0110" => seg <= "10000010";
when "0111" => seg <= "11111000";
when "1000" => seg <= "10000000";
when "1001" => seg <= "10010000";
when others => seg <= "11111111";
end case;
end process p2;
end;