镁光原厂工程师对nandflash稳定性的分析——flash_mem_summit_jcooke_inconvenient_truths_nand

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Agenda
• NAND Flash Differences
– MLC vs. SLC – Architecture, Features, and Performance Comparisons
• NAND Error Modes
– Program Disturb – Read Disturb – Data Retention – Endurance – Wear Leveling – ECC Fixes Almost Everything

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Reducing Program Disturb
Program pages in a block sequentially, from page 0 to page 63 (SLC) or 127 (MLC) Minimize partial-page programming operations (SLC) It is mandatory to restrict page programming to a single operation (MLC) Use ECC to recover from program disturb errors
NAND Operation
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Two-Plane Features
Device is divided into two physical planes, odd/even blocks Users have the ability to: • Concurrently access two pages for read • Erase two blocks concurrently • Program two pages concurrently The page addresses of blocks from both planes must be the same during two-plane READ/PROGRAM/ERASE operations
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tPROG tBERS
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2Gb, 2K-Page SLC NAND Architecture
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2Gb, 2K-Page, 72nm, SLC Performance
Micron (72nm SLC) 2Gb die 2K Page Performance
Block Architecture
I/O I/O I/O I/O
NAND architecture is based on independent blocks Blocks are the smallest erasable units Pages are the smallest programmable units
40.00
37.62 33.50 28.94
35.00
30.00
25.00
M B /s e c
20.00
19.05 12.94 7.74 9.56
15.00
10.00
5.00
0.00
Page Read
Cache Read
2Plane Page Read
Page Program
Program Pge Cache
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4Gb, Two-Plane, 2K-Page SLC NAND Architecture
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4Gb, 2K-Page SLC NAND Performance
Micron (72nm SLC) 4Gb die 2K Page Performance

Charge collects on the floating gate causing the cell to appear to be weakly programmed Does not damage cells; ERASE returns cells to undisturbed levels Disturbed bits are effectively managed with error correction codes (ECC) Partial-page programming accelerates disturbance
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Program Disturb
Cells not being programmed receive elevated voltage stress Stressed cells • • Are always in the block being programmed Unselected 10V Page: Selected 20V Page:
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NAND Error Modes
Program Disturb Read Disturb Data Retention Endurance
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Let’s Get Orientated: NAND Architecture
2Plane Program 2Plane Program Page Page Cache Mode
NAND Operation
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8Gb, Two-Plane, 2K-Page MLC NAND Architecture
Santa Clara, CA USA August 2007
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37.42 32.41 27.30
7.73 4.28 4.79
9.56
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Open NAND Flash Interface
Future Micron NAND Flash devices support the ONFI specification Micron is a founding member of ONFI The ONFI 1.0 specification is available at http://www.onfi.org/ ONFI founders:
The Inconvenient Truths of NAND Flash Memory
Jim Cooke (jcooke@micron.com) Applications Engineering Director Micron Technology, Inc.
Santa Clara, CA USA August 2007
Open NAND Flash Interface (ONFI) helps to address many of these
Santa源自文库Clara, CA USA August 2007
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Cell Types – MLC vs. SLC
Features Bits per cell Voltage Data width (bits) Architecture Number of planes Page size Pages per block Reliability NOP (partial page programming) ECC (per 512 bytes) Endurance (ERASE / PROGRAM cycles) Array Operations
I/O I/O I/O I/O
Programmed Cells
Can either be on pages not selected, or in a selected page Unselected but not supposed to be 10V Page: programmed
Stressed Cells
35.00
31.62
30.00
25.00
23.85
M B /s e c
20.00
15.00
10.00
5.81
5.00
7.02
0.00
0.00 Page Read Cache Read 2Plane Page Read Page Program Program Pge Cache
0.00
0.00
2Plane Program 2Plane Program Page Page Cache Mode
Micron (55nm MLC) 16Gb die 4K Page Performance
40.00 35.00 30.00 25.00 M B /s e c 20.00 15.00 10.00 5.00 0.00 Page Read Cache Read 2Plane Page Page Program Program Pge 2Plane 2Plane Read Cache Program Page Program Page Cache Mode NAND Operation
5.58 3.00 3.25
6.49
NAND Opeation
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16Gb, Two-Plane, 4K-Page MLC NAND Architecture
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Two-Plane, 4K-Page MLC NAND Architecture
tR
MLC 2 3.3V x8 2 2,112–4,314 bytes 128 1 4+ <10K 50µs 600–900µs 2ms
SLC 1 3.3V, 1.8V x8, x16 1 or 2 2,112 bytes 64 4 1 <100K 25µs 200–300µs 1.5–2ms
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(Max) (Typ) (Typ)
• Partial pages can be programmed in some devices
Control Gate
String Memory Cell
Float Gate
64 pages per block*
Page
16,896 bits per page*
* Typical for 4Gb SLC

10V
0V
10V
0V
Strings being programmed are grounded; others are at 10V.
Note: Circuit structures and voltages are representative only. Details vary by manufacturer and technology node.
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All NAND Flash Devices Are Not Created Equal
Differences include:
• Cell types • Architectural • Performance • Timing parameters • Command set
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8Gb, 2K-Page MLC Performance
Micron (72nm MLC) 8Gb die 2K Page Performance
45.00 40.00 35.00 30.00
27.06 20.51 19.92
MB/sec
25.00 20.00 15.00 10.00 5.00 0.00 Page Read Cache Read 2Plane Page Read Page Program Program Pge Cache 2Plane Program Page 2Plane Program Page Cache Mode