verilog HDL 测试代码

`timescale 1ns/1ns

moduleJK_flip_flop(J,K,Clk,Q,Qbar);

inputJ,K,Clk;

outputQ,Qbar;

reg Q;

assignQbar=~Q;

always @(negedgeClk)

begin

case({J,K})

2'b00:Q=Q;

2'b01:Q=1;

2'b10:Q=0;

2'b11:Q=~Q;

default:Q=1'bx;

endcase

end

endmodule

moduleJK_flip_flop_tb ;

wire Q ;

wireQbar ;

regClk ;

reg J ;

reg K ;

initial

begin

J=0;

K=0;

Clk=0;

end

always

#2 Clk=!Clk;

always

begin

#6 J<=0;

#8 K<=0;

#16 J<=1;

#26 K<=1;

#36 J<=0;

#500 $stop; end

JK_flip_flop DUT (.Q (Q ) ,.Qbar (Qbar ) , .Clk (Clk ) , .J (J ) , .K (K ) ); endmodule