电子元件资料HC08AG

MC74HC08A

Quad 2−Input AND Gate

High −Performance Silicon −Gate CMOS

The MC74HC08A is identical in pinout to the LS08. The device inputs are compatible with Standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.

Features

•Output Drive Capability: 10 LSTTL Loads

•Outputs Directly Interface to CMOS, NMOS and TTL •Operating V oltage Range: 2.0 to 6.0 V •Low Input Current: 1 m A

•High Noise Immunity Characteristic of CMOS Devices

•In Compliance With the JEDEC Standard No. 7A Requirements •Chip Complexity: 24 FETs or 6 Equivalent Gates •

Pb −Free Packages are Available

3Y1

1A1PIN 14 = V CC PIN 7 = GND

LOGIC DIAGRAM

2B16

Y24A25B28

Y3

9A310B311

Y4

12A413

B4

Y = AB

Pinout: 14−Lead Packages (Top View)

13

14

12

11

10

9

8

2134567V CC B4A4Y4B3A3Y3A1

B1

Y1

A2

B2

Y2

GND

MARKING DIAGRAMS

A = Assembly Location WL or L = Wafer Lot YY or Y = Year

WW or W = Work Week G or G = Pb −Free Package TSSOP −14DT SUFFIX CASE 948G

SOIC −14D SUFFIX CASE 751A

HC

08ALYW G G

1

14

PDIP −14N SUFFIX CASE 646

MC74HC08AN AWLYYWWG

114

See detailed ordering and shipping information in the package dimensions section on page 3 of this data sheet.

ORDERING INFORMATION

L L H H L H L H

FUNCTION TABLE

Inputs

Output A B L L L H

Y (Note: Microdot may be in either location)

MAXIMUM RATINGS

Symbol Parameter Value Unit V CC DC Supply Voltage (Referenced to GND)– 0.5 to + 7.0V V in DC Input Voltage (Referenced to GND)– 0.5 to V CC + 0.5V V out DC Output Voltage (Referenced to GND)– 0.5 to V CC + 0.5V

I in DC Input Current, per Pin± 20mA

I out DC Output Current, per Pin± 25mA

I CC DC Supply Current, V CC and GND Pins± 50mA

P D Power Dissipation in Still Air,Plastic DIP†

SOIC Package†

TSSOP Package†750

500

450

mW

T stg Storage Temperature– 65 to + 150_C

T L Lead Temperature, 1 mm from Case for 10 Seconds

Plastic DIP, SOIC or TSSOP Package260

_C

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress

ratings only. Functional operation above the Recommended Operating Conditions is not implied.

Extended exposure to stresses above the Recommended Operating Conditions may affect device

reliability.

†Derating—Plastic DIP: – 10 mW/_C from 65_ to 125_C

SOIC Package: – 7 mW/_C from 65_ to 125_C

TSSOP Package: − 6.1 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D). RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Min Max Unit

V CC DC Supply Voltage (Referenced to GND) 2.0 6.0V

V in, V out DC Input Voltage, Output Voltage

(Referenced to GND)

0V CC V

T A Operating Temperature, All Package Types– 55+ 125_C

t r, t f Input Rise and Fall Time V CC = 2.0 V (Figure 1)V CC = 4.5 V

V CC = 6.0 V 0

1000

500

400

ns

This device contains protection

circuitry to guard against damage

due to high static voltages or electric

fields. However, precautions must

be taken to avoid applications of any

voltage higher than maximum rated

voltages to this high−impedance cir-

cuit. For proper operation, V in and

V out should be constrained to the

range GND v (V in or V out) v V CC.

Unused inputs must always be

tied to an appropriate logic voltage

level (e.g., either GND or V CC).

Unused outputs must be left open.