标准CMOS工艺集成肖特基二极管设计与实现_英文文献和翻译

*Project supported by National High T echnology Research and Development Program of China(No.2003AA1Z1280) Li Qiang male,PhD candidate.His research field emphases on analog integrate circuit design.Email:liqi ang@ Received 24M ay 2004,revised manuscript received 2August 20042005Chi n ese Ins titute of Electron i csDesign and Fabrication of Schottky Diode withStandard CMOS Process *Li Qiang,Wang Junyu,Han Yifeng,and M in Hao(S tate K e y L abor atory o f AS IC&Syste m ,Fudan Univ ersity ,S hanghai 200433,China)Abstract:Desig n and fabrication of Schottky bar rier diodes (SBD)w ith a commer cial standard 0 35 m CM OS process are described.I n order to reduce the series resistor of Schottky contact,interdigitating the fingers of scho ttky diode layout i s adopted.T he I V ,C V ,and S parameter are measured.T he parameters of realized SBD such as t he saturation cur rent,breakdow n voltage,and the Schottky barr ier heig ht are given.T he SPI CE simulation model of the realized SBDs is g iven.Key words:CM O S;Schottky dio de;integration EEAC C:2560H;2570DC LC number:T N311+7 Document code:A Article ID:0253 4177(2005)02 0238 051 IntroductionSchottky diodes have advantages such as fast sw itching speed and low forward voltage drop.Due to these ex cellent hig h frequency performance,they have been w idely used in pow er detection and microwave network circuit[1].Schottky diodes are often fabricated by depositing metals on n ty pe or p type semicon ductor materials such as GaAs and SiC [2~4].Theproperties of forw ard biased Schottky diodes are de termined by m ajority carrier,while minority carrier prim arily determine those properties of p n diodes.In order to improve high frequency performance and de crease supply voltage of IC,integ rating the Schottky diode into modern IC is very important.But the pro cess that can integrate Schottky diode is often not commercially available and not to integrate with CM OS circuits monolithically.Design about it has ev er been introduced and the fabrication of Schottky in standard CMOS process w ith the additional CMOS process has been repoted w hile not show n the measured results [5,6].In this paper w e describe the w ay todesign and layout a Schottky diode in a low cost com mercial standard CM OS process w ithout any processmodification.The measured results and SPICE simu lation model are offered.2 Design and layout of Schottky diodeThis design w as performed throug h M PW(multi project wafer)in charted 0 35 m CM OS process.A Schottky diode is form ed w hen a metal layer is de posited directly onto a low doped n type or p type sem iconductor region.When these tw o materials are brought into contact with each other,the difference in potential g ives rise to a barrier heig ht that the elec trons have to overcom e for current to flow.The metal on the low doped semiconductor is the anode and the sem iconductor material,w hich contacted through an ohm ic contact,is the cathode.In our design only n type Schottky diodes w ere used.A cross section of the Al Si Schottky diode is show n in Fig.1.第26卷 第2期2005年2月半 导 体 学 报CHI NESE JOU RNAL OF SEM ICON DUCT ORSVol.26 No.2 Feb.,2005Fig.1 Cross section of Al Si SchottkyIn our design,there w as no p+active reg ion un der the contact in n well,the contact material is alu m inum w ith area A(equal to d d).Therefore,the metal layer will connect directly to the low doped n w ell.As a result there forms a Al Si Schottky diode contact.For the foundry process determines most of the parameters such as w ork function of metal and density of n well,w e can only control the area A of Schottky diode to modify the I V curve or other pa rameters of the diode.Fig ure2show s the layout of designed Schottky diode.In order to reduce the series resistance of the Schottky diode,firstly,the distance betw een the Schottky and ohmic contacts w as set to the minimum allow able according to the design rules.Secondly,in terdigitating the fingers of Schottky diode layout w as adopted.The interdigitated layout offers the advan tage of parallel connecting of each series resistance un der Schottky contact.3 Measurement results of the fabricated diodeThree types of interdigitating fingers Schottky diodes w ith different area have been fabricated in the charted standard0 35 m CM OS process throug h M PW.The measured results are discussed.3.1 I V performanceConsidering the series resistor,the I V function of Schottky diode can be express as[7]I=I s exp(V-IR snV t)1-exp(V-I R sV t)(1)F ig.2 (a)Cross section layout of t he r ealized Schottkydiode;(b)P lane section layout of the r ealized Schottkydiodew here V is the bias voltage,I s is the saturation current,R s is the series resistor,V t is the therm al voltagew hich equals to kT/q,and n is the SBD ideality factor which can be calculated as:n=I/(V td Id V)(2)If the bias voltage is larger than3kT/q,Equation(1)can be sim plified asI=I s ex p(V-I R sn V t)(3)And the Schottky barrier heig ht B can be calculatedasB=V t ln(A A*T2I s)(4)w here A*is the effective Richardson constant.The measured I V curve is show n in Fig.3.By fitting Eq.(3)and the m easured results,wecan get the parameters of the realized SBDs,w hich areshow n in T able1.T able1 P ar ameters of the realized SBDArea/ m2Finger number I s/A R s/SBD116102 10-810SBD2 1.625 10-990SBD30.6401 10-9200From T able1,w e can observe that w ith thenumber of interdig itating fingers increasing,the seriesresistance can be reduced evidently.239第2期Li Q iang et al.: Desig n and Fabricatio n of Schottky Diode w ith Standard CM OS ProcessF ig.3 (a)M easured I V cur ves at forward bias;(b)M easur ed I V curves at rever se bias Area of SBD1,SBD2,and SBD3ar e r espectively 16,1 6,and 0 64 m 2.T he measured statistic result of barrier height Bfor the realized SBD is show n in Fig.4.There are to tal 90samples that have been measured (30samples for each of SBD1,SBD2,SBD3).And the barrier height of the realized SBD is about 044eV.F ig.4 Statistic result of B for the measur ed SBD (total 90samples)The breakdow n voltage is about 4 5V.In future w ork,the breakdow n voltage can be ex tended by some methods that have been used in normal SBD de sig n,such as the fabrication of SBD w ith self alig ned guard ring[8].3.2 C V performanceThe small signal junction capacitor C j of Schot tky diode is g iven below,C j =Aq s N d2( B - n -V)(5)w here N d is the doping concentration of the n w ell, n is the potential difference betw een the fermi level and the conduction band edge w hich equals to (E C -E f)/q.Figure 5shows the measured reverse bias C V curve for SBDs.Fig.5 M easured C V curve f =2 4GHz3.3 S parameter measurement and SBD high frequency modelingIn order to measure the high frequency S param eter of the designed devices,each SBD w as laid w ith three probe pads.The size of middle signal pad is 85 m 85 m and top/bottom g round size is 85 m 135 m.U sing the GSG probe and netw ork analysis instrument,w e can get the S parameter of the de sig ned SBD.But the directly measured results of Sparameter include the parasitic capacitance of pads,metal line and overlays.For the designed device is very small,these parasitic parameters could not be ne240半 导 体 学 报第26卷g lected and must be subtracted from the directly mea sured S parameter by GSG probe.In our w orks,w e fabricated two dummy GSG pads w ith no tested de vice.The dummy pads size is the same as that includ ing SBD.One dummy GSG pads signal is connected w ith GND called short pad.The other dummy GSG pads sig nal is open w hich is called open pad.The S parameter of dummy pads should be measured.Then w e can get the parasitic capacitance and resistance of the pad and metal line.And subtracting these parasitic parameter w e can get the S parameter of SBDs with no parasitic capacitance and resistance.T his method is called de embedding technology [9].U sing the measured S parameter,the SPICE model can be abstracted for high frequency simula tion.Figure 6show s the simulation model of the real ized SBD.L 1and L 2ex hibit the input and output se rial inductance.C i and C o exhibit the anode input and cathode node output capacitance respectively.C 1ex hibits the parasitic capacitance betw een the interdigi tating fingers of Schottky diode s two ports.R 1and R 2model for the resistance under the n w ell w hich connects the place under NWLL to ground.T he pn diode reflects the parasite n w ell p sub diode.In our design,the parameter of the pn diode can be gotten from the charted 0 35 m analog CMOS process SPICEmodel.F ig.6 Simulatio n model of the r ealized SBDFig ure 7show s the measured and simulation S parameter of SBD1(after de em bedding ).Table 2shows the parameter of SBD1by the simulation mod el.The frequency is swept from 50MHz to 40GH z.And the model can match the measured results up to 30GHz.Figure 8show s the photo of realized SBD under probemeasurement.Fig.7 M easurement and simulation S parameter of SBD1from 50M Hz to 40GHz after deembeddingFig.8 Photo of the realized SBD under GSG pr obe mea sur ementT able 2 Component value of SBD1L 10.005nH L 20.005nH C i 0.01pf C o 0.05pf R 1200 R 2200 C 10.14pf I s 2 10-8A R s 10 C j00.022pf B v4.5VNbv234 ConclusionFabrication of Schottky barrier diode in standard CMOS process throug h M PW are performed.T he barrier heig ht of the Al nSi contacts is about 0 44eV.The measured I V ,C V ,and S parameter of the re241第2期Li Q iang et al.: Desig n and Fabricatio n of Schottky Diode w ith Standard CM OS Processalized SBDs are show n in this paper.The advantages of this SBD design are low cost and can be integ rated into commercial standard CM OS process.In the fu ture w ork,more emphasis w ill be focused on extension of the reverse breakdow n voltage and frequency range of the SBDs designed on standard CM OS process.References[1] Sharma B L.M etal semiconductor Schottky barrier junctionsand th eir applications.New York:Plenum,1984[2] Hudait M K,Vankatesw arlu P,Krupanidhi S B.Electricaltransport characteristics of Au/n GaAs Schottky diodes on n Geat low temperatures.Solid S tate Electron,2001,45(1):133 [3] Zhang Yuming,Zhang Yimen,Alexandrov P,et al.Fabrication of4H SiC m erged PN S chottky diodes.Chinese Journal of S emiconductors,2001,22(3):265[4] Zhang Haiyan,Ye Zhizhen,Huang Jingyun,et al.Fabrication ofS chottky barrier diodes of high frequency based on thin siliconepilayer.Chi n ese Journal of Semiconductors,2003,24(6):622(i n Chinese)[张海燕,叶志镇,黄靖云,等.在薄硅外延片上制备高频肖特基势垒二极管.半导体学报,2003,24(6):622] [5] M ilanovic V,Gai tan M,M arshall J C,et al.CM OS foundry i mplem entation of Schottky diodes for RF detection.IE EE TransElectron Devices,1996,43(2):2210[6] Rivera B,Baker R J,M elngaili s J.Design and layout of S chottkydiodes in a standard CM OS process.International SemiconductorDevice Research Symposium,2001:79[7] Rhoderick E H.M etal semiconductor contacts.Second edition.Oxford:Ox ford University Press,1988[8] C ha S I,Cho Y H.Novel Schottky di ode w i th selfalignedguard ring.Electron Lett,1992:1221[9] Aktas A,Ismail M.Pad de embedding in RF CM OS.IEEEC i rcuit and Devices M agazine,2001,17(3):8标准CMO S工艺集成肖特基二极管设计与实现*李 强 王俊宇 韩益锋 闵 昊(复旦大学专用集成电路与系统国家重点实验室,上海 200433)摘要:提出了一种在标准CM OS工艺上集成肖特基二极管的方法,并通过M P W在charted0 35 m工艺中实现.为了减小串连电阻,肖特基的版图采用了交织方法.对所设计的肖特基二极管进行了实测得到I V,C V和S参数,并计算得出所测试肖特基二极管的饱和电流、势垒电压及反向击穿电压.最后给出了可用于SPI CE仿真的模型.关键词:CM OS;肖特基二极管;集成EEAC C:2560H;2570D中图分类号:T N311+ 7 文献标识码:A 文章编号:0253 4177(2005)02 0238 05*国家高技术研究发展计划资助项目(批准号:2003AA1Z1280)李 强 男,博士研究生,研究方向为模拟集成电路设计.Email:li qiang@2004 05 24收到,2004 08 02定稿 2005中国电子学会242半 导 体 学 报第26卷。