摩尔定律和超越摩尔定律

More than Moore(Functional Diversificaevices is provided by incorporating functionalities that do not necessarily scale according to "Moore's Law“.
Beyond CMOS (beyond silicon basic)
New devices model contains new principle and new materials or structures
Example of More moore
New structure
New technology
Gate
Source
Substrate
Channel/Drain
• • • • •
Drain
• S/D leakage current • Gate leakage current
Power
Surface scattering - mobility High E-field - mobility DIBL drain to source leakage IOFF Subthreshold slope >> ln(10)kT/q IOFF VG - VT decrease ION
create high electric field. It can destroy the mechanics of the devices
The result of high heat
Two ways for us
More moore(scaling)：
1.geometry scaling :go on reduce the size on the logical memory at the horizontal direction and vertical directions 2. Equivalent scaling: Improved three-dimensional device structures and other new materials or none geometry technology
Moore’s Law observation that ,over the history of computing hardware the number of transistors on integrated circuit doubles every two years.
Describes a driving force of technological and social change in the late 20th and early 21st centuries. The period is often quoted as 18 months because of Intel executive David House, who
predicted that chip performance would double
every 18 months
Gordon Moore's original graph from 1965
The tendency of semiconductors development
The graphs tell us that the change tend of the degree of integration follow the Moore’s Law. At the same time,we can find that the feature size become small.In another we Rd,enlargement of the degree of integration due to narrow of devices.
First generation VLSI system
New VLSI system
MOS 0.03
0.01 0.003 1980 1990 2000
Limit of MOS
QED
2010
year
We can see that COMS scaling meets choke point with the reduce of size.
year 2001 2003 2005 2007 Size(μm) 0.18 0.15 0.13 0.1
2009
2011
0.07
0.05 Feature size change with time
Feature size with years
65 nm 2005
45 nm 2007
2times Transistor witching speed：promote more than 20% Transistor witch power：reduce more than 30%
At 10 nm gate lengths, the transistors continue
to function as MOS devices but they limited by off-state leakage
Transistor off-state leakage vs gate length
Transistor density：promote
Source- drain leakage power ：reduce
more than
5times
Gate oxide leakage power：reduce
more than
10times
3 1 size/um 0.3 0.1
ASICs Advanced technology
Student Number:M201472140 Name: 辛超
Moore’s Law and the tendency of CMOS
scaling
The problem Moore’s Law and COMS scaling
meets
MTM or others
What’s the Moore’s Law?
Thermal effect: with the large degree ofintegration ,more
heat is made .so IC need more energy and the heat reduce device’s performance .
High electric field: extreme small size lead low voltage
what’s the problem CMOS scaling meet?
• Tunneling current IOFF • Gate depletion EOT
Gate stack
Source/Drain
• Parasitic resistance • Doping level, abruptness
Gate(Au)
From the examples above ,we can see that there are too many means to improve the performance of semiconductor device and get over the shortage of the traditional technologies. However the most we need is advanced Processing Technology and efficient way to take the design into industry field. In the long term , we will meet a new great age of semiconductor
Intel repors: At gate lengths of 20 & 15 nm, the devices still have excellent device characteristics, but off-state leakage and gate leakage do increase.
Physics limit
Quantum effect：when the size become extremely small
we have to consider the quantum effect. That break the mechanics of the transistor.
Thank you