FPGA_ADC0809_statemechine verilog 代码(状态机)
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// FPGA接50MHZ 晶振
`timescale 1ns/1ns
module ADC0809_statemechine( sys_clk,
sys_rstn,
adc_clk,
adc_start,
adc_eoc,
adc_oe,
adc_ale,
adc_data,
adc_led,
);
input sys_clk,sys_rstn,adc_eoc;
input [0:7]adc_data;
output adc_clk,adc_start,adc_ale,adc_oe; output [0:7]adc_led;
reg adc_clk, adc_start, adc_ale, adc_oe, lock; reg [0:7]adc_led;
reg [0:7]counter_500k;
reg [0:7]state;
parameter
idle =8'b00000000,
ale_enable =8'b00000001,
start_1 =8'b00000010,
start_0 =8'b00000100,
eoc_0 =8'b00001000,
eoc_1 =8'b00010000,
oe_enable =8'b00100000,
get_data =8'b01000000;
initial
begin
state=8'b00000000;
adc_ale=1'b0;
adc_start=1'b0;
adc_oe=1'b0;
adc_clk=1'b0;
adc_led<=8'b11111111;
end
always @(posedge sys_clk)
begin
counter_500k<=counter_500k+1'b1;
if (counter_500k>=8'd50)
begin
counter_500k<=8'd0;
adc_clk<=~adc_clk; //500khz(2us), ADC work frquency/clock end
end
always @(posedge adc_clk)
begin
case (state)
idle:
begin
adc_ale<=1'b0;
adc_start<=1'b0;
adc_oe<=1'b0;
lock<=1'b0;
state<=ale_enable;
end
ale_enable:
begin
adc_ale<=1'b1;
adc_start<=1'b0;
adc_oe<=1'b0;
lock<=1'b0;
state<=start_1;
end
start_1:
begin
adc_ale<=1'b0;
adc_start<=1'b1;
adc_oe<=1'b0;
lock<=1'b0;
state<=start_0;
end
start_0:
begin
adc_ale<=1'b0;
adc_oe<=1'b0;
lock<=1'b0;
state<=eoc_0;
end
eoc_0:
begin
adc_ale<=1'b0;
adc_start<=1'b0;
if (adc_eoc==1'b0)
begin
adc_oe<=1'b0;
lock<=1'b0;
state<=eoc_0;
end
else
begin
adc_oe<=1'b1;
lock<=1'b0;
state<=eoc_1;
end
end
eoc_1:
begin
adc_ale<=1'b0;
adc_start<=1'b0;
adc_oe<=1'b1;
lock<=1'b0;
state<=oe_enable;
end
oe_enable:
begin
adc_ale<=1'b0;
adc_start<=1'b0;
adc_oe<=1'b0;
lock<=1'b1;
state<=get_data;
end
get_data:
begin
adc_start<=1'b0;
adc_oe<=1'b0;
lock<=1'b0;
adc_led<=adc_data;
state<=idle;
end
default:
begin
adc_ale<=1'b0;
adc_start<=1'b0;
adc_oe<=1'b0;
lock<=1'b0;
state<=idle;
end
endcase
end
endmodule