Mixed Verilog VHDL simulation with NC(verilog)-Sim

-- High-performance mixed-languages simulation solution
-- Increased simulation productivity through advanced debug tools -- Low-overhead integrated code coverage
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Interleaved Native Compiled Code
• Present and future extensions to Native Compiled Code address the performance challenges of a singlesimulation strategy • Multiple representations – behavioral / RTL / gate / UDP • Multiple paradigms – Event / Cycle • Multiple languages – Verilog / HDL • Mixed signal – Analog / Digital
•Example Shell to Import VHDL into Verilog module inv ( o , i ) ( * const integer foreign = “ VHDL ( event ) WORKLIB.inv:proc”; * ); output o ; input i ; endmodule
Time update code K
K K K K Event scheduling Kernel (distributed)
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Simulating Multi-Language Source
•Co-execution of Verilog and VHDL simulation models •The foreign model import shell
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Importing VHDL Source Code into NC Verilog
• Define libraries and the work library in cds.lib and hdl.var
include $CDS_INST_DIR/tools/inca/files/cds.lib
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Understanding the Model Shell
•Example Shell to Import Verilog into VHDL Library ieee; use ieee.std_logic_1164.all; entity inv is port ( o : out std_logic; i : in std_logic); end inv; architecture verilog of inv is attribute foreign of verilog: architecture is “ VERILOG (event ) worklib.inv:module”; begin end;
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NC-Sim: The heart of a complete simulation solution
Transaction-based System-level Designs And Testbench Static HDL Analysis Testbench design
Algorithm Design
ncelab top: struct
ncsim top: struct
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Generating a Model Shell with ncshell
•Example • ncshell -import vhdl -into verilog inv:proc • Produces shell file inv.vs and compiles into view shell • ncshell -import verilog -into vhdl inv • Produces shell file inv.vhd and analyzes it into
•Importing a VHDL model into a Verilog design
•Importing a Verilog model into a VHDL design
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Co-executing Verilog and VHDL
•Co-execution is the simultaneous simulation of multiple simulation languages in a single process.
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Mixed Verilog/VHDL simulation with NC-Sim
義隆電子 王偉民 29 Aug 2001
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Agenda
•Overview of Cadence NC-Sim
•Simulating Multi-Language Source •Mixed VHDL testbench/Verilog Gate Level Simulation
•You can import VHDL into a Verilog model or Verilog into a VHDL model -- Compile Verilog with ncverilog or ncvlog and VHDL with ncvhdl •You encapsulate second-language hierarchies in a model shell -- You can use the ncshell utility to automatically create the shell
architecture verilog
• Produces package file inv_comp.vhd containing component definition
ຫໍສະໝຸດ Baidu
• You can also use ncshell to generate shells to import
LMSFI, FMI, or Swift models into a VHDL design.
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Importing Verilog Source Code into NC VHDL
• Analyze VHDL source, package, and configuration files with ncvhdl ncvhdl test.vhd top.vhd • Elaborate and simulate the design with ncelab and ncsim
include $CDS_INST_DIR/tools/inca/files/hdl.var • Analyze the VHDL source files with ncvhdl
ncvhdl and2.vhd
• Generate and compile a Verilog shell with ncshell ncshell -import vhdl -into verilog and2:proc
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Importing VHDL Source Code into NC Verilog
• Compile the Verilog source files with ncvlog ncvlog test.v top.v • Elaborate and simulate the design with ncelab and ncsim ncelab top:module
•Summary
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Overview of Cadence NC-Sim
VHDL Timing Verilog
External Model， Engines， & Tools
PLI VPI VHPI OMI Industry Standard Interfaces
VHDL Compilation
Verilog Compilation
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Generating a Model Shell with ncshell
•Use ncshell to generate a shell for foreign model import
•Syntax :
• ncshell -import vhdl -into verilog [-options ][library.]entity:architecture • ncshell -import verilog -into vhdl [-options ][library.]cell[:view]
• Compile the Verilog source files with ncvlog
ncvlog and2.v • Generate and analyze a VHDL shell with ncshell ncshell -import verilog -into vhdl and2:module
ncsim top:module
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Importing Verilog Source Code into NC VHDL
• Define libraries and the work library in cds.lib and hdl.var include $CDS_INST_DIR/tools/inca/files/cds.lib include $CDS_INST_DIR/tools/inca/files/hdl.var
•Each imported hierarchy retains its own features and limitations
-- Case sensitivity -- PLI vs. CIF
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Understanding the Model Shell
•The model shell encapsulates the foreign model. It converts port types and generics( parameters) . • It defines the foreign entity, and its type, and for nonINCA simulators,defines the slave simulator.
C/C++ Testbench Digital Simulation
Transistor Level
NC-Sim
Analog/Mixed-Signal
Support for mixed Links to physical Design verification Code Coverage Analysis Simulation Debug Transaction Analysis Analog/Digital Designs
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How Native Compiled Code is interleaved
Verilog
VHDL Simulator-X
Compile
Compile
Compile
VST
AST
……
Elaborate, Generate Code
Update
Verilog VHDL Simulation - X K
• Co-execution is a more efficient solution than cosimulation, which requires multiple simulation processes to communicate over an IPC backbone.
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Co-executing Verilog and VHDL
Nclaunch SimVision Signalscan
Central Elaboration Single Kernel Engine Coverage Tracking
Advanced Debug Environment
Complete simulation environment targeted at SoC design