EDA课后问题详解(适用于朱正伟《EDA技术及应用》)
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1.1、设计集成计数器74161，设计要求如下：
4-BIT BINARY UP COUNTER WITH SYNCHRONOUS LOAD AND ASYNCHRONOUS CLEAR NOTE
INPUTS： CLK LDN CLRN D C B A
OUTPUTS：QD QC QB QA RCO
*RCO = QD & QC & QB & QA
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT4 IS
PORT(
CLK,LDN,CLRN : IN STD_LOGIC;
D,C,B,A : IN STD_LOGIC;
CARRY : OUT STD_LOGIC;
QD,QC,QB,QA : OUT STD_LOGIC
);
END;
ARCHITECTURE A OF CNT4 IS
SIGNAL DATA_IN: STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
DATA_IN<=D&C&B&A;
PROCESS(DATA_IN,CLK,LDN,CLRN)
V ARIABLE CNT:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
IF CLRN='0' THEN
CNT:=(OTHERS=>'0');
ELSIF CLK'EVENT AND CLK='1' THEN
IF LDN='0' THEN
CNT:=DATA_IN;
ELSE
CNT:=CNT+1;
END IF;
END IF;
CASE CNT IS
WHEN "1111"=> CARRY<='1';
WHEN OTHERS=> CARRY<='0';
END CASE;
QA<=CNT(0);
QB<=CNT(1);
QC<=CNT(2);
QD<=CNT(3);
END PROCESS;
END A;
1.2、设计一个通用双向数据缓冲器，要求缓冲器的输入和输出端口的位数可以由参数决定。
设计要求：N BIT数据输入端口A，B。工作使能端口EN=0时双
向总线缓冲器选通，
DIR=1，则A=B；反之B=A。
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY BIDIR IS
GENERIC(N:INTEGER:=8);
PORT( A,B : INOUT STD_LOGIC_VECTOR(N-1 DOWNTO 0);
EN,DIR : IN STD_LOGIC);
END;
ARCHITECTURE A OF BIDIR IS
BEGIN
PROCESS(EN,DIR)
BEGIN
IF EN='0' THEN
A<=(OTHERS=>'Z');
B<=(OTHERS=>'Z');
ELSE
IF DIR='1' THEN
B<=A;
ELSE
A<=B;
END IF;
END IF;
END PROCESS;
END A;
2.1、用VHDL语言编程实现十进制计数器，要求该计数器具有异步复位、同步预置功能。
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY CNT_10_2 IS
PORT(
CLK,CLR : IN STD_LOGIC;
COUNT : OUT STD_LOGIC
);
END;
ARCHITECTURE A OF CNT_10_2 IS
SIGNAL CNT_10 : INTEGER RANGE 0 TO 10;
BEGIN
PROCESS(CLK,CLR)
BEGIN
IF CLR='1' THEN
CNT_10<=0;
ELSIF CLK'EVENT AND CLK='1' THEN
CNT_10<=CNT_10+1;
IF CNT_10=9 THEN
CNT_10<=0;
COUNT<='1';
ELSE
COUNT<='0';
END IF;
END IF;
END PROCESS;
END A;
2.2、设计实现一位全减器。
行为描述: F_SUB4
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY F_SUB4 IS
PORT(
A,B,CIN : IN STD_LOGIC;
DIFF,COUT : OUT STD_LOGIC
);
END;
ARCHITECTURE A OF F_SUB4 IS
BEGIN
DIFF<=A XOR B XOR CIN;
COUT<=(NOT A AND B) OR (NOT A AND CIN) OR (B AND CIN); END A;
数据流描述F_SUB1
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY F_SUB1 IS
PORT(
A,B :IN STD_LOGIC;
CIN :IN STD_LOGIC;
DIFF,COUT : OUT STD_LOGIC
);
END;
ARCHITECTURE A OF F_SUB1 IS
SIGNAL S :STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
S<=CIN&A&B;
PROCESS(A,B,CIN)
BEGIN
CASE S IS
WHEN "000" => DIFF<='0';COUT<='0';
WHEN "001" => DIFF<='1';COUT<='1';
WHEN "010" => DIFF<='1';COUT<='0';
WHEN "011" => DIFF<='0';COUT<='0';
WHEN "100" => DIFF<='1';COUT<='1';
WHEN "101" => DIFF<='0';COUT<='1';