基本数字逻辑单元的设计
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2
ARCHITECTURE data_flow OF tri_buf8 IS
PROCESS (en, din) BEGIN
En din(0)
IF (en='1') THEN dout <= din;
ELSE
din(1) din(2)
dout <= "ZZZZZZZZ"; END IF; END PROCESS;
8
WHEN "0010" => q <= "10100100"; WHEN "0011" => q <= "10110000"; WHEN "0100" => q <= "10011001"; WHEN "0101" => q <= "10010010"; WHEN "0110" => q <= "10000010"; WHEN "0111" => q <= "11011000"; WHEN "1000" => q <= "10000000"; WHEN "1001" => q <= "10010000"; WHEN OTHERS => q <="11111111"; END CASE; END PROCESS; END seg-rtl;
第四章
基本数字逻辑单元的设计
1
4.1 组合逻辑设计
4.1.2 三态缓冲器和总线缓冲器
8bit单向总线缓冲器
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY tri_buf8 IS PORT (din:IN STD_LOGIC_VECTOR (7 DOWN TO 0); dout：OUT STD_LOGIC_VECTOR (7 DOWN TO 0); en：IN STD_LOGIC); END tri_buf8;
7
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY seg_del IS PORT (d:IN STD_LOGIC VECTOR (3 DOWN
TO 0 ); q：OUT BIT_VECTOR (7 DOWN TO 0)); END seg_del; ARCHITECTURE seg_rtl OF seg_del IS BEGIN PROCESS(d) BEGIN CASE d IS WHEN "0000" => q <= "11000000"; WHEN "0001" => q <= "11111001";
0101 5 1 0 0 1 0 0 1 0
0110 6 1 0 0 0 0 0 1 0
0111 7 1 0 1 0 0 1 1 1
1000 8 1 0 0 0 0 0 0 0
1001 9 1 0 0 1 0 0 0 0
其它
11111111
Vcc
fa
b
e
g d
c
.h
BCD-段选码译码器
d0 d1 d2 d3
din(3) din(4)
END data_flow ;
din(5)
din(6)
din(7)
dout(0) dout(1) dout(2) dout(3) dout(4) dout(5) dout(6) dout(7)
3
双向总线缓冲器
用VHDL语言描述的双向总线缓冲器。
a
b
en dir 功能
dir
5
P2: PROCESS (b, dir, en) BEGIN IF ((en='0') AND (dir='0')) THEN aout <= b; ELSE aout <= "ZZZZZZZZ"; END IF a <= aout;
END PROCESS P2; END rtl;
6
BCD码—段选码译码器。
A3 B3
ci a b sum co
ci a b sum co
ci a b sum co
ci a b sum co
S0 S0
S1 S1
S2 S3
S3 CO Sn-1 cout
N位超 前进位 加法器
SUM CI A B
SUM CI A B
SUM CI A B
CI0 A0 B0
CI1 A1 B1
CI2 A2 B2
END dobl_tri_buf8;
4
ARCHITECTURE rtl OF dobl_ tri_buf8 IS SIGNAL aout, bout:STD_LOGIC_VECTOR (7 DOWN TO 0 ); BEGIN P1: PROCESS (a, dir, en) BEGIN IF ((en='0') AND (dir='1')) THEN bout <= a; ELSE bout <="ZZZZZZZZ"; END IF; b <= bout; END PROCESS P1;
ci cout
ARCHITECTURE rtl OF full_adder IS
BEGIN
sum <= a XOR b XOR ci；
cout <= (a AND b) OR (a AND ci ) OR ( b AND ci)；
END rtl;
10
4位串行进位加法器
CI A0 B0
A1 B1
A2 B2
BCD码输入与LED显示器字段的对应关系
Fra Baidu bibliotek
BCD码 数字 显 示 段
hgfedcba
0000 0 1 1 0 0 0 0 0 0
0001 1 1 1 1 1 1 0 0 1
0010 2 1 0 1 0 0 1 0 0
0011 3 1 0 1 1 0 0 0 0
0100 4 1 0 0 1 1 0 0 1
进位产生逻辑
SUM CI A B
9
4.1.4 运算器的设计
一位全加器的设计.
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; ENTITY full_adder IS
a sum
PORT (a, b, ci: IN STD_LOGIC;
b
sum, cout： OUT STD_LOGIC); END full_adder;
1 X 高阻态
0 0 a<=b
en
0 1 b<=a
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY dobl_tri_buf8 IS
PORT (a, b:INOUT STD_LOGIC_VECTOR (7 DOWN TO 0); dir, en：IN STD_LOGIC);
ARCHITECTURE data_flow OF tri_buf8 IS
PROCESS (en, din) BEGIN
En din(0)
IF (en='1') THEN dout <= din;
ELSE
din(1) din(2)
dout <= "ZZZZZZZZ"; END IF; END PROCESS;
8
WHEN "0010" => q <= "10100100"; WHEN "0011" => q <= "10110000"; WHEN "0100" => q <= "10011001"; WHEN "0101" => q <= "10010010"; WHEN "0110" => q <= "10000010"; WHEN "0111" => q <= "11011000"; WHEN "1000" => q <= "10000000"; WHEN "1001" => q <= "10010000"; WHEN OTHERS => q <="11111111"; END CASE; END PROCESS; END seg-rtl;
第四章
基本数字逻辑单元的设计
1
4.1 组合逻辑设计
4.1.2 三态缓冲器和总线缓冲器
8bit单向总线缓冲器
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY tri_buf8 IS PORT (din:IN STD_LOGIC_VECTOR (7 DOWN TO 0); dout：OUT STD_LOGIC_VECTOR (7 DOWN TO 0); en：IN STD_LOGIC); END tri_buf8;
7
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY seg_del IS PORT (d:IN STD_LOGIC VECTOR (3 DOWN
TO 0 ); q：OUT BIT_VECTOR (7 DOWN TO 0)); END seg_del; ARCHITECTURE seg_rtl OF seg_del IS BEGIN PROCESS(d) BEGIN CASE d IS WHEN "0000" => q <= "11000000"; WHEN "0001" => q <= "11111001";
0101 5 1 0 0 1 0 0 1 0
0110 6 1 0 0 0 0 0 1 0
0111 7 1 0 1 0 0 1 1 1
1000 8 1 0 0 0 0 0 0 0
1001 9 1 0 0 1 0 0 0 0
其它
11111111
Vcc
fa
b
e
g d
c
.h
BCD-段选码译码器
d0 d1 d2 d3
din(3) din(4)
END data_flow ;
din(5)
din(6)
din(7)
dout(0) dout(1) dout(2) dout(3) dout(4) dout(5) dout(6) dout(7)
3
双向总线缓冲器
用VHDL语言描述的双向总线缓冲器。
a
b
en dir 功能
dir
5
P2: PROCESS (b, dir, en) BEGIN IF ((en='0') AND (dir='0')) THEN aout <= b; ELSE aout <= "ZZZZZZZZ"; END IF a <= aout;
END PROCESS P2; END rtl;
6
BCD码—段选码译码器。
A3 B3
ci a b sum co
ci a b sum co
ci a b sum co
ci a b sum co
S0 S0
S1 S1
S2 S3
S3 CO Sn-1 cout
N位超 前进位 加法器
SUM CI A B
SUM CI A B
SUM CI A B
CI0 A0 B0
CI1 A1 B1
CI2 A2 B2
END dobl_tri_buf8;
4
ARCHITECTURE rtl OF dobl_ tri_buf8 IS SIGNAL aout, bout:STD_LOGIC_VECTOR (7 DOWN TO 0 ); BEGIN P1: PROCESS (a, dir, en) BEGIN IF ((en='0') AND (dir='1')) THEN bout <= a; ELSE bout <="ZZZZZZZZ"; END IF; b <= bout; END PROCESS P1;
ci cout
ARCHITECTURE rtl OF full_adder IS
BEGIN
sum <= a XOR b XOR ci；
cout <= (a AND b) OR (a AND ci ) OR ( b AND ci)；
END rtl;
10
4位串行进位加法器
CI A0 B0
A1 B1
A2 B2
BCD码输入与LED显示器字段的对应关系
Fra Baidu bibliotek
BCD码 数字 显 示 段
hgfedcba
0000 0 1 1 0 0 0 0 0 0
0001 1 1 1 1 1 1 0 0 1
0010 2 1 0 1 0 0 1 0 0
0011 3 1 0 1 1 0 0 0 0
0100 4 1 0 0 1 1 0 0 1
进位产生逻辑
SUM CI A B
9
4.1.4 运算器的设计
一位全加器的设计.
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; ENTITY full_adder IS
a sum
PORT (a, b, ci: IN STD_LOGIC;
b
sum, cout： OUT STD_LOGIC); END full_adder;
1 X 高阻态
0 0 a<=b
en
0 1 b<=a
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY dobl_tri_buf8 IS
PORT (a, b:INOUT STD_LOGIC_VECTOR (7 DOWN TO 0); dir, en：IN STD_LOGIC);