05_ARM CortexM3中断处理

345v05
5
Interrupt Entry Timing
1 CLK 2 3 4 5 6 7 8 9 10 11 12 13 14 15 INTISR[2]
HADDRS[31:0]
SP + 18 SP +1 C SP +0
SP + 4
SP+ 8
SP + C
SP+10 SP+14
HWDATAS[31:0]
01
02
ETMINSTAT [2:0]
000
010
100
001
ETMINTNUM[8:0]
17
18
345v05
11
Interrupt Response - Preemption
IRQ1 Highest IRQ2
Traditional Interrupt Handling Must Complete Stack Cycle
In parallel, Interrupt Service Routine (ISR) is prefetched on the instruction bus

ISR ready to start executing as soon as stack push is complete

Late arriving interrupt will restart ISR prefetch, but state saving does not need to be repeated
Follows AAPCS (ARM Architecture
Procedure Calling Standard)
xPSR PC LR R12 R3 R2 R1 R0
<-SP
345v05
8
Return From Interrupt

Normal Return from Interrupt instruction is BX LR
Assumes LR not corrupted during ISR Could use

LDR PC, ….. LDM/POP which includes loading the PC BX to another register

If no other interrupts are pending, the processor state is automatically restored from the stack
LDM/STM, PUSH/POP, DIV, MUL may be interrupted for better interrupt latency LDM/STM, PUSH/POP will normally be continued upon return from interrupt
10
Tail Chaining Timing Diagram
CLK
INTISR [2 ]
HADDRI [31:0]
0 x48 Last instruction fetch of ISR (BX LR)
0x100 0 x104 0 x108
HRDATAI [31:0]
0x100
CURRPRI [7:0]
345v05
7
Interrupt Stack

Cortex-M3 stack at start of ISR
Following automatic stacking of
registers by core
<previous>
<-SP <- Old SP

Stack Pointer is automatically decremented Cortex-M3 stack is Full-Descending Saving these registers allows ISRs to be written in C/C++
CURRPRI[7:0]
ETMINSTAT[2:0]
000
100
001
000
ETMINTNUM[8:0]
18
18
345v05
6
Interrupt Entry

Upon receiving an interrupt, the processor will finish current instruction
SP+18 SP +1C SP+ 0 SP+4
SP+8
SP+C SP +10 SP+ 14
HWDATAS[31:0 ]
PC xPSR r 0
r1
r2
r3
r12
LR
HADDRI [31:0 ]
48
100 104 108
60
500 504
64
600 604 608
HRDATAI [31:0 ]
100 Fetch of ISR6
Cortex-M3
345v05 3
“Micro-Coded” Interrupt Mechanism

Interrupt structure designed for low latency
Interrupt prioritization mechanism is part of Cortex-M3
Then, processor state automatically saved to the stack over the data bus

{PC, R0-R3, R12, R14, xPSR} Follows AAPCS (ARM Architecture Procedure Calling Standard)
Interrupt Controller (NVIC) is tightly coupled with processor core Interrupt inputs are active HIGH
INTNMI 1-240 Interrupts INTISR[239:0] NVIC
…
Cortex-M3 Processor Core

Must still fetch new vector and refill pipeline
345v05 9
Interrupt Response – Tail Chaining
Interrupt handling in assembler code
Interrupt handling in hardware (Cortex-M3)
LDM/STM and PUSH/POP instructions are interruptible and continuable DIV and long MUL instructions will be cancelled, then restarted later
345v05
4
Agenda
Interrupt routine
Pop
16 cycles
Push
26 cycles
Interrupt routine
Tail-chaining Cortex-M3 May Abandon Stack Operations Dynamically Interrupt routine Pop Interrupt routine
Cortex-M3 Interrupts
1
Agenda

Basic Interrupt Operation Interrupt Entry/Exit Interrupt Registers Interrupt Prioritization Interrupt Implementation Configurability Interrupt Handlers
345v05
2
Cortex-M3 Interrupts

One Non-Maskable Interrupt (INTNMI) supported
1-240 prioritizable, maskable interrupts supported
Implementation option selects number of interrupts supported
Cortex-M3 12 cycles from IRQ1 [ ISR1 entered
12 cycles if LSM 6 cycles from ISR1 exit [ ISR2 entry 12 cycles to return ISR2 [ return code
345v05
百度文库345v05
12
Late Preemption Timing Diagram
1 CLK 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 INTISR[2 ]
INTISR[8 ]
INTISR[9 ]
HADDRS [31:0 ]
processor state (tail-chaining)
Interrupt Service Routines (ISRs) can be written entirely in C

Long instructions are interruptible for improved interrupt latency
PC
xPSR
r0
r1
r2
r3
r 12
LR
HADDRI[31:0]
0x48
0x100
0x104
0x108
HRDATAI[31:0]
0x100 ISR fetch Handler fetch 2 Twelve- cycle ISR entry latency First ISR instruction in Execute stage
1-12 cycles 6 cycles
ARM7
Load Multiple uninterruptible, and hence the core must complete the POP and then full stack PUSH
Cortex-M3
POP may be abandoned early if another interrupt arrives If POP is interrupted it only takes 6 cycles to enter ISR2 (equivalent to Tailchaining)
12 cycles
ARM7 26 cycles from IRQ1 [ ISR1 entered up to 42 cycles if LSM
42 cycles from ISR1 exit [ ISR2 entry 16 cycles to return from ISR2 [ return code
Processor state saved/restored by core on interrupt entry/return Interrupt entry/exit is “micro-coded”
No instruction overhead Allows late determination of highest priority pending interrupt Allows another pending interrupt to be serviced without a full restore/save of
Basic Interrupt Operation

Interrupt Entry/Exit Interrupt Registers Interrupt Prioritization Interrupt Implementation Configurability Interrupt Handlers
If other interrupts are pending, the ISR of the highest priority pending interrupt is
started (Tail-Chaining)

In parallel, interrupted instruction is prefetched to be ready for execution upon completion of stack restore Stack restore can be interrupted, allowing new ISR to be immediately executed without the overhead of state saving