非常详细的静态时序分析教程

Clk
0
100
Data
Early Required Time
Late Required Time
Renjini
Limitations of STA
STA
• Works best with synchronous (not asynchronous) logic • Complex to learn • Must define timing requirements / exceptions • Difficulty in handling:
A node exists for every
Model pin
4
Cell Pin
8
Hierarchical pin
2
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14
Renjini
STA - Node Types
Top Data Clk
DQ QB
Simplifying assumptions:
One number for rise and fall Input arrival time of 1 Wire delay 0.2 ; gate delay 0.5
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Renjini
Comparing STA and DTA
STA
• Automatically
exhaustive in nature.
• Does not require a
vector set.
• More efficient than
DTA in memory and CPU resources.
Renjini
STA - Events
STA
At each node is a group of events modeling signal transitions
DQ
AT RT
QB
SLEW
Arrival Time (AT) - when the signal arrives Required Time (RT) - when the signal is needed Slew (SLEW) - time for signal transition from logic levels
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• Require an exhaustive set
of vectors to test all possibilities.
• Mixes functional and
timing problems together, may be difficult to discern the true cause of failure.
Output OutputBar
STASTA
Data Nodes
Clock Nodes All nodes along clock path Created from “force clock constraints”
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HINT: Timing Levels = 2 * Logic Levels + 2
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Renjini
STA - Calculating AT
1 1.0
1 1.0
1 1.0 1 1.0
1 1.0
1.2 2
Renjini
STA – What is Static Timing Analysis?
STA
Data Clk
DQ QB
Output OutputBar
What are our circuit timing requirements?
Clk 0
Data
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STA
STA is an exhaustive method of analyzing, debugging and validating the timing performance of a design.
Advantages:
• Much faster than timing-driven, gate-level
STA
9 10 3.8 4.0
Renjini
STA - Calculating RT
1 1.2 1.0
1.4 1.2
1.9
2 2.4
1 0.5 1.0
0.7 1.2
2
3
5 2.1
2.6 4 1.9
8 9
1
-0.2 1.0
1
-0.2 1.0
0.0 2 1.2
0.0 1.2
1
2
1.0 0.5
1.7
1.2
data is not available.
• Also, early mode timing is not available!
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Renjini
STA - Meeting Timing
STA
Q. Am I meeting late mode timing at this node?
• Multiple clocks
• False paths
• Latches
• Multicycle paths
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Renjini
What is Dynamic Timing Analysis ?
STA
Place and Route
Parasitic Extraction
SDF
(extracted parasitics)
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Renjini
STA
The Timing Graph
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3
1Leabharlann Baidu7
2 1.2
1.7 3
1.2 2
4 1.9
2 1.2
1.2 2 2.4
5
2.6 4 1.9
8 9
4 1.9 7
5
6 2.6
2.4
3.1 3.3
STEP 1 : Calculate timing level for each node
STEP 2 : Calculate AT from level 1 to level n
- Static timing with latches (Time borrowing)
- Limits
- Minimum delay
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Renjini
STA – What is Static Timing Analysis?
• Requires more memory
and CPU resources over STA.
Renjini
STA in ASIC Design Flow – Pre layout
STA
Constraints
(clocks, input drive, output load)
Static Timing Analysis
Concepts Covered
STA
• Static timing concepts • Understanding and describing clocks • Constraining a design • Issues that add complexity • Miscellaneous concepts:
Advantages
• Can be very accurate (spice-level)
Disadvantages:
• Analysis quality depends on stimulus vectors • Non-exhaustive, slow
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0.5
1.7 3
4
0.7 1.9
2 1.2
1.4 1.4
4 1.9 7
3.1
5
6 2.6
1.9
2.4 1.4
1.2
3.3 2.1
Logic Synthesis Design For test
Floor planning
Static Timing Analysis (estimated parasitics)
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Renjini
STA in ASIC Design Flow – Post Layout
500
Data
Setup Requirement Hold Requirement
IBM’s Hitchcock (70’s) observed that you could exhaustively test all behaviors within a single clock cycle
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Renjini
STA - Levels
STA
Q. How many levels of logic are in this design?
5
3
4
1 21
2
3
4
67 8
9 10
Q. How many timing levels are in this design?
HINT: Determine the nodes first
Renjini
STA - Timing Graph Introduction
STA
Node: where timing information is stored on the design
Top Data Clk
DQ QB
Output OutputBar
Bottom
Q. How many nodes are in our design?
simulation.
• Exhaustive • Proper circuit functionality is not checked. • Vector generation NOT required.
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STA
Constraints
(clocks, input drive, output load)
Floor planning Clock Tree Synthesis
Static Timing Analysis (estimated parasitics)
Static Timing Analysis (extracted parasitics)
100
200
300
400
500
Setup Requirement Hold Requirement
Data Cannot Change Within These Windows
Renjini
STA – What is Static Timing Analysis?
STA
Clk
0
100
200
300
400
SLACK = RT - AT
AT +SLACK RT
RT
AT
-SLACK
No, the falling edge slack is negative... HINT: RT should always be after AT
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Renjini
STA - Meeting Timing
STA
Q. Am I meeting timing at this node?
AT +SLACK RT
SLEW
SLACK = RT - AT
• Timing is met when slack is greater than or equal to zero • Timing at this node is undetermined, as the falling event