RISC简易指令流水线操作

Jump & Link
PCSrc RegWrite
Asanovic/Devadas Spring 2002 6.823
MemWrite
WBSrc ALU / Mem / PC
Add Add clk we clk
PC
addr inst ALU GPRs Imm Ext Inst. Memory
clk
* *
Hardwired Unpipelined Machine
Simple One instruction per cycle Why wasn’t this a popular machine style?
Asanovic/Devadas Spring 2002 6.823
Unpipelined DLX
Load/Store Instructions:
Harvard-Style Datapath
RegWrite clk Add we addr inst GPRs clk Inst. Memory Imm Ext ALU Control ALU clk we addr rdata Data Memory wdata MemWrite
OpSel
BSrc
zero?
Hardwired Control is pureCombinational Logic:
Unpipelined DLX
ExtSel BSrc OpSel MemWrite WBSrc RegDst RegWrite PCSrc
Asanovic/Devadas Spring 2002 6.823
op code zero?
combinational logic
ALU Control & Immediate Extension
Inst<5:0> (Func) Inst<31:26> (Opcode)
Asanovic/Devadas Spring 2002 6.823
ALUop
OpSel ( Func, Op, +, 0? )
RegDst= rf2 / rf3 /
Reg Dest rf3 rf3 rf2 rf2 rf2 * * * * R31 * R31
PC Src ~j ~j ~j ~j ~j ~j PCR ~j PCR PCR Rlnd Rlnd
sExt16 uExt16 sExt16 sExt16 sExt16 sExt16 sExt26 sExt26
Asanovic/Devadas Spring 2002 6.823
Harvard style: separate (Aiken and Mark 1 influence) - read-only program memory - read/write data memory at some level the two memories have to be the same Princeton style: the same (von Neumann’s influence) - A Load or Store instruction requires accessing the memory more than once during its execution
Decode Map
ExtSel ( sExt16, uExt16, sExt26,High16)
Hardwired Control worksheet
PCSrc PCR / RInd / ~j RegWrite MemWrite
Asanovic/Devadas Spring 2002 6.823
ALU Control
we addr rdata Data Memory wdata
ExtSel OpCode RegDst rf3 / rf2 / R31
OpSel
BSrc
zero?
PC-Relative Jumps
PCSrc RegWrite
Asanovic/Devadas Spring 2002 6.823
WBSrc
Add Add clk we clk
PC
addr inst ALU GPRs Imm Ext ALU Control Inst. Memory
Байду номын сангаас
clk
we addr rdata Data Memory wdata
Jump & Link?
OpCode RegDst ExtSel OpSel BSrc zero?
WBSrc ALU / Mem / PC
Add Add Add
we
PC
addr inst ALU GPRs Imm Ext ALU Control BSrc Reg / Imm OpCode RegDst rf3 / rf2 / R31 ExtSel OpSel sExt16/uExt16/ Func/ sExt26/High16 Op/+/0? zero? Inst. Memory we addr rdata Data Memory wdata
PCSrc ( ~j / j )
Conditional Branches
RegWrite
Asanovic/Devadas Spring 2002 6.823
MemWrite
WBSrc
Add Add clk we clk
PC
addr inst ALU GPRs Imm Ext ALU Control Inst. Memory
A Simple Memory Model
WriteEnable Clock Address WriteData
Asanovic/Devadas Spring 2002 6.823
MAGIC RAM
ReadData
Reads and writes are always completed in one cycle a Read can be done any time (i.e. combinational) a Write is performed at the rising clock edge if it is enabled ⇒ the write address, data, and enable must be stable at the clock edge
Proc 0.5-2ns <10ns 2-3 clk 5~15 clk 8~64KB 0.25-2MB
< 25ns 15~50 clk 1~8MB
~150ns 100~300 clk 64M~1GB
~10ms seek time ~107 clk 20~100GB
Our memory model is a good approximation of the hierarchical memory system when we hit in the on-chip cache
Asanovic/Devadas Spring 2002 6.823
Simple Instruction Pipelining
Krste Asanovic Laboratory for Computer Science Massachusetts Institute of Technology
Processor Performance Equation
Asanovic/Devadas Spring 2002 6.823
WBSrc= ALU / Mem / PC PCSrc2 = PCR / RInd
Op Sel Func Func Op Op + + 0? 0? * * * * Mem Write no no no no no yes no no no no no no Reg Write yes yes yes yes yes no no no no yes no yes WB Src ALU ALU ALU ALU Mem * * * * PC * PC
Asanovic/Devadas Spring 2002 6.823
Time = Instructions * Cycles * Time Program Program Instruction Cycle
Instructions per program depends on source code, compiler technology, and ISA Microcoded DLX from last lecture had cycles per instruction (CPI) of around 7 minimum Time per cycle for microcoded DLX fixed by microcode cycle time
Asanovic/Devadas Spring 2002 6.823
Clock period must be sufficiently long for all of the following steps to be “completed”:
clk
Hardwired Control Table
BSrc= Reg / Imm R31 PCSrc1 = j / ~j
Opcode ALU ALUu ALUi ALUiu LW SW BEQZz=0 BEQZz=1 J JAL JR JALR Ext Sel * * BSrc Reg Reg Imm Imm Imm Imm * * * * * *
Memory Hierarchy c.2002
Desktop & Small Server
Asanovic/Devadas Spring 2002 6.823
On-chip Caches
Off-chip L3 Cache SRAM/ eDRAM Interleaved Banks of DRAM
Hard Disk
ExtSel
OpSel
BSrc Reg / Imm
func OpCode immediate
rf3 ← (rf1) func (rf2) rf2 ← (rf1) op immediate
Datapath for Memory Instructions
Should program and data memory be separate?
Asanovic/Devadas Spring 2002 6.823
WBSrc ALU / Mem
PC
OpCode RegDst
ExtSel
OpSel
BSrc
OpCode
displacement
addressing mode (rf1) + displacement
rf1 is the base register rf2 is the destination of a Load or the source for a Store
— mostly ROM access + next µPC select logic
Pipelined DLX
To pipeline DLX: First build unpipelined DLX with CPI=1
Asanovic/Devadas Spring 2002 6.823
Next, add pipeline registers to reduce cycle time while maintaining CPI=1
MemWrite
WBSrc ALU / Mem / PC
Add Add clk we clk
PC
addr inst ALU GPRs Imm Ext Inst. Memory we addr rdata Data Memory wdata
clk
ALU Control
ExtSel OpCode RegDst rf3 / rf2 / R31
Datapath for ALU Instructions
Add RegWrite clk we
PC
Asanovic/Devadas Spring 2002 6.823
addr inst ALU GPRs Imm Ext ALU Control
clk
Inst. Memory
OpCode
RegDst rf2 / rf3
clk
we addr rdata Data Memory wdata
OpCode RegDst
ExtSel
OpSel
BSrc
zero?
PCSrc ( ~j / j )
Register-Indirect Jumps
RegWrite MemWrite
Asanovic/Devadas Spring 2002 6.823