八位16进制、八位10进制频率计设计
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EDA综合实习报告一
李爱20111154006 电子科学与技术2011级
1.数字频率计的设计
（1）8位16进制频率计
①．主程序：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY MAIN IS
PORT (A,clk1,CLK: IN STD_LOGIC;
O:OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
P: OUT STD_LOGIC_VECTOR(6 DOWNTO 0));
END;
ARCHITECTURE HEAD OF MAIN IS
COMPONENT CEPIN
PORT (CLK1:IN STD_LOGIC;
CNT: OUT STD_LOGIC;
RST:OUT STD_LOGIC;
LOAD:OUT STD_LOGIC);
END COMPONENT;
COMPONENT JISHU
PORT (CLR:IN STD_LOGIC;
EN:IN STD_LOGIC;
FIN:IN STD_LOGIC;
COUT:OUT STD_LOGIC_VECTOR(31 DOWNTO 0) );
END COMPONENT;
COMPONENT SUOCUN
PORT( LK :IN STD_LOGIC;
DIN:IN STD_LOGIC_VECTOR (31 DOWNTO 0);
QDOUT: OUT STD_LOGIC_VECTOR (31 DOWNTO 0));
END COMPONENT;
COMPONENT XIANSHI
PORT (clk: in std_logic;
Q:IN STD_LOGIC_VECTOR(31 DOWNTO 0);
T:buffer STD_LOGIC_VECTOR(2 DOWNTO 0);
Y:OUT STD_LOGIC_VECTOR(6 DOWNTO 0));
END COMPONENT;
SIGNAL NET1,NET2,NET3:STD_LOGIC;
SIGNAL NET4,NET5 :STD_LOGIC_VECTOR(31 DOWNTO 0);
BEGIN
U1:CEPIN PORT MAP (CLK1=>CLK,CNT=>NET1,RST=>NET2,LOAD=>NET3);
U2:JISHU PORT MAP (CLR=>NET2,EN=>NET1,FIN=>A,COUT=>NET4);
U3:SUOCUN PORT MAP (LK=>NET3,DIN=>NET4,QDOUT=>NET5);
U4:XIANSHI PORT MAP (clk=>clk1,Q=>NET5,Y=>P,T=>O);
END HEAD;
②．测频
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY cepin IS
PORT (CLK1:IN STD_LOGIC;
CNT: OUT STD_LOGIC;
RST:OUT STD_LOGIC;
LOAD:OUT STD_LOGIC);
END ;
ARCHITECTURE one OF cepin IS
SIGNAL M: STD_LOGIC;
BEGIN
PROCESS (CLK1)
BEGIN
IF CLK1 'EVENT AND CLK1='1' THEN
M<= NOT M;
END IF;
END PROCESS;
PROCESS (CLK1,M)
BEGIN
IF CLK1='0' AND M='0' THEN RST<='1';
ELSE RST <='0';
END IF;
END PROCESS;
LOAD <= NOT M;
CNT <=M;
END one;
③．计数
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY JISHU IS
PORT (CLR:IN STD_LOGIC;
EN:IN STD_LOGIC;
FIN:IN STD_LOGIC;
COUT:OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END ;
ARCHITECTURE two OF JISHU IS
SIGNAL Q: STD_LOGIC_VECTOR(31 DOWNTO 0);
BEGIN
PROCESS (CLR,EN,FIN) BEGIN
IF CLR='1' THEN Q <= (OTHERS=>'0');
ELSIF FIN 'EVENT AND FIN='1' THEN
IF EN='1' THEN Q <= Q+1;
END IF;
END IF;
END PROCESS;
COUT <=Q;
END two;
④．锁存
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY SUOCUN IS
PORT( LK :IN STD_LOGIC;
DIN:IN STD_LOGIC_VECTOR (31 DOWNTO 0);
qDOUT: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)); END ;
ARCHITECTURE three OF SUOCUN IS
BEGIN
PROCESS (LK,DIN)
BEGIN
IF LK 'EVENT AND LK='1' THEN qDOUT <=DIN;
END IF;
END PROCESS;
END three;