硅片行业术语大全
- 1、下载文档前请自行甄别文档内容的完整性,平台不提供额外的编辑、内容补充、找答案等附加服务。
- 2、"仅部分预览"的文档,不可在线预览部分如存在完整性等问题,可反馈申请退款(可完整预览的文档不适用该条件!)。
- 3、如文档侵犯您的权益,请联系客服反馈,我们会尽快为您处理(人工客服工作时间:9:00-18:30)。
硅片行业术语大全(中英文对照A-H)
Acceptor - An element, such as boron, indium, and gallium used to create a free hole in a semiconductor. The acceptor atoms are required to have one less valence electron than the semiconductor.
受主- 一种用来在半导体中形成空穴的元素,比如硼、铟和镓。受主原子必须比半导体元素少一价电子
Alignment Precision - Displacement of patterns that occurs during the photolithography process.
套准精度- 在光刻工艺中转移图形的精度。
Anisotropic - A process of etching that has very little or no undercutting
各向异性- 在蚀刻过程中,只做少量或不做侧向凹刻。
Area Contamination - Any foreign particles or material that are found on the surface of a wafer. This is viewed as discolored or smudged, and it is the result of stains, fingerprints, water spots, etc.
沾污区域- 任何在晶圆片表面的外来粒子或物质。由沾污、手印和水滴产生的污染。
Azimuth, in Ellipsometry - The angle measured between the plane of incidence and the major axis of the ellipse.
椭圆方位角- 测量入射面和主晶轴之间的角度。
Backside - The bottom surface of a silicon wafer. (Note: This term is not preferred; instead, use …back surface‟.)
背面- 晶圆片的底部表面。(注:不推荐该术语,建议使用“背部表面”)
Base Silicon Layer - The silicon wafer that is located underneath the insulator layer, which supports the silicon film on top of the wafer.
底部硅层- 在绝缘层下部的晶圆片,是顶部硅层的基础。
Bipolar - Transistors that are able to use both holes and electrons as charge carriers.
双极晶体管- 能够采用空穴和电子传导电荷的晶体管。
Bonded Wafers - Two silicon wafers that have been bonded together by silicon dioxide, which acts as an insulating layer.
绑定晶圆片- 两个晶圆片通过二氧化硅层结合到一起,作为绝缘层。
Bonding Interface - The area where the bonding of two wafers occurs.
绑定面- 两个晶圆片结合的接触区。
Buried Layer - A path of low resistance for a current moving in a device. Many of these dopants are antimony and arsenic.
埋层- 为了电路电流流动而形成的低电阻路径,搀杂剂是锑和砷。
Buried Oxide Layer (BOX) - The layer that insulates between the two wafers.
氧化埋层(BOX) - 在两个晶圆片间的绝缘层。
Carrier - Valence holes and conduction electrons that are capable of carrying a charge through a solid surface in a silicon wafer.
载流子- 晶圆片中用来传导电流的空穴或电子。
Chemical-Mechanical Polish (CMP) - A process of flattening and polishing wafers that utilizes both chemical removal and mechanical buffing. It is used during the fabrication process.
化学-机械抛光(CMP) - 平整和抛光晶圆片的工艺,采用化学移除和机械抛光两种方式。此工艺在前道工艺中使用。
Chuck Mark - A mark found on either surface of a wafer, caused by either a robotic end effector, a chuck, or a wand.
卡盘痕迹- 在晶圆片任意表面发现的由机械手、卡盘或托盘造成的痕迹。
Cleavage Plane - A fracture plane that is preferred.
解理面- 破裂面
Crack - A mark found on a wafer that is greater than 0.25 mm in length.
裂纹- 长度大于0.25毫米的晶圆片表面微痕。
Crater - Visible under diffused illumination, a surface imperfection on a wafer that can be distinguished individually.
微坑- 在扩散照明下可见的,晶圆片表面可区分的缺陷。
Conductivity (electrical) - A measurement of how easily charge carriers can flow throughout a material.
传导性(电学方面)- 一种关于载流子通过物质难易度的测量指标。
Conductivity Type - The type of charge carriers in a wafer, such as “N-type” and “P-type”.