verilog语法练习

1,八位数据通路控制器

`define ON 1‟b1

`define OFF 1‟b0

wire controlswitch;

wire [7:0] in out;

assign out = (controlswitch == `ON) ? in : 8‟h00;

2,数据在寄存器中的暂时保存

module reg8(en ,clk, data,rst,out);

input en,clk,rst;

input [7:0] data;

output [7:0] out;

reg [7:0] out;

always @ (posedge clk)

begin

if(!rst)

out <= 0

else if (en)

out <= data;

else

out <= 8‟h00;

end

endmodule

3,状态机

module fsm(clk,rst,a,k1,k2);

input clk,rst,a;

output k1,k2;

reg k1,k2;

reg state;

parameteter Idle = 2‟b00, Start = 2‟b01, Stop = 2‟b10, Clear = 2‟b11; always @ (posedge clk)

begin

if (!rst)

begin

state <= Idle;

k2 <= 0;

k1 <= 0;

end

else

case (state)

Idle: begin

If(a) begin

state <= Start;

k1 <= 0;

end

else

state <= Idle;

end

Start : begin

If(!a)

state <= Stop;

else

state <= Start;

end

Stop ：begin

If (a)

Begin

state <= Clear;

k2 <= 1;

end

else state <= Stop;

end

Clear : begin

If (!a)

begin

state <= Idle;

k2 <= 0;

k1 <= 1;

end

else

state <= Clear;

end

endcase

endmodule

4,组合逻辑电路设计实例

8位带进位端的加法器的设计实例module adder_8 (cout, sum, a,b,cin); output [7:0] sum;

output cout;

input [7:0] a;

input cin;

assign {cout,sum} = a+b+cin;

endmodule

5,指令译码电路的设计实现（利用电平敏感的always快来设计组合逻辑）。

//操做码的宏定义

`define plus 3‟d0

`define minus 3‟d1

`define band 3‟d2

`define bor 3‟d3

`define unegate 3‟d4

module alu (out, opcode,a,b);

output [7:0] out;

input [2:0] opcode;

input [7:0] a,b;

reg [7:0] out;

always @ (opcode or a or b)

begin

case(opcode)

//算术运算

`plus : out = a+b;

`minus : out = a-b;

//位运算

`band : out =a&b;

`bor ：out =a|b;

//单目运算

`unegate out=~a;

default: out= 8‟hx;

endcase

end

endmodule

6,利用task和电平敏感的always块设计比较后重组信号的组合逻辑

module sort4(ra,rb,rc,rd,a,b,c,d);

parameter t = 3;

output [t:0] ra,rb,rc,rd;

input [t:0] a,b,c,d;

reg [t:0] ra,rb,rc,rd;

always @ (a or b or c or d)

//用电平敏感的always块描述组合逻辑

begin

reg [t:0] va,vb,vc,vd;

{va,vb,vc,cd}={a,b,c,d};

sort2(va,vc);

sort2(va,vb);

sort2(vc,vd);

sort2(vb,vc);

{ra,rb,rc.rd}={va,vb,vc,vd};

end

task sort2;.

inout [t:0] x,y;

reg [t:0] temp;

if (x>y)

begin

tmp = x;

x = y;

y = tmp;

end

endtask

endmodule

7,比较器的设计实例（利用赋值语句设计组合逻辑电路）

module compare (equal,a,b);

output equal;

input a,b;

assign equal = (a==b)?1:0;

endmodule

8,3-8译码器设计实例（利用赋值语句设计组合逻辑）

module decoder(out,in);

output [7:0] out;

input [2:0] in;

assign out = 1‟b1<

/*把最低位的1左移in（根据从in端口输入的值）位，并赋予out*/ endmodule

9,8-3编码器的设计实例

module encoder1(none_on,out,in);

output none_on;

output [2:0] out;

input [7:0] in;

reg [2:0] out;

reg none_on;

always @ (in)

begin :

local integer i;

out = 0;

none_on = 1;

/* returns the value of the highest bit number turned on*/

for (i= 0; i<8; i=i+1)