FPGA数字钟源代码
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module shuzizhong
(
input clk_in, // system clock
input rst_n_in, // system reset, active low
inout one_wire, // ds18b20z one-wire-bus
output rclk_out, // 74HC595 RCK
output sclk_out, // 74HC595 SCK
output sdio_out, // 74HC595 SER
input key3,
input key4,
input hold
//output reg [8:0] seg_led_1,
//output reg [8:0] seg_led_2
);
reg clk_divided;
reg hold_flag;
reg [3:0] flag1 ;
reg [3:0] flag2;
reg [3:0] flag3;
reg back_to_zero_flag = 0;
reg [6:0] seg [9:0];
reg [23:0] cnt;
reg [3:0] cnt_ge;
reg [3:0] ge;
reg [3:0] cnt_shi;
reg [3:0] shi;
reg [3:0] bai1;
reg [3:0] bai2;
reg [3:0] qian1 =0 ;
reg [3:0] qian2 ;
reg [3:0] cnt_bai_1 = 0;
reg [3:0] cnt_bai_2 = 0;
reg [3:0] cnt_qian_1 = 0;
reg [3:0] cnt_qian_2 = 0;
parameter PERIOD=6000000;
always @ (posedge clk_in) begin
if (!rst_n_in == 1) begin
cnt <= 0;
clk_divided <= 0; end
else begin
if (cnt < PERIOD-1)
cnt <= cnt + 1;
else begin
cnt <= 0;
clk_divided <= ~clk_divided; end
end
end
always @ (*) begin
if (!rst_n_in == 1)
back_to_zero_flag <= 1;
else if (((cnt_shi*10) + cnt_ge)==61)
back_to_zero_flag <= 1;
else
back_to_zero_flag <= 0;
end
always @ (posedge hold)
hold_flag <= ~hold_flag;
always @ (posedge key3)
begin
flag1 <= flag1 + 1;
if(flag1>=6)
flag1<=0;
end
always @ (posedge key4)
flag2 <= ~flag2;
always @ (posedge flag2)
begin
case(flag1)
3'd0: begin
ge <= ge +1;
if(ge >= 9)
ge <= 0;
end
3'd1: begin
shi <= shi +1;
if(shi >= 9)
shi <= 0;
end
3'd2: begin
bai1 <= bai1 +1;
if(bai1 >= 9)
bai1 <= 0;
end
3'd3: begin
bai2 <= bai2 +1;
if(bai2 >= 9)
bai2 <= 0;
end
3'd4: begin
qian2 <= qian2 +1;
if(qian2 >= 9)
qian2 <= 0;
end
3'd5: begin
qian1 <= qian1 +1;
if(qian1 >= 9)
qian1 <= 0;
end
endcase
end
/* shi = shi + 1;
if(shi >= 6)
shi <= 0;*/
//end
always @ (posedge clk_divided or posedge back_to_zero_flag) begin if (back_to_zero_flag == 1) begin
cnt_ge <= 0;
cnt_shi <= 0; end
else if(cnt_qian_1 >= 9) begin
cnt_qian_2 <= cnt_qian_2 + 1;
cnt_qian_1 <= 0;
end
else if(cnt_bai_2 >= 6) begin
cnt_bai_2 <= 0;
cnt_qian_1 <= cnt_qian_1 + 1;
end
else if(cnt_bai_1 >= 6 ) begin
cnt_bai_1 <= 0;
cnt_bai_2 <= cnt_bai_2 + 1;
end
else if(cnt_shi >= 5 && cnt_ge >= 9 ) begin
cnt_bai_1 <= cnt_bai_1 + 1;
cnt_shi <= 0;
cnt_ge <= 0;
end
else if (cnt_ge >= 9) begin
cnt_ge <= 0;
cnt_shi <= cnt_shi + 1; end
else if (hold_flag == 1)
begin
cnt_ge <= ge;
cnt_shi <= shi;
cnt_bai_1 <= bai1;
cnt_bai_2 <= bai2;
cnt_qian_1 <= qian1;
cnt_qian_2 <= qian2;
end
else
cnt_ge <= cnt_ge + 1;
end
wire [5:0] seg_data_en;
assign seg_data_en[5:0] = 6'b111111;
Segment_scan Segment_scan_uut
(
.clk_in (clk_in ), //system clock, 12mhz .rst_n_in (rst_n_in ), //active with low