实验三--8-3优先编码器和3-8线译码器
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实验三 8-3优先编码器和3-8线译码器
一、实验目的
1、熟悉常用编码器，译码器的功能逻辑。
2、熟悉VHDL的代码编写方法。
3、掌握复杂译码器的设计方法。
二、实验原理
2、逻辑表达式：
Y2=X4&X5&X6&X7
Y1=~(~(X2)&X4&X5|~(X3)&X4&X5|~(X6)|~(X7));
Y0=~(~(X1)&x2&X4&X6|~(X3)&X4&X6|~(X5)&X6|~(X7));
2、3-8线码器
总体思路以EP2C5中的三个拨位开关，SW3，SW2,SW1为三个输入信号，可以代表8种不同的状态，该译码器对这8种状态译码，并把所译码的结果在七段LED数码管上显示出来。
三、实验连线
1、将EP2C5适配板左下角的JTAG用十芯排线和万用下载区左下角的SOPC JTAG 口连
接起来，万用下载区右下角的电源开关拨到 SOPC下载的一边
2、请将JPLED1短路帽右插，JPLED的短路帽全部上插。
3、请将JP103的短路帽全部插上。
四、实验步骤及波形
按照步骤三正确连线，参考实验二步骤，完成项目的建立，文件的命名，文件的编辑，语法检查，引脚分配，编译，下载。
8-3优先编码器参考代码：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY encode IS
PORT(XINA :IN STD_LOGIC_VECTOR(7 DOWNTO 0);
Y0,Y1,Y2: OUT STD_LOGIC;
OUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
LEDW: OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
);
END encode;
ARCHITECTURE ADO OF encode IS
SIGNAL LED: STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL XIN: STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
XIN<=XINA;
LEDW<="000";
PROCESS (XIN)
BEGIN
CASE XIN IS
WHEN x"00" => OUTA<=x"3F";
WHEN x"01" => OUTA<=x"06";
WHEN x"02" => OUTA<=x"5B";
WHEN x"04" => OUTA<=x"4F";
WHEN x"08" => OUTA<=x"66";
WHEN x"10" => OUTA<=x"6D";
WHEN x"20" => OUTA<=x"7D";
WHEN x"40" => OUTA<=x"07";
WHEN x"80" => OUTA<=x"3F";
WHEN OTHERS => OUTA<=x"3F";
END CASE;
END PROCESS;
PROCESS (XIN)
BEGIN
CASE XIN IS
WHEN x"01" => LED<="001";
WHEN x"02" => LED<="010";
WHEN x"04" => LED<="011";
WHEN x"08" => LED<="100";
WHEN x"10" => LED<="101";
WHEN x"20" => LED<="110";
WHEN x"40" => LED<="111";
WHEN x"80" => LED<="000";
WHEN OTHERS => LED<="000";
END CASE;
END PROCESS;
Y2<=LED(2);
Y1<=LED(1);
Y0<=LED(0);
END ADO;
3-8译码器参考代码：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY DECODE IS
PORT(DATA_IN :IN STD_LOGIC_VECTOR(2 DOWNTO 0);
LEDOUT,DATA_OUT :OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
LEDW :OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
);
END DECODE;
ARCHITECTURE ADO OF DECODE IS
SIGNAL OUTA,D_OUT : STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
LEDW<="000";
PROCESS (DATA_IN)
VARIABLE DIN: STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
DIN:=DATA_IN;
LEDOUT<=OUTA;
DATA_OUT<=D_OUT;
CASE DIN IS
when "000" => OUTA<="00111111" ; --"0"
when "001" => outa<="00000110" ; --"1"
when "010" => outa<="01011011"; --"2"
when "011" => outa<="01001111"; --"3"
when "100" => outa<="01100110"; --"4"
when "101" => outa<="01101101"; --"5"
when "110" => outa<="01111101"; --"6"
when "111" => outa<="00000111"; --"7"
WHEN OTHERS => OUTA<="XXXXXXXX";
END CASE;
CASE DIN IS
WHEN "000" => D_OUT<="00000000";
WHEN "001" => D_OUT<="00000001";
WHEN "010" => D_OUT<="00000010";
WHEN "011" => D_OUT<="00000100";
WHEN "100" => D_OUT<="00001000";
WHEN "101" => D_OUT<="00010000";
WHEN "110" => D_OUT<="00100000";
WHEN "111" => D_OUT<="01000000";
WHEN OTHERS=> D_OUT<="XXXXXXXX";
END CASE;
END PROCESS;
END ADO;
五、实验仿真
8-3编码器引脚锁定如图：
图5-1