浙大模拟与数模混合集成电路课件1
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(b) self-aligned structure.
10
The basic Silicon-gate CMOS process
Figure 1.6 The basic silicon-gate CMOS process
11
Figure 1.7 Typical N-well CMOS Process steps (8 Steps)
N+ N
N+
N+
Buried layer
Figure 1.10 Integrated-circuit NPN transistor. The mask layers are coded as shown.
Baidu Nhomakorabea16
Appendix:
A process from industry-BiCMOS
1 Zero Mask, ASM Align 2 Align.Keys Trench Etch/Laser 3 BL Mask 4 Iso Up Mask 14 N+ Source Mask 5 Ep 15 Shallow P+ Mask 6 P-Well Mask 7 Deep+Mask 8 Active(Composite)Mask 9 P-Field Mask 16 M1 Mask 17 M2 Mask 18 Passivation Mask 19 Electrical Test 10 VT Mask 11 Polysillicon Mask 12 P-Body Mask 13 N-Ext./LDD Mask
Analog & Mixed Signal Integrated Circuit
Wu Xiaobo Zhao Menglian
Chapter 1
INTRODUCTION OF CMOS PROCESS
——FROM TRANSISTOR TO DIE
2
Chip fabrication process
Thin Layer
c b Bottom Layer (b)
Figure 1.1 (a) Prepare to etch top layer; (b) Etching result demonstrates horizontal etching and bottom etching.
5
Photolithography
(d)
(e)
Figure 1.2 Layers comprising the structures
7
The basic silicon-gate NMOS process
Figure 1.3 The basic silicon-gate NMOS process
8
Channel stopper
Figure 1.4 (a) Unwanted conduction due to inversion of field area.
17
Appendix:
Submicron CMOS Circuit Design(1)
18
Appendix:
Submicron CMOS Circuit Design(2)
19
Thank you !
☺ FTP//10.212.43.214
(b) channel-stop implant
9
Self-aligned structure
n+
P-substrate (a)
n+
n+
P-substrate
n+
n+
P-substrate (b) P-substrate
n+
Figure 1.5 (a) Formation of n+ regions before deposition of poly,
12
Figure 1.9 Profile of CMOS Inverter Structure (a)P-Well Process ; (b)N-Well Process; (c)Two-Well Process
13
Figure 1.8 Side view of CMOS IC
14
15
Appendix: NPN transistor
- Manufacturing industry
3
Five basic processing steps
Oxidation (oxide growth) Diffusion Ion implantation Deposition Etching
4
Thin Layer
Bottom Layer (a) a
Cover wafer with photoresist Expose to UV light Etch Remove photoresist
•Negative photoresist •Positive photoresist
6
N-Well
Active
(a)
Poly
(b) Contact
(c)
Metal 1
10
The basic Silicon-gate CMOS process
Figure 1.6 The basic silicon-gate CMOS process
11
Figure 1.7 Typical N-well CMOS Process steps (8 Steps)
N+ N
N+
N+
Buried layer
Figure 1.10 Integrated-circuit NPN transistor. The mask layers are coded as shown.
Baidu Nhomakorabea16
Appendix:
A process from industry-BiCMOS
1 Zero Mask, ASM Align 2 Align.Keys Trench Etch/Laser 3 BL Mask 4 Iso Up Mask 14 N+ Source Mask 5 Ep 15 Shallow P+ Mask 6 P-Well Mask 7 Deep+Mask 8 Active(Composite)Mask 9 P-Field Mask 16 M1 Mask 17 M2 Mask 18 Passivation Mask 19 Electrical Test 10 VT Mask 11 Polysillicon Mask 12 P-Body Mask 13 N-Ext./LDD Mask
Analog & Mixed Signal Integrated Circuit
Wu Xiaobo Zhao Menglian
Chapter 1
INTRODUCTION OF CMOS PROCESS
——FROM TRANSISTOR TO DIE
2
Chip fabrication process
Thin Layer
c b Bottom Layer (b)
Figure 1.1 (a) Prepare to etch top layer; (b) Etching result demonstrates horizontal etching and bottom etching.
5
Photolithography
(d)
(e)
Figure 1.2 Layers comprising the structures
7
The basic silicon-gate NMOS process
Figure 1.3 The basic silicon-gate NMOS process
8
Channel stopper
Figure 1.4 (a) Unwanted conduction due to inversion of field area.
17
Appendix:
Submicron CMOS Circuit Design(1)
18
Appendix:
Submicron CMOS Circuit Design(2)
19
Thank you !
☺ FTP//10.212.43.214
(b) channel-stop implant
9
Self-aligned structure
n+
P-substrate (a)
n+
n+
P-substrate
n+
n+
P-substrate (b) P-substrate
n+
Figure 1.5 (a) Formation of n+ regions before deposition of poly,
12
Figure 1.9 Profile of CMOS Inverter Structure (a)P-Well Process ; (b)N-Well Process; (c)Two-Well Process
13
Figure 1.8 Side view of CMOS IC
14
15
Appendix: NPN transistor
- Manufacturing industry
3
Five basic processing steps
Oxidation (oxide growth) Diffusion Ion implantation Deposition Etching
4
Thin Layer
Bottom Layer (a) a
Cover wafer with photoresist Expose to UV light Etch Remove photoresist
•Negative photoresist •Positive photoresist
6
N-Well
Active
(a)
Poly
(b) Contact
(c)
Metal 1