K9F1G08X0A中文翻译文档
K9F1G08UOM数据手册
m A 5 5 15 15 1 10 10 20 20 1 µA 10 50 10 50
页 编 ICC2 程 擦除 ICC3 ISB1 等待状态电流 （TTL） 等待状态电流 （CMOS） 输入开漏电流 输出开漏电流
ISB2
IL1 IL0
-
-
±10 ±10
-
-
±10 ±10 VCC V +0.3 0.8 -
6． 命令/地址/ 数据复用端口： 7. 硬件数据保护：编程/擦除操作在电源转换时关闭。 8. 可靠的 CMOS 浮置门技术： --保证：100K 编程/ 擦除次数。 --数据保持时间: 10 年。 9. 命令寄存器操作 10. 为高速编程设置的缓冲编程操作。 11. 通电自动读操作。 12. 智能复制拷贝操作。 13．为防盗版而设置的唯一的 ID 保护。 14. 封装。 - K9F1GXXX0M-YCB0/YIB0 48 - Pin TSOP I (12 x 20 / 0.5 mm pitch) - K9F1G08U0M-VCB0/VIB0 48 - Pin WSOP I (12X17X0.7mm)
器件描述
三星 K9F1GXXX0M 提供了 128M*8Bit/64M*16Bit 的存储容量，另外还有 32 M 的空闲存储器，它是采用 NAND 技术的大容量、高可靠的 Flash 存储器。 它对 2112 字节一页（*8device ）或者 1056 字（*16device）一页的写操作。典型 时间是 300 微秒。对 128 字节／64K 字一块的擦除时间是 50 纳秒。输出引脚可 以作为数据／地址／命令复用。每一页的数据读出时间也很快，平均每个字节只 需 50 纳秒。片内的写控制器，可以自动执行写操作和擦除功能，包括必要的脉 冲产生器，内部校验和冗余数据。 K9F1G08 提供了实时映像算法的纠错码，写 操作系统可以利用 K9F1G08U0M 扩展的 100K 编程/ 擦除。K9F1G08U0M 为大 容量存储，新型电可擦写的非易失性半导体存储器，提供了最优方案。
K9W8G08U1M-YIB0资料
11
Vcc
12
Vss
13
N.C
14
N.C
15
CLE
16
ALE
17
WE
18
WP
19
N.C
20
N.C
21
N.C
22
N.C
23
N.C
24
48-pin TSOP1 Standard Type 12mm x 20mm
48
N.C
47
N.C
46
N.C
45
N.C
44
I/O7
43
I/O6
42
I/O5
41
I/O4
40
N.C
1
元器件交易网
K9W8G08U1M K9K4G08U0M
512M x 8 Bit / 1G x 8 Bit NAND Flash Memory
PRODUCT LIST
Part Number K9K4G08U0M-Y,P K9W8G08U1M-Y,P
Vcc Range 2.7 ~ 3.6V
3. Pb-free Package is added.
K9K4G08Q0M-PCB0,PIB0
K9K4G08U0M-PCB0,PIB0
K9K4G16U0M-PCB0,PIB0
K9K4G16Q0M-PCB0,PIB0
K9W8G08U1M-PCB0,PIB0
0.4
1. Added Addressing method for program operation.
2. The value of output load capacitance is changed.
3. EDO mode is added.
K9F2G08U0A 中文数据手册
(基准线 A)
A B C D (基准线 B) E F G H J K L M N
底视图
12.00±0.10 2.00 1.00 10.00 1.00
7 6 54 3 2 1
1.00
1.00
1.00
0.50
1.00
1.00
1.30
2.00 2.50 2.50
A B
0.65(最大)
12-∅1.00±0.05
42
I/O5
41
I/O4
40
N.C
39
N.C
38
N.C
37
Vcc
36
Vss
35
N.C
34
N.C
33
N.C
32
I/O3
31
I/O2
30
I/O1
29
I/O0
28
N.C
27
N.C
26
N.C
25
N.C
单位:毫米/英寸
0.10 0.004 最大
#48
0.008-+00..000013
+0.07 -0.03
)
0.25 0.010
修正历史
1. 首次发行
1. 增加1.8V 模块。 2. 定义tRHW参数, tCSD 参数。 3. 删除4G DDP LGA 部分。 4. 添加技术说明。(第18页)
1. FBGA 封装尺寸变化 2. 删除1.8V TSOP 封装方案
1. 1.8V Ioh/Iol (拉电流/灌电流)条件改变 2. 最小 tADL参数(@3.3 )范围改变为 70ns 到100ns
3
K9F2G08R0A K9F2G08U0A
MEMORY存储芯片K9F1G08U0B-PCB0中文规格书
Product IntroductionThe K9F1G08U0B is a 1,056Mbit(1,107,296,256 bit) memory organized as 65,536 rows(pages) by 2,112x8 columns. Spare 64x8 col-umns are located from column address of 2,048~2,111. A 2,112-byte data register is connected to memory cell arrays accommodat-ing data transfer between the I/O buffers and memory during page read and page program operations. The memory array is made up of 32 cells that are serially connected to form a NAND structure. Each of the 32 cells resides in a different page. A block consists of two NAND structured strings. A NAND structure consists of 32 cells. Total 1,081,344 NAND cells reside in a block. The program and read operations are executed on a page basis, while the erase operation is executed on a block basis. The memory array consists of 1,024 separately erasable 128K-byte blocks. It indicates that the bit by bit erase operation is prohibited on the K9F1G08U0B.The K9F1G08U0B has addresses multiplexed into 8 I/Os. This scheme dramatically reduces pin counts and allows system upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through I/O's by bringing WE to low while CE is low. Those are latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. Some commands require one bus cycle. For example, Reset Command, Status Read Command, etc require just one cycle bus. Some other commands, like page read and block erase and page program, require two cycles: one cycle for setup and the other cycle for execution. The 132M byte physical space requires 28 addresses, thereby requiring four cycles for addressing : 2 cycles of column address, 2 cycles of row address, in that order. Page Read and Page Program need the same four address cycles following the required command input. In Block Erase oper-ation, however, only the two row address cycles are used. Device operations are selected by writing specific commands into the com-mand register. Table 1 defines the specific commands of the K9F1G08U0B.In addition to the enhanced architecture and interface, the device incorporates copy-back program feature from one page to another page without need for transporting the data to and from the external buffer memory. Since the time-consuming serial access and data-input cycles are removed, system performance for solid-state disk application is significantly increased.Table 1. Command SetsNOTE : 1. Random Data Input/Output can be executed in a page.2. Read EDC Status is only available on Copy Back operation.Caution : Any undefined command inputs are prohibited except for above command set of Table 1.Function1st Cycle 2nd CycleAcceptable Command during BusyRead00h 30h Read for Copy Back 00h 35h Read ID 90h -Reset FFh -OPage Program 80h 10h Copy-Back Program 85h 10h Block Erase60h D0h Random Data Input (1)85h -Random Data Output (1)05h E0hRead Status 70h O Read EDC Status (2)7BhODC AND OPERATING CHARACTERISTICS (Recommended operating conditions otherwise noted.)NOTE : 1. V IL can undershoot to -0.4V and V IH can overshoot to V CC +0.4V for durations of 20 ns or less.2. Typical value is measured at Vcc=3.3V, T A =25°C. Not 100% tested.ParameterSymbol Test ConditionsK9F1G08U0B(3.3V)UnitMinTypMaxOperating CurrentPage Read with Serial Access I CC 1tRC=25nsCE=V IL, I OUT =0mA-1530mAProgram I CC 2-EraseI CC 3-Stand-by Current(TTL)I SB 1CE=V IH , WP=0V/V CC --1Stand-by Current(CMOS)I SB 2CE=V CC -0.2, WP=0V/V CC -1050µAInput Leakage Current I LI V IN =0 to Vcc(max)--±10Output Leakage Current I LO V OUT =0 to Vcc(max)--±10Input High VoltageV IH (1)-0.8xVcc -V CC +0.3V Input Low Voltage, All inputs V IL (1)--0.3-0.2xVccOutput High Voltage Level V OH K9F1G08U0A :I OH =-400µA 2.4--Output Low Voltage Level V OLK9F1G08U0A :I OL =2.1mA--0.4Output Low Current(R/B)I OL (R/B)K9F1G08U0A :V OL =0.4V810-mA RECOMMENDED OPERATING CONDITIONS(Voltage reference to GND, K9F1G08U0B-XCB0 :T A =0 to 70°C, K9F1G0808B-XIB0:T A =-40 to 85°C)ParameterSymbol K9F1G08U0B(3.3V)UnitMin Typ.Max Supply Voltage V CC 2.7 3.3 3.6V Supply VoltageV SSV ABSOLUTE MAXIMUM RATINGSNOTE :1. Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns. Maximum DC voltage on input/output pins is V CC +0.3V which, during transitions, may overshoot to V CC +2.0V for periods <20ns.2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.ParameterSymbol Rating Unit3.3V Device Voltage on any pin relative to VSSV CC-0.6 to + 4.6VV IN -0.6 to + 4.6V I/O-0.6 to Vcc + 0.3 (< 4.6V)Temperature Under BiasK9XXG08XXB-XCB0T BIAS -10 to +125°C K9XXG08XXB-XIB0-40 to +125Storage Tempera-tureK9XXG08XXB-XCB0T STG-65 to +150°CK9XXG08XXB-XIB0Short Circuit CurrentI OS5mACAPACITANCE (T A =25°C, V CC =3.3V, f=1.0MHz)NOTE : Capacitance is periodically sampled and not 100% tested.ItemSymbol Test ConditionMin Max Unit Input/Output Capacitance C I/O V IL =0V -10pF Input CapacitanceC INV IN =0V-10pFVALID BLOCKNOTE :1. The device may include initial invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase or pro-gram factory-marked bad blocks. Refer to the attached technical notes for appropriate management of invalid blocks.2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block up to 1K program/erase cycles with 1bit/512Byte ECC.ParameterSymbol Min Typ.Max Unit K9F1G08U0BN VB1,004-1,024BlocksMODE SELECTIONNOTE : 1. X can be V IL or V IH.2. WP should be biased to CMOS high or CMOS low for standby.CLE ALE CE WERE WP ModeH L L H X Read Mode Command Input L H L H X Address Input(4clock)H L L H H Write ModeCommand Input L H L H H Address Input(4clock)L L L HH Data Input L L L H XData Output X X X X H X During Read(Busy)X X X X X H During Program(Busy)X X X X X H During Erase(Busy)X X (1)X X X L Write Protect XXHXX0V/V CC (2)Stand-byAC TEST CONDITION(K9F1G08U0B-XCB0 :TA=0 to 70°C, K9F1G08U0B-XIB0:TA=-40 to 85°C, K9F1G08U0B : Vcc=2.7V~3.6V unless otherwise noted)ParameterK9F1G08U0B Input Pulse Levels 0V to Vcc Input Rise and Fall Times 5ns Input and Output Timing Levels Vcc/2Output Load1 TTL GATE and CL=50pF。
AFND1G08U3-CKA规格书(K9F1G08)
• Copy-Back PROGRAM Operation - Fast Page copy without external buffering
z Status Register - Normal Status Register (Read/Program/Erase)
• Security features -OTP area, 16Kbytes(8 pages)
Initial Draft
June. 2012
Preliminary
Rev.01
Add new FBGA PKG dimension option (6.5x8.0mm 48B)
Nov. 2012
Rev. 02 Rev. 03
tRP(/RE Pulse Width) 12ns Æ 15ns
- VOH, VIL, VOL values control - Read Operation Figure modification - Write Protect figures added
PACKAGE DIMENSIONS
48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I)
Rev.03 Jan. 2013
Confidential
7
1G bit (128Mx8Bit)NAND FLASH
K9F4G08U0M中文资料
NC
NC
NC
NC
NC
NC
7
NC
/RE1 R/B2 IO7-2 IO6-2 IO5-2
NC
6
Vcc
/RE2 Vss
IO7-1 IO5-1
Vcc
5
4
/CE1 /CE2
R/B1 /WP2 IO6-1
IO4-1 IO4-2
3
CLE1 CLE2 /WE1
IO0-1 IO2-1
A B
0.65(Max.)
12-∅1.00±0.05
∅0.1 M C AB
Side View
17.00±0.10
41-∅0.70±0.05
∅0.1 M C AB
0.10 C
4
元器件交易网
K9K8G08U1M K9F4G08U0M
Advance FLASH MEMORY
K9K8G08U1M-ICB0/IIB0
12.00±0.10
#A1
17.00±0.10
(Datum A)
A B C D (Datum B) E F G H J K L M N
Bottom View
12.00±0.10
2.00
10.00
1.00
1.00
7 6 54 3 2 1
1.00
1.00
1.00
0.50
1.00
1.00
1.30
2.00 2.50 2.50
1
元器件交易网
K9K8G08U1M K9F4G08U0M
512M x 8 Bit / 1G x 8 Bits NAND Flash Memory
三星K9F1G08U0E（128MB,NANDFLASH）STM32平台驱动程序（模拟时序）
三星K9F1G08U0E（128MB,NANDFLASH）STM32平台驱动程序（模拟时序）STM32平台下模拟时序驱动K9F1G08U0E，主要⽬的为了解、学习NAND FLASH的功能特性，没有使⽤STM32的FSMC（⽕龙开发板硬件为模拟时序驱动），纯粹⾃娱⾃乐，如对你有帮助，不胜荣幸，呵呵。
C⽂件内容：1 #include "NAND512W3A2C.h"2/*3作者:毕⼩乐4⽇期:2019.01.245版本:V1.0067驱动代码针对K9F1G08U0E时序⽽写，K9F1G08U0E与NAND512W3A2C,Pin to Pin兼容。
8驱动运⾏平台STM32F103。
9驱动实现功能：101）Page Read112) Page Program123) Block Erase134) Read Status145) Read ID15PE0~PE7 -> DB00~DB0716PD6 -> CL17PD5 -> AL18PD14 -> W19PD15 -> R20PD7 -> CS21PB5 -> R/B22*/23static void NAND512_Delay_uS(int tick)24 {25int i;26while(tick>0)27 {28 tick--;29for(i=0;i<10;i++)30 __nop();31 }32 }33void NAND512_DB_OutPut(void)34 {35 GPIO_InitTypeDef GPIO_InitStructure;3637 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_338 | GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_6 | GPIO_Pin_7;39 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;40 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;41 GPIO_Init(GPIOE, &GPIO_InitStructure);42 }43void NAND512_DB_InPut(void)44 {45 GPIO_InitTypeDef GPIO_InitStructure;4647 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_348 | GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_6 | GPIO_Pin_7;49 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;50 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;51 GPIO_Init(GPIOE, &GPIO_InitStructure);52 }53char NAND512_DB_Read(void)54 {55char dat;56 NAND512_DB_InPut();57 __nop();58 dat = GPIO_ReadInputData(GPIOE) & 0x00FF;59return dat;60 }61void NAND512_DB_Write(char Data)62 {63 u16 temp;64 NAND512_DB_OutPut();65// __nop();71void NAND512_IO_Init(void)72 {73 GPIO_InitTypeDef GPIO_InitStructure;7475 RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB | RCC_APB2Periph_GPIOD76 | RCC_APB2Periph_GPIOE, ENABLE);7778/*CL*/79 GPIO_InitStructure.GPIO_Pin = NAND512_CL_PIN;80 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;81 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;82 GPIO_Init(NAND512_CL_PORT, &GPIO_InitStructure);8384/*AL*/85 GPIO_InitStructure.GPIO_Pin = NAND512_AL_PIN;86 GPIO_Init(NAND512_AL_PORT, &GPIO_InitStructure);8788/*W*/89 GPIO_InitStructure.GPIO_Pin = NAND512_W_PIN;90 GPIO_Init(NAND512_W_PORT, &GPIO_InitStructure);9192/*R*/93 GPIO_InitStructure.GPIO_Pin = NAND512_R_PIN;94 GPIO_Init(NAND512_R_PORT, &GPIO_InitStructure);9596/*CE*/97 GPIO_InitStructure.GPIO_Pin = NAND512_CE_PIN;98 GPIO_Init(NAND512_CE_PORT, &GPIO_InitStructure);99100/*R/B*/101 GPIO_InitStructure.GPIO_Pin = NAND512_RB_PIN;102 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;103 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;104 GPIO_Init(NAND512_RB_PORT, &GPIO_InitStructure);105106 NAND512_CL_LOW;107 NAND512_AL_LOW;108 NAND512_R_HIGH;109 NAND512_W_HIGH;110 NAND512_CE_HIGH;111 }112113//读状态寄存器信息114char NAND512_Read_Status(void)115 {116char dat;117118 NAND512_CL_LOW;119 NAND512_W_HIGH;120 NAND512_R_HIGH;121 NAND512_CE_HIGH;122 NOP;123124 NAND512_Delay_uS(5);125 NAND512_CL_HIGH;126 NOP;127 NOP;128 NAND512_CE_LOW;129 NOP;130 NOP;131 NOP;132 NAND512_W_LOW;133 NAND512_DB_Write(0x70);134 NOP;135 NAND512_W_HIGH;136137 NAND512_Delay_uS(5);138 NAND512_CL_LOW;139 NOP;140 NOP;141//CE状态保持不变142143 NAND512_Delay_uS(10);144 NAND512_R_LOW;145 NOP;146 dat = NAND512_DB_Read();147 NAND512_Delay_uS(5);148 NAND512_R_LOW;149 NAND512_Delay_uS(5);155156void NAND512_Read_ID(char* Buf)157 {158char i = 0;159160 NAND512_CL_LOW;161 NAND512_AL_LOW;162 NAND512_R_HIGH;163 NAND512_W_HIGH;164 NAND512_CE_HIGH;165 NAND512_Delay_uS(5);166167 NAND512_CL_HIGH;168 NAND512_W_LOW;169 NAND512_Delay_uS(5);170 NAND512_CE_LOW;171 NAND512_DB_Write(0x90);172 NAND512_Delay_uS(5);173 NAND512_W_HIGH;174 NAND512_Delay_uS(5);175176 NAND512_CL_LOW;177 NAND512_Delay_uS(20);178 NAND512_AL_HIGH;179 NAND512_Delay_uS(20);180 NAND512_W_LOW;181 NAND512_DB_Write(0x00); //写地址0182 NAND512_Delay_uS(5);183 NAND512_W_HIGH;184 NAND512_Delay_uS(10);185 NAND512_AL_LOW;186 NAND512_Delay_uS(20);187188for(i=0;i<5;i++)189 {190 NAND512_R_LOW;191 NAND512_Delay_uS(10);192 Buf[i] = NAND512_DB_Read();193 NAND512_R_HIGH;194 NAND512_Delay_uS(10);195 }196197return ;198 }199200void NAND512_Page_Read(char* Buf,int Len,int Add)201 {202int Bank_Index,Page_Index,Page_Start_Add;203int Add_New,j;204char i;205206 Bank_Index = Add / BANK_SIZE;207 Page_Index = (Add % BANK_SIZE) / PAGE_SIZE;208 Page_Start_Add = Add % PAGE_SIZE;209 Add_New = (((Bank_Index<<6) | Page_Index)<<16) | Page_Start_Add; 210211 NAND512_CL_LOW;212 NAND512_AL_LOW;213 NAND512_W_HIGH;214 NAND512_R_HIGH;215 NAND512_CE_HIGH;216 NAND512_Delay_uS(10);217218 NAND512_CE_LOW;219 NAND512_Delay_uS(5);220 NAND512_CL_HIGH;221 NAND512_W_LOW;222 NAND512_DB_Write(0x00);223 NAND512_Delay_uS(5);224 NAND512_W_HIGH;225 NAND512_Delay_uS(5);226 NAND512_CL_LOW;227 NAND512_Delay_uS(5);228 NAND512_AL_HIGH;229 NAND512_Delay_uS(5);230231//发送地址232for(i=0;i<4;i++)233 {239 NAND512_Delay_uS(10);240 }241 NAND512_AL_LOW;242 NAND512_Delay_uS(5);243 NAND512_CL_HIGH;244 NAND512_Delay_uS(5);245 NAND512_W_LOW;246 NAND512_Delay_uS(5);247 NAND512_DB_Write(0x30);248 NAND512_Delay_uS(5);249 NAND512_W_HIGH;250 NAND512_Delay_uS(5);251 NAND512_CL_LOW;252 NAND512_Delay_uS(5);253254while(NAND512_RB_STATUS == 0);255 NAND512_Delay_uS(5);256257for(j=0;j<Len;j++)258 {259 NAND512_R_LOW;260 NAND512_Delay_uS(5);261 Buf[j] = NAND512_DB_Read();262 NAND512_Delay_uS(5);263 NAND512_R_HIGH;264 NAND512_Delay_uS(10);265 }266267return;268 }269270char NAND512_Page_Write(char* Buf,int Len,int Add)271 {272int Bank_Index,Page_Index,Page_Start_Add;273int Add_New,j;274char i,Status;275276 Bank_Index = Add / BANK_SIZE;277 Page_Index = (Add % BANK_SIZE) / PAGE_SIZE;278 Page_Start_Add = Add % PAGE_SIZE;279 Add_New = (((Bank_Index<<6) | Page_Index)<<16) | Page_Start_Add; 280281 NAND512_CL_LOW;282 NAND512_AL_LOW;283 NAND512_W_HIGH;284 NAND512_R_HIGH;285 NAND512_CE_HIGH;286 NAND512_Delay_uS(10);287288 NAND512_CE_LOW;289 NAND512_Delay_uS(5);290 NAND512_CL_HIGH;291 NAND512_W_LOW;292 NAND512_DB_Write(0x80);293 NAND512_Delay_uS(5);294 NAND512_W_HIGH;295 NAND512_Delay_uS(5);296 NAND512_CL_LOW;297 NAND512_Delay_uS(5);298 NAND512_AL_HIGH;299 NAND512_Delay_uS(5);300301//发送地址302for(i=0;i<4;i++)303 {304 NAND512_W_LOW;305 NAND512_Delay_uS(5);306 NAND512_DB_Write(Add_New>>8*i);307 NAND512_Delay_uS(10);308 NAND512_W_HIGH;309 NAND512_Delay_uS(10);310 }311 NAND512_AL_LOW;312 NAND512_Delay_uS(5);313314for(j=0;j<Len;j++)315 {316 NAND512_W_LOW;317 NAND512_Delay_uS(5);324 NAND512_CL_HIGH;325 NAND512_Delay_uS(5);326 NAND512_W_LOW;327 NAND512_Delay_uS(5);328 NAND512_DB_Write(0x10);329 NAND512_Delay_uS(5);330 NAND512_W_HIGH;331 NAND512_Delay_uS(5);332333while(NAND512_RB_STATUS == 0);334 NAND512_Delay_uS(5);335336 Status = NAND512_Read_Status();337338if((Status & 0x01) == 0)339return1;340else341return0;342 }343344char NAND512_Block_Erase(int Add)345 {346int Bank_Index,Page_Index;347int Add_New;348char i,Status;349350 Bank_Index = Add / BANK_SIZE;351 Page_Index = (Add % BANK_SIZE) / PAGE_SIZE; 352 Add_New = (Bank_Index<<6) | Page_Index;353354 NAND512_CL_LOW;355 NAND512_AL_LOW;356 NAND512_W_HIGH;357 NAND512_R_HIGH;358 NAND512_CE_HIGH;359 NAND512_Delay_uS(10);360361 NAND512_CE_LOW;362 NAND512_Delay_uS(5);363 NAND512_CL_HIGH;364 NAND512_W_LOW;365 NAND512_DB_Write(0x60);366 NAND512_Delay_uS(5);367 NAND512_W_HIGH;368 NAND512_Delay_uS(5);369 NAND512_CL_LOW;370 NAND512_Delay_uS(5);371 NAND512_AL_HIGH;372 NAND512_Delay_uS(5);373374//发送地址375for(i=0;i<2;i++)376 {377 NAND512_W_LOW;378 NAND512_Delay_uS(5);379 NAND512_DB_Write(Add_New>>8*i);380 NAND512_Delay_uS(10);381 NAND512_W_HIGH;382 NAND512_Delay_uS(10);383 }384 NAND512_AL_LOW;385 NAND512_Delay_uS(5);386387 NAND512_CL_HIGH;388 NAND512_Delay_uS(5);389 NAND512_W_LOW;390 NAND512_Delay_uS(5);391 NAND512_DB_Write(0xD0);392 NAND512_Delay_uS(5);393 NAND512_W_HIGH;394 NAND512_Delay_uS(5);395 NAND512_CL_LOW;396 NAND512_Delay_uS(5);397398while(NAND512_RB_STATUS == 0);399 NAND512_Delay_uS(5);400401 Status = NAND512_Read_Status();H⽂件内容：1 #ifndef NAND512W3A2C__H2#define NAND512W3A2C__H34 #include "stm32f10x.h"56#define NAND512_CL_PORT GPIOD7#define NAND512_AL_PORT GPIOD8#define NAND512_W_PORT GPIOD9#define NAND512_R_PORT GPIOD10#define NAND512_CE_PORT GPIOD11#define NAND512_RB_PORT GPIOB12#define NAND512_WP_PORT /*GPIOD*/1314#define NAND512_CL_PIN GPIO_Pin_615#define NAND512_AL_PIN GPIO_Pin_516#define NAND512_W_PIN GPIO_Pin_1417#define NAND512_R_PIN GPIO_Pin_1518#define NAND512_CE_PIN GPIO_Pin_719#define NAND512_RB_PIN GPIO_Pin_520#define NAND512_WP_PIN /*GPIO_Pin_5*/2122#define NAND512_CL_CLK RCC_APB2Periph_GPIOD23#define NAND512_AL_CLK RCC_APB2Periph_GPIOD24#define NAND512_W_CLK RCC_APB2Periph_GPIOD25#define NAND512_R_CLK RCC_APB2Periph_GPIOD26#define NAND512_CE_CLK RCC_APB2Periph_GPIOD27#define NAND512_RB_CLK RCC_APB2Periph_GPIOB28#define NAND512_WP_CLK /*RCC_APB2Periph_GPIOD*/2930#define NAND512_CE_LOW GPIO_ResetBits(NAND512_CE_PORT,NAND512_CE_PIN)31#define NAND512_CE_HIGH GPIO_SetBits(NAND512_CE_PORT,NAND512_CE_PIN)32#define NAND512_CL_LOW GPIO_ResetBits(NAND512_CL_PORT,NAND512_CL_PIN)33#define NAND512_CL_HIGH GPIO_SetBits(NAND512_CL_PORT,NAND512_CL_PIN)34#define NAND512_AL_LOW GPIO_ResetBits(NAND512_AL_PORT,NAND512_AL_PIN)35#define NAND512_AL_HIGH GPIO_SetBits(NAND512_AL_PORT,NAND512_AL_PIN)36#define NAND512_W_LOW GPIO_ResetBits(NAND512_W_PORT,NAND512_W_PIN)37#define NAND512_W_HIGH GPIO_SetBits(NAND512_W_PORT,NAND512_W_PIN)38#define NAND512_R_LOW GPIO_ResetBits(NAND512_R_PORT,NAND512_R_PIN)39#define NAND512_R_HIGH GPIO_SetBits(NAND512_R_PORT,NAND512_R_PIN)4041#define NAND512_RB_STATUS GPIO_ReadInputDataBit(NAND512_RB_PORT,NAND512_RB_PIN) 4243#define NOP __nop()44#define BANK_SIZE 13107245#define PAGE_SIZE 20484647extern void NAND512_IO_Init(void);48extern char NAND512_Read_Status(void);49extern void NAND512_Read_ID(char* Buf);50extern void NAND512_Page_Read(char* Buf,int Len,int Add);51extern char NAND512_Page_Write(char* Buf,int Len,int Add);52extern char NAND512_Block_Erase(int Add);53#endif。
艾利和闪存升级支持F型号
升级到1G 单片1G 两片512M
iFP-890/895升级后可使用所有无驱、有驱版本。
iFP-880升级后可使用有驱或无驱固件，但升级闪存后无法再升级固件，请在升级前确认使用什么版本的固件。
iFP-1000系列
100系列用512MX2升级到1G会出现在下载歌曲时会出现停止响应的情况，尤其是建立多个文件夹时停止响应会比较频繁，录音时也有可能出现无法录音的情况，如果对以上的BUG感觉不方便的网友建议只升级到512M。
iFP-300系列
可选升级方案（最大1G，两个闪存位置）：
升级到256M 单片256M 两片128M
iFP-100系列
可选升级方案（最大1G）：
升级到256M 单片256M 两片128M
升级到512M 单片512M 两片256M
升级到1G 两Biblioteka 512M 使用2片128、256M可以使用除无驱1.0e以外的所有版本固件，单片512M只可以使用有驱3.06以上和无驱1.85版固件。2片512M可升级1G，只可以使用有驱3.06版以上固件。使用两片闪存的仅限于线路板编号是M0C、M2C、M2D、iFP-195TC，编号是M2、M4的只有一个闪存位置。
升级后可使用所有无驱、有驱版本。
N11系列
可选升级方案（最大1G，一个闪存位置）：
升级到256M 单片256M
升级到512M 单片512M
升级到1G 单片1G
升级后可使用所有无驱、有驱版本。
希望对大家有所帮助，另外，小艾升级有所困难，最好是把原机升级到无驱版本后才硬件升级（也就是内存加大。至于具体什么有驱无驱的版本，怎样硬件升级等等关于技术上的，那么我就不说了。
UT165 A1B Flash Support List-26
Page 1 of 5 Sys tem Validation TeamSubject: UT165 A1B Flash Compatibility ListThis document shows the flash compatibility list of the series of UT165 A1B controller. MP tool version: 1.65.30.0MP Format Density MP Tool F/W Version VendorTypePage SizePart No. Flash ID Flash ECC Process IdentifierDen sity Single Dual CE #SingleDualUT165 A0A Note SLC 2k K9F4G08U0A EC DC 10 95 54 1bit / 512Bytes - 512MB 489MB 979MB 1BM0790BM0790 SLC 4k K9F8G08U0M EC D3 10 A6 64 1bit / 512Bytes 52nm 1GB 979 MB 1959 MB 1BM0795BM0795 SLC 4k K9K8G08U0A EC D3 51 95 58 1bit / 512Bytes - 1GB 979 MB 1959 MB 1BM4790BM0795 5 SLC 4kK9K8G08U0B EC D3 51 95 58 1bit / 512Bytes 50nm 1GB 979 MB 1959 MB 1BM4790BM0795 5 SLC 4k K9KAG08U0M EC D5 51 A6 68 1bit / 512Bytes 51nm 2GB 1959 MB 3909 MB 1BM4790BM0795 5 SLC 2k K9WAG08U1A EC D3 51 95 58 1bit / 512Bytes - 2GB 1959 MB 3909 MB 2BM3795BM0795 5 SLC 2k K9WAG08U1B EC D3 51 95 58 1bit / 512Bytes 50nm 2GB 1959 MB 3909 MB 2BM3795BM0795 5 SLC 4k K9WBG08U1M EC D5 51 A6 68 1bit / 512Bytes 50nm 4GB 3909 MB 7813 MB 2BM3795BM0795 5MLC 2K K9G4G08U0A EC DC 14 25 54 4bit / 512Bytes - 512MB 481MB 963MB 1BM0795BM0795 SamsungMLC 2kK9G8G08U0AEC D3 14 A5 644bit / 512Bytes51nm1GB963 MB1927 MB1BM0795BM0795Product: UT165Date:08/26/2010Document Type: Flash Support ListRef. No.: UT165 A1B Flash Support List-26MLC 2k K9G8G08U0B EC D3 14 A5 64 4bit / 512Bytes 50nm 1GB 963 MB1927 MB1BM0795BM0795 MLC 2k K9L8G08U0A EC D3 55 25 58 4bit / 512Bytes 51nm 1GB 963 MB1927 MB1BM4790BM0795 5 MLC 2k K9LAG08U0A EC D5 55 A5 68 4bit / 512Bytes 51nm 2GB 1927 MB3846 MB1BM4790BM0795 5 MLC 2k K9LAG08U0B EC D5 55 A5 68 4bit / 512Bytes 50nm 2GB 1927 MB3846 MB1BM4790BM0795 5 MLC 4k K9GAG08U0D EC D5 94 29 34 8bit / 512Bytes 42nm 2GB 1927 MB3846 MB1BM0795BM0795 V 6 MLC 4k K9GAG08U0M EC D5 14 B6 74 4bit / 512Bytes 51nm 2GB 1927 MB3846 MB1BM0795BM0795 V 6 MLC 4k K9LBG08U0D EC D5 94 29 38 4bit / 512Bytes 42nm 4GB 3846 MB7686 MB1BM4790BM0795 V 5,6 SamsungMLC 4k K9LBG08U0M EC D7 55 B6 78 4bit / 512Bytes 51nm 4GB 3846 MB7686 MB1BM4790BM0795 5 MLC 4k K9LBG08U1M EC D5 14 B6 74 4bit / 512Bytes 51nm 4GB 3846 MB7686 MB2BM3795BM0795 V 5,6 MLC 4k K9HBG08U1A EC D5 55 A5 68 4bit / 512Bytes 51nm 4GB 3846 MB7686 MB2BM3795BM0795 5 MLC 4k K9HBG08U1M EC D5 55 25 68 4bit / 512Bytes - 4GB 3846 MB7686 MB2BM3795BM0795 5 MLC 4k K9HCG08U1M EC D7 55 B6 78 4bit / 512Bytes 51nm 8GB 7686 MB15406 MB2BM3795BM0795 V 5,6 MLC 4k K9HCG08U1D EC D7 D5 29 38 4bit / 512Bytes 42nm 8GB 7686 MB15406 MB2BM3795BM0795 V 5,6 MLC 4k K9MDG08U5D EC D7 D5 29 38 4bit / 512Bytes 42nm 16GB15406 MB30814 MB4BM3795BM0795 V 5,6 SLC 2k HY27UF084G2B AD DC 10 95 54 1bit / 512Bytes - 512MB489MB 979MB 1BM0795BM0795 SLC 2k HY27UG088G5M AD DC 80 95 AD 1bit / 512Bytes - 1GB 979 MB1959 MB2BM0795BM0795 SLC 2k HY27UG088G5B AD DC 10 95 54 1bit / 512Bytes 57nm 1GB 979 MB1959 MB2BM3795BM0795 5 HynixMLC 2k HY27UT084G2M AD DC 84 25 AD 4bit / 512Bytes - 512MB481MB 963MB 1BM0795BM0795 MLC 2k HY27UT088G2M AD D3 14 A5 64 4bit / 512Bytes - 1GB 963 MB1927 MB1BM0795BM0795 MLC 2k HY27UU088G5M AD DC 84 25 AD 4bit / 512Bytes - 1GB 963 MB1927 MB2BM0795BM0795MLC 2k HY27UU08AG5A AD D3 14 A5 34 4bit / 512Bytes 57nm 2GB 1927 MB3846 MB2BM3795BM0795 5Page 2 of 5 Sys tem Validation TeamMLC 2k HY27UW08BGFM AD D3 85 25 AD 4bit / 512Bytes - 4GB 3846 MB7686 MB4BM0795BM0795 MLC 4k H27UAG8T2ATR AD D5 94 25 44 12bit / 512Bytes41nm 2GB 1927 MB3846 MB1BM0795BM0795 MLC 4k H27UBG8U5ATR AD D5 94 25 44 12bit / 512Bytes41nm 4GB 3846 MB7686 MB2BM3795BM0795 5 MLC 4k H27UCG8V5ATR AD D7 95 25 48 12bit / 512Bytes41nm 8GB 7686 MB15406 MB2BM3795BM0795 5 HynixMLC 4k H27UBG8T2MYR AD D7 94 25 44 12bit / 512Bytes41nm 4GB 3846 MB7686 MB1BM0795BM0795 MLC 4k H27UCG8UDMYR AD D7 94 25 44 12bit / 512Bytes41nm 8GB 7686 MB15406 MB2BM3795BM0795 5 MLC 4k HY27UBG8U5MTR AD D5 14 B6 44 4bit / 512Bytes 48nm 4GB 3846 MB7686 MB2BM3795BM0795 5 MLC 4k HY27UV08BG5A AD D5 55 A5 38 4bit / 512Bytes 57nm 4GB 3846 MB7686 MB2BM3795BM0795 5 SLC 2k MT29F4G08AAC 2C CC 90 D5 54 1bit / 512Bytes - 512MB489MB 979MB 1BM0795BM0795 SLC 4k MT29F16G08DAA 2C D3 90 2E 64 1bit / 512Bytes 50nm 2GB 1959 MB3909 MB1BM3795BM0795 SLC 4k MT29F32G08FAA 2C D5 D1 2E 68 1bit / 512Bytes 50nm 4GB 3909 MB7813 MB2BM3795BM0795 5 MLC 4k MT29F16G08MAA 2C D5 94 3E 74 8bit / 512Bytes 50nm 2GB 1927 MB3846 MB1BM0795BM0795 V 6 MLC 4k MT29F32G08QAA 2C D5 94 3E 74 8bit / 512Bytes 50nm 4GB 3846 MB7686 MB2BM3795BM0795 V 5,6 MLC 4k MT29F64G08TAA 2C D7 D5 3E 78 8bit / 512Bytes 50nm 8GB 7686 MB15406 MB2BM3795BM0795 V 5,6 MicronMLC 4k MT29F16G08CBABA 2C 48 04 46 85 12bit / 540Bytes34nm 2GB 1927 MB3846 MB1BM0795BM0795 MLC 4k MT29F32G08CBAAA 2C D7 94 3E 84 12bit / 539Bytes34nm 4GB 3846 MB7686 MB1BM0795BM0795 V 6,7 MLC 4k MT29F32G08CBABA 2C 68 04 46 89 12bit / 540Bytes34nm 4GB 3846 MB7686 MB1BM0795BM0795 MLC 4k MT29F64G08CFAAA 2C D7 94 3E 84 12bit / 539Bytes34nm 8GB 7686 MB15406 MB2BM3795BM0795 V 5,6,7 MLC 4k MT29F64G08CFABA 2C 68 04 46 89 12bit / 540Bytes34nm 8GB 7686 MB15406 MB2BM3795BM0795 5 MLC 4k MT29F128G08CJAAA 2C D9 D5 3E 88 12bit / 539Bytes34nm 16GB15406 MB30814 MB2BM3795BM0795 V 5,6,7 MLC 4k MT29F128G08CJABA 2C 88 05 C6 89 12bit / 540Bytes34nm 16GB15406 MB30814 MB2BM3795BM0795 5Page 3 of 5 Sys tem Validation TeamSLC 4K29F16G08CANC1 89 D3 90 2E 64 1-bit / 528 Bytes50nm 2GB 1959 MB3909 MB2BM3795BM0795 5 MLC 4k29F16G08AAMDB 89 48 04 46 A5 12bit / 540Bytes34nm 2GB 1927 MB3846 MB1BM0795BM0795MLC 4k29F16G08AAMC1 89 D5 94 3E 74 8bit / 512Bytes 50nm 2GB 1927 MB3846 MB1BM0795BM0795 MLC 4k29F32G08CAMC1 89 D5 94 3E 74 8bit / 512Bytes 50nm 4GB 3846 MB7686 MB2BM3795BM0795 5 MLC 4k29F64G08FAMC1 89 D7 D5 3E 78 8bit / 512Bytes 50nm 8GB 7686 MB15406 MB2BM3795BM0795 5 MLC 4k29F32G08AAMDA 89 68 04 46 89 (A9)12bit / 540Bytes34nm 4GB 3846 MB7686 MB1BM0795BM0795 MLC 4k29F32G08AAMDB 89 68 04 46 89 (A9)12bit / 540Bytes34nm 4GB 3846 MB7686 MB1BM0795BM0795 IntelMLC 4k29F32G08AAMD1 89 D7 94 3E 84 12bit / 512Bytes34nm 4GB 3846 MB7686 MB1BM0795BM0795 V 6,7 MLC 4k29F32G08AAMD2 89 D7 94 3E 84 12bit / 512Bytes34nm 4GB 3846 MB7686 MB1BM0795BM0795 V 6,7 MLC 4k29F64G08CAMD1 89 D7 94 3E 84 12bit / 512Bytes34nm 8GB 7686 MB15406 MB2BM3795BM0795 V 5,6,7 MLC 4k29F64G08CAMD2 89 D7 94 3E 84 12bit / 512Bytes34nm 8GB 7686 MB15406 MB2BM3795BM0795 V 5,6,7 MLC 4k29F64G08CAMDB 89 68 04 46 89 (A9)12bit / 540Bytes34nm 8GB 7686 MB15406 MB2BM3795BM0795 5 MLC 4k29F16B08JAMDB 89 68 04 46 89 (A9)12bit / 540Bytes34nm 16GB15406 MB30814 MB4BM3795BM0795 5 MLC 4k29F16B08JAMD1 89 D7 94 3E 84 12bit / 512Bytes34nm 16GB15406 MB30814 MB4BM3795BM0795 V 5,6,7 MLC 4k29F16B08JAMD2 89 D7 94 3E 84 12bit / 512Bytes34nm 16GB15406 MB30814 MB4BM3795BM0795 V 5,6,7 MLC 2K TH58NVG4D4CTG 98 D5 85 A5 6A 4bit / 512Bytes - 2GB 1927 MB3846 MB1BM0795BM0795 MLC 4k TC58NVG3D1DTG10 98 D3 94 BA 64 8bit / 512Bytes 56nm 1GB 963 MB1927 MB1BM0795BM0795 ToshibaMLC 4k TC58NVG4D1DTG00 98 D5 94 BA 74 8bit / 512Bytes 56nm 2GB 1927 MB3846 MB1BM0795BM0795 MLC 4k TH58NVG5D1DTG20 98 D5 94 BA 74 8bit / 512Bytes 56nm 4GB 3846 MB7686 MB2BM0795BM0795 MLC 4k TH58NVG6D1DTG20 98 D7 95 BA 78 8bit / 512Bytes 56nm 8GB 7686 MB n/a 2BM0795BM0795 ST SLC 2k NAND04GW3B2DN6 20 DC 10 95 54 - - 512MB489MB 979MB 1BM0795BM0795Page 4 of 5 Sys tem Validation TeamSLC 2k NAND08GW3B2CN6 20 D3 51 95 58 1GB 979 MB1959 MB1BM0795BM0795STMLC 2k NAND08GW3C2BN6 20 D3 14 A5 34 - - 1GB 963 MB1927 MB1BM0795BM0795Note:1.Support 16CE.2.Non-Support Force single channel.3.Support single channel only.4.Please contact our FAE for consultation.5.Support Interleave function for single channel only, dual channel do not support interleave function.6.For UT165 A0A MP Tool F/W Version : Single / Dual - AM0688 ,AT0688 ; Support Interleave Flash – AM36887.UT165 can only support maximum 8 die列 flash 聯 72 讀 .The listed flash devices are based on ITE laboratory sample and pass 72 hours burn-in test.Page 5 of 5 Sys tem Validation Team。
K9F2G08X0C_0.1
K9F2G08X0CINFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE.NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDEDON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.1. For updates or additional information about Samsung products, contact your nearest Samsung office.2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply.* Samsung Electronics reserves the right to change products or specification without notice.Document Title256M x 8 Bit NAND Flash Memory Revision HistoryThe attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the rightto change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questions, please contact the SAMSUNG branch office near your office.Revision No0.00.1RemarkAdvance AdvanceHistory1. Initial issue1. DC Parameter is chagned2. Typo is modifiedDraft DateAug. 12, 2009Dec. 9, 20091.0 Introduction1.1 PRODUCT LIST1.2 FEATURES1.3 GENERAL DESCRIPTIONOffered in 256Mx8bit, the K9F2G08X0C is a 2G-bit NAND Flash Memory with spare 64M-bit. Its NAND cell provides the most cost-effective solution for the solid state application market. A program operation can be performed in typical 250µs on the (2K+64)Byte page and an erase operation can be performed in typical 2ms on a (128K+4K)Byte block. Data in the data register can be read out at 30ns cycle time per Byte. The I/O pins serve as the ports for address and data input/output as well as command input. The on-chip write controller automates all program and erase functions including pulse repetition, where required, and internal verification and margining of data. Even the write-intensive systems can take advantage of the K9F2G08X0C ′s extended reliability of 100K program/erase cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm. The K9F2G08X0C is an optimum solu-tion for large nonvolatile storage applications such as solid state file storage and other portable applications requiring non-volatility.Part Number Vcc Range OrganizationPKG Type K9F2G08U0C-S 2.7 ~ 3.6v x8TSOP1K9F2G08U0C-H2.7 ~3.6vx863 FBGA• Voltage Supply- 3.3V device(K9F2G08U0C ): 2.70V ~ 3.60V • Organization- Memory Cell Array : (256M + 8M) x 8bit - Data Register : (2K + 64) x 8bit • Automatic Program and Erase - Page Program : (2K + 64)Byte - Block Erase : (128K + 4K)Byte • Page Read Operation- Page Size : (2K + 64)Byte - Random Read : 35µs (Max.) - Serial Access : 30ns (Min.)• Fast Write Cycle Time- Page Program time : 250µs (Typ.) - Block Erase Time : 2ms (Typ.)• Command/Address/Data Multiplexed I/O Port • Hardware Data Protection- Program/Erase Lockout During Power Transitions • Reliable CMOS Floating-Gate Technology-Endurance & Data Retention : Refor to the gualification report -ECC regnirement : 1 bit / 528bytes • Command Driven Operation • Unique ID for Copyright Protection • Package :- K9F2G08U0C-SCB0/SIB0 : Pb-FREE PACKAGE 48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)- K9F2G08U0C-HCB0/HIB0 : Pb-FREE PACKAGE 63 - ball FBGA (9 x 11 / 0.8 mm pitch)K9F2G08X0C-HCB0/HIB0PACKAGE DIMENSIONS48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I)48 - TSOP1 - 1220FUnit :mm/Inch0.787±0.00820.00±0.20#1#240.20+0.07-0.030.008+0.003-0.0010.500.0197#48#250.48812.40M A X12.000.4720.10 0.004M A X 0.250.010()0.039±0.0021.00±0.050.0020.05MIN0.0471.20MAX0.45~0.750.018~0.0300.724±0.00418.40±0.100~8°0.0100.25T Y P0.125+0.0750.0350.005+0.003-0.0010.500.020()48-pin TSOP1Standard Type 12mm x 20mm123456789101112131415161718192021222324484746454443424140393837363534333231302928272625N.C N.C N.C N.C N.C N.C R/B RE CE N.C N.C Vcc Vss N.C N.C CLE ALE WE WP N.C N.C N.C N.C N.CN.C N.C N.C N.C I/O7I/O6I/O5I/O4N.C N.C N.C Vcc Vss N.C N.C N.C I/O3I/O2I/O1I/O0N.C N.C N.C N.CK9F2G08X0C-HCB0/HIB0R/B /WE /CE Vss ALE /WP /RE CLE NC NC NCNCVcc NC NC I/O0I/O1NC NCVccQ I/O5I/O7VssI/O6I/O4I/O3I/O2VssNC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NCNC NC NCN.CN.C N.C N.C N.C N.CN.CN.CN.C N.C N.C N.CN.C N.C N.C 34561 2A B CD GEF HTop View1.5.1 PACKAGE DIMENSIONS63-Ball FBGA (measured in millimeters)9.00±0.10#A1Side ViewTop View1.00(M a x .)0.45±0.054321A BC D G Bottom View11.00±0.1063-∅0.45±0.050.80 x 7= 5.6011.00±0.100.80 x 5= 4.000.800.25(M i n .)0.10MAXBA2.809.00±0.10(Datum B)(Datum A)0.20 M A B∅0.800.80 x 11= 8.800.80 x 9= 7.20 659.00±0.10EF H2.001.6 PIN DESCRIPTIONNOTE : Connect all V CC and V SS pins of each device to common power supply outputs. Do not leave V CC or V SS disconnected.Pin Name Pin FunctionI/O 0 ~ I/O 7DATA INPUTS/OUTPUTSThe I/O pins are used to input command, address and data, and to output data during read operations. The I/O pins float to high-z when the chip is deselected or when the outputs are disabled.CLECOMMAND LATCH ENABLEThe CLE input controls the activating path for commands sent to the command register. When active high, commands are latched into the command register through the I/O ports on the rising edge of the WE signal.ALEADDRESS LATCH ENABLEThe ALE input controls the activating path for address to the internal address registers. Addresses are latched on the rising edge of WE with ALE high.CECHIP ENABLEThe CE input is the device selection control. When the device is in the Busy state, CE high is ignored, and the device does not return to standby mode in program or erase operation.REREAD ENABLEThe RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after the falling edge of RE which also increments the internal column address counter by one.WEWRITE ENABLEThe WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse.WPWRITE PROTECTThe WP pin provides inadvertent program/erase protection during power transitions. The internal high volt-age generator is reset when the WP pin is active low.R/BREADY/BUSY OUTPUTThe R/B output indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is in process and returns to high state upon completion. It is an open drain output and does not float to high-z condition when the chip is deselected or when outputs are disabled.Vcc POWERV CC is the power supply for device. Vss GROUNDN.CNO CONNECTIONLead is not internally connected.2.0 Product IntroductionNAND Flash Memory has addresses multiplexed into 8 I/Os. This scheme dramatically reduces pin counts and allows system upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through I/O's by bringing WE to low while CE is low. Those are latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. Some commands require one bus cycle. For example, Reset Command, Status Read Command, etc. require just one cycle bus. Some other commands, like page read and block erase and page program, require two cycles: one cycle for setup and the other cycle for execution.. Page Read and Page Program need the same five address cycles following the required command input. In Block Erase operation, however, only the three row address cycles are used. Device operations are selected by writing specific commands into the command register. Table 1 defines the specific commands of the K9G2G08U0C.Table 1. Command SetsFunction1st Cycle2nd Cycle Acceptable Command during Busy Read 00h30hRead for Copy Back00h35hRead ID90h-Reset FFh-OPage Program80h10hCopy-Back Program85h10hTwo-Plane Page Program(2)80h---11h81h---10hBlock Erase60h D0hRandom Data Input(1)85h-Random Data Output(1)05h E0hRead Status70h-ORead Status 2F1h-ONOTE : 1. Random Data Input/Output can be executed in a page.2. Any command between 11h and 81h is prohibited except 70h/F1h and FFh.Caution : Any undefined command inputs are prohibited except for above command set of Table 1.2.1 ABSOLUTE MAXIMUM RATINGSNOTE :1. Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns. Maximum DC voltage on input/output pins is V CC +0.3V which, during transitions, may overshoot to V CC +2.0V for periods <20ns.2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.2.2 RECOMMENDED OPERATING CONDITIONS(Voltage reference to GND, K9F2G08X0C-XCB0 :T A =0 to 70°C, K9F2G08X0C-XIB0:T A =-40 to 85°C)2.3 DC AND OPERATING CHARACTERISTICS (Recommended operating conditions otherwisenoted.)NOTE : 1. V IL can undershoot to -0.4V and V IH can overshoot to V CC +0.4V for durations of 20 ns or less. 2. Typical value is measured at Vcc= 3.3V, T A =25°C. Not 100% tested.ParameterSymbol Rating Unit Voltage on any pin relative to VSSV CC -0.6 to +4.6VV IN -0.6 to +4.6V I/O-0.6 to Vcc + 0.3 (< 4.6V)Temperature Under BiasK9F2G08X0C-XCB0T BIAS -10 to +125°C K9F2G08X0C-XIB0-40 to +125Storage Temperature K9F2G08X0C-XCB0T STG-65 to +150°CK9F2G08X0C-XIB0Short Circuit CurrentI OS5mAParameterSymbol 3.3VUnit Min Typ.Max Supply Voltage V CC 2.7 3.3 3.6V Supply VoltageV SSVParameterSymbol Test Conditions3.3VUnitMinTypMaxOperating CurrentPage Read with Serial Access I CC 1tRC=30nsCE=V IL, I OUT =0mA-2035mAProgram I CC 2-EraseI CC 3-Stand-by Current(TTL)I SB 1CE=V IH , WP=0V/V CC --1Stand-by Current(CMOS)I SB 2CE=V CC -0.2, WP=0V/V CC -1050µAInput Leakage Current I LI V IN =0 to Vcc(max)--±10Output Leakage Current I LO V OUT =0 to Vcc(max)--±10Input High VoltageV IH (1)-0.8xVcc -Vcc+0.3V Input Low Voltage, All inputs V IL (1)--0.3-0.2xVccOutput High Voltage Level V OH K9F2G08B0C: I OH=-100µA K9F2G08U0C: I OH =-400µA 2.4--Output Low Voltage Level V OL K9F2G08B0C: I OL=100µA K9F2G08U0C: I OL =2.1mA --0.4Output Low Current(R/B)I OL (R/B)K9F2G08B0C: V OL =0.1V K9F2G08U0C: V OL =0.4V810-mA2.4 VALID BLOCKNOTE :1. The device may include initial invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase or pro-gram factory-marked bad blocks. Refer to the attached technical notes for appropriate management of invalid blocks.2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block up to 1K program/erase cycles with 1bit/528Byte ECC.3. The number of valid block is on the basis of single plane operations, and this may be decreased with two plane operations.2.5 AC TEST CONDITION (K9F2G08X0C-XCB0 :T A =0 to 70°C, K9F2G08X0C-XIB0:T A =-40 to 85°C, K9F2G08U0C: Vcc=2.7V~3.6V unless otherwise noted)2.6 CAPACITANCE (T A =25°C, V CC =3.3V, f=1.0MHz)NOTE : Capacitance is periodically sampled and not 100% tested.2.7 MODE SELECTIONNOTE : 1. X can be V IL or V IH.2. WP should be biased to CMOS high or CMOS low for standby.Parameter Symbol Min Typ.Max Unit K9F2G08X0CN VB2,008-2,048BlocksParameterK9F2G08X0C Input Pulse Levels 0V to Vcc Input Rise and Fall Times 5ns Input and Output Timing Levels Vcc/2Output Load1 TTL GATE and CL=50pFItemSymbol Test ConditionMin Max Unit Input/Output Capacitance C I/O V IL =0V -10pF Input CapacitanceC INV IN =0V-10pFCLE ALE CE WERE WP ModeH L L H X Read Mode Command Input L H L H X Address Input(5clock)H L L H H Write Mode Command Input L H L H H Address Input(5clock)L L L HH Data Input L L L H X Data Output X X X X H X DuringRead(Busy)X X X X X H During Program(Busy)X X X X X H During Erase(Busy)X X (1)X X X L Write Protect XXHXX0V/V CC (2)Stand-by2.8 Program / Erase CharacteristicsParameter Symbol Min Typ Max Unit Program Time t PROG-250750µs Number of Partial Program Cycles Nop--4cycles Block Erase Time t BERS-210ms NOTE :1. Typical value is measured at Vcc=3.3V, T A=25°C. Not 100% tested.2. Typical program time is defined as the time within which more than 50% of the whole pages are programmed at3.3V Vcc and 25°C temperature.2.9 AC Timing Characteristics for Command / Address / Data InputParameter Symbol Min Max Unit CLE Setup Time t CLS(1)15-ns CLE Hold Time t CLH5-nsCE Setup Time t CS(1)20-nsCE Hold Time t CH5-nsWE Pulse Width t WP15-ns ALE Setup Time t ALS(1)15-ns ALE Hold Time t ALH5-ns Data Setup Time t DS(1)15-ns Data Hold Time t DH5-ns Write Cycle Time t WC30-nsWE High Hold Time t WH10-ns Address to Data Loading Time t ADL(2)100-ns NOTES : 1. The transition of the corresponding control pins must occur only once while WE is held low2. tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle2.10 AC Characteristics for OperationParameter Symbol Min Max Unit Data Transfer from Cell to Register t R-35µs ALE to RE Delay t AR10-ns CLE to RE Delay t CLR10-ns Ready to RE Low t RR20-ns RE Pulse Width t RP15-ns WE High to Busy t WB-100ns Read Cycle Time t RC30-ns RE Access Time t REA-20ns CE Access Time t CEA-25ns RE High to Output Hi-Z t RHZ-100ns CE High to Output Hi-Z t CHZ-30ns CE High to ALE or CLE Don’t Care t CSD0-ns RE High to Output Hold t RHOH15-ns RE Low to Output Hold t RLOH5-ns CE High to Output Hold t COH15-ns RE High Hold Time t REH10-ns Output Hi-Z to RE Low t IR0-ns RE High to WE Low t RHW100-ns WE High to RE Low t WHR60-ns Device Resetting Time(Read/Program/Erase)t RST-5/10/500(1)µs NOTE : 1. If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5µs.3.0 NAND Flash Technical Notes3.1 Initial Invalid Block(s)Initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is not guaranteed by Samsung. The information regarding the initial invalid block(s) is called the initial invalid block information. Devices with initial invalid block(s) have the same quality level as devices with all valid blocks and have the same AC and DC characteristics. An initial invalid block(s) does not affect the performance of valid block(s) because it is isolated from the bit line and the common source line by a select tran-sistor. The system design must be able to mask out the initial invalid block(s) via address mapping. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block up to 1K program/erase cycles with 1bit /528Byte ECC .3.2 Identifying Initial Invalid Block(s)All device locations are erased(FFh) except locations where the initial invalid block(s) information is written prior to shipping. The ini-tial invalid block(s) status is defined by the 1st byte in the spare area. Samsung makes sure that either the 1st or 2nd page of every initial invalid block has non-FFh data at the column address of 2048. Since the initial invalid block information is also erasable in most cases, it is impossible to recover the information once it has been erased. Therefore, the system must be able to recognize the initial invalid block(s) based on the original initial invalid block information and create the initial invalid block table via the following sug-gested flow chart(Figure 3). Any intentional erasure of the original initial invalid block information is prohibited.*Check "FFh" at the column address 2048 Figure 3. Flow chart to create initial invalid block tableStartSet Block Address = 0Check "FFh"Increment Block AddressLast Block ?EndNoYesYesCreate (or update)NoInitialof the 1st and 2nd page in the blockInvalid Block(s) TableNAND Flash Technical Notes (Continued)3.3 Error in write or read operationWithin its life time, additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual data.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read fail-ure after erase or program, block replacement should be done. Because program status fail during a page program does not affect the data of the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erased empty block and reprogramming the current target data and copying the rest of the replaced block. In case of Read, ECC must be employed. To improve the efficiency of memory space, it is recommended that the read or verification failure due to single bit error be reclaimed by ECC without any block replacement. The said additional block failure rate does not include those reclaimed blocks.Failure ModeDetection and Countermeasure sequenceWrite Erase Failure Status Read after Erase --> Block Replacement Program Failure Status Read after Program --> Block Replacement ReadSingle Bit FailureVerify ECC -> ECC CorrectionProgram Flow ChartStartI/O 6 = 1 ?I/O 0 = 0 ?No*Write 80hWrite AddressWrite DataWrite 10hRead Status RegisterProgram Completedor R/B = 1 ?Program ErrorYesNoYes: If program operation results in an error, map out the block including the page in error and copy thetarget data to another block.*ECC: Error Correcting Code --> Hamming Code etc. Example) 1bit correction & 2bit detection3.4 Addressing for program operationWithin a block, the pages must be programmed consecutively from the LSB(least significant bit) page of the block to the MSB(most significant bit) pages of the block. Random page address programming is prohibited. In this case, the definition of LSB page is the LSB among the pages to be programmed. Therefore, LSB doesn't need to be page 0.From the LSB page to MSB page DATA IN: Data (1)Data (64)(1)(2)(3)(32)(64)Data register Page 0Page 1Page 2Page 31Page 63Ex.) Random page program (Prohibition)DATA IN: Data (1)Data (64)(2)(32)(3)(1)(64)Data registerPage 0Page 1Page 2Page 31Page 63::::4.13 Read ID OperationDevice Device Code (2nd Cycle)3rd Cycle 4th Cycle 5th Cycle K9F2G08U0CDAh10h15h44hCECLEWEALERE90hRead ID CommandMaker Code Device Code00h ECht REAAddress 1cycleI/Oxt ARDevice 4th cyc.Code3rd cyc.5th cyc.ID Definition Table3rd ID Data 4th ID Data Description1st Byte 2nd Byte 3rd Byte 4th Byte 5th Byte Maker CodeDevice CodeInternal Chip Number, Cell Type, Number of Simultaneously Programmed Pages, EtcPage Size, Block Size,Redundant Area Size, Organization, Serial Access MinimumPlane Number, Plane SizeDescription I/O7 I/O6I/O5 I/O4I/O3 I/O2I/O1 I/O0Internal Chip Number 12480 00 11 01 1Cell Type 2 Level Cell4 Level Cell8 Level Cell16 Level Cell0 00 11 01 1Number ofSimultaneouslyProgrammed Pages 12480 00 11 01 1Interleave Program Between multiple chips Not SupportSupport1Cache Program Not SupportSupport1Description I/O7 I/O6I/O5 I/O4 I/O3I/O2I/O1 I/O0Page Size(w/o redundant area ) 1KB2KB4KB8KB0 00 11 01 1Block Size(w/o redundant area ) 64KB128KB256KB512KB0 00 11 01 1Redundant Area Size ( byte/512byte) 8161Organization x8x161Serial Access Minimum 50ns/30ns25nsReservedReserved11115th ID DataDescription I/O7I/O6 I/O5 I/O4I/O3 I/O2 I/O1I/O0Plane Number 12480 00 11 01 1Plane Size(w/o redundant Area) 64Mb128Mb256Mb512Mb1Gb2Gb4Gb8Gb0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1Reserved 0 0 05.2 PAGE PROGRAMThe device is programmed basically on a page basis, but it does allow multiple partial page programming of a word or consecutive bytes up to 2,112, in a single page program cycle. The number of consecutive partial page programming operation within the same page without an intervening erase operation must not exceed 4 times for a single page. The addressing should be done in sequential order in a block. A page program cycle consists of a serial data loading period in which up to 2,112bytes of data may be loaded into the data register, followed by a non-volatile programming period where the loaded data is programmed into the appropriate cell.The serial data loading period begins by inputting the Serial Data Input command(80h), followed by the five cycle address inputs and then serial data loading. The words other than those to be programmed do not need to be loaded. The device supports random data input in a page. The column address for the next data, which will be entered, may be changed to the address which follows random data input command(85h). Random data input may be operated multiple times regardless of how many times it is done in a page. The Page Program confirm command(10h) initiates the programming process. Writing 10h alone without previously entering the serial data will not initiate the programming process. The internal write state controller automatically executes the algorithms and timings necessary for program and verify, thereby freeing the system controller for other tasks. Once the program process starts, the Read Status Register command may be entered to read the status register. The system controller can detect the completion of a program cycle by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. Only the Read Status command and Reset com-mand are valid while programming is in progress. When the Page Program is complete, the Write Status Bit(I/O 0) may bechecked(Figure 8). The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command register remains in Read Status command mode until another valid command is written to the command register.Figure 7. Random Data Output In a PageAddress 00hData OutputR/B RE t30hAddress 05hE0h5Cycles2Cycles Data OutputData Field Spare Field Data Field Spare FieldI/OxCol. Add.1,2 & Row Add.1,2,3Col. Add.1,2Figure 8. Program & Read Status Operation80hR/B Address & Data Input I/O0PassData10h70hFailt PROGI/OxCol. Add.1,2 & Row Add.1,2,3"0""1"5.3 Copy-Back ProgramCopy-Back program with Read for Copy-Back is configured to quickly and efficiently rewrite data stored in one page without data re-loading when the bit error is not in data stored. Since the time-consuming re-loading cycles are removed, the system performance is improved. The benefit is especially obvious when a portion of a block is updated and the rest of the block also needs to be copied to the newly assigned free block. Copy-Back operation is a sequential execution of Read for Copy-Back and of copy-back program with the destination page address. A read operation with "35h" command and the address of the source page moves the whole 2,112-byte data into the internal data buffer. A bit error is checked by sequential reading the data output. In the case where there is no bit error,the data do not need to be reloaded. Therefore Copy-Back program operation is initiated by issuing Page-Copy Data-Input command (85h) with destination page address. Actual programming operation begins after Program Confirm command (10h) is issued. Once the program process starts, the Read Status Register command (70h) may be entered to read the status register. The system controller can detect the completion of a program cycle by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. When the Copy-Back Program is complete, the Write Status Bit(I/O 0) may be checked(Figure 10 & Figure 11). The command register remains in Read Status command mode until another valid command is written to the command register.During copy-back program, data modification is possible using random data input command (85h) as shown in Figure11.Figure 9. Random Data Input In a Page80hR/B Address & Data Input I/O0Pass10h70hFailt PROG85hAddress & Data InputI/OxCol. Add.1,2 & Row Add1,2,3Col. Add.1,2 DataData"0""1""0""1"Figure 10. Page Copy-Back Program Operation00hR/B Add.(5Cycles)I/O0Pass85h 70h Failt PROGAdd.(5Cycles) t R Source Address Destination Address35h10h I/OxCol. Add.1,2 & Row Add.1,2,3Col. Add.1,2 & Row Add.1,2,3Figure 11. Page Copy-Back Program Operation with Random Data Input00hR/B Add.(5Cycles)85h 70ht PROGAdd.(5Cycles) t RSource AddressDestination AddressData 35h10h 85hData Add.(2Cycles) There is no limitation for the number of repetition.I/OxCol. Add.1,2 & Row Add.1,2,3Col. Add.1,2 & Row Add.1,2,3Col. Add.1,2Note : Copy-Back Program operation is allowed only within the same memory plane.5.4 READ STATUSThe device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether the program or erase operation is completed successfully. After writing 70h/F1h command to the command register, a read cycle out-puts the content of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE does not need to be toggled for updated status. Refer to Table 3 for specific Status Register definitions and Table 4 for specific F1h Status Register definitions. The command register remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read cycle, the read command(00h) should be given before starting read cycles.Table 3. Read Status Register Definition for 70h CommandI/O Page Program Block Erase Read DefinitionI/O 0Pass/Fail Pass/Fail Not use Pass : "0" Fail : "1"I/O 1Not use Not use Not use Don’t -caredI/O 2Not use Not use Not use Don’t -caredI/O 3Not Use Not Use Not Use Don’t -caredI/O 4Not Use Not Use Not Use Don’t -caredI/O 5Not Use Not Use Not Use Don’t -caredI/O 6Ready/Busy Ready/Busy Ready/Busy Busy : "0" Ready : "1"I/O 7Write Protect Write Protect Write Protect Protected : "0" Not Protected : "1" NOTE : I/Os defined ’Not use’ are recommended to be masked out when Read Status is being executed.Table 4. Read Status 2 Register Definition for F1h CommandI/O No.Page Program Block Erase Read DefinitionI/O 0Chip Pass/Fail Chip Pass/Fail Not use Pass : "0" Fail : "1"I/O 1Plane0 Pass/Fail Plane0 Pass/Fail Not use Pass : "0" Fail : "1"I/O 2Plane1 Pass/Fail Plane1 Pass/Fail Not use Pass : "0" Fail : "1"I/O 3Not Use Not Use Not Use Don’t -caredI/O 4Not Use Not Use Not Use Don’t -caredI/O 5Not Use Not Use Not Use Don’t -caredI/O 6Ready/Busy Ready/Busy Ready/Busy Busy : "0" Ready : "1"I/O 7Write Protect Write Protect Write Protect Protected : "0" Not Protected : "1" NOTE : I/Os defined ’Not use’ are recommended to be masked out when Read Status is being executed.。
TE2440-II用户手册
TE2440-II用户手册V2.0保定飞凌嵌入式技术有限公司网站：论坛：/bbsTE2440-II是由飞凌嵌入式技术有限公司在原有TE2440开发板的基础上修改并添加了部分功能设计生产的一款基于ARM9的嵌入式工控板，它基于三星公司的ARM处理器S3C2440A，内部带有全性能的MMU(内存处理单元)，适用于设计移动手持设备类产品。
TE2440-II采用底板+核心板形式，底板为四层，核心板为六层，性能稳定可靠，具有高性能、低功耗、接口丰富和体积小等优良特性。
该开发板已将芯片S3C2440A 的功能发挥的淋漓尽致，目前已成功移植Linux，WINCE等操作系统。
在使用开发板时，请注意以下事项：1．用户在拿到开发板后，请至网站“客户服务”页面注册，并打电话通知我们您的姓名，购买时间，注册名称，开发板的编号，我们会及时为您开通会员权限，便于您及时下载更新的资料！2．第一次使用TE2440-II开发板时，请务必先阅读用户手册，按照手册上所述进行相关操作，谨防随意破坏系统程序！3．每次使用TE2440-II开发板前，请先将手接触开发板周围金属接口或者其它地方放电，避免直接用手触摸芯片造成芯片烧坏！4．需要对开发板进行物理操作时，请关闭电源，除USB以及网络接口（如果与局域网相接请使用普通网线，开发板带网线为计算机直连网线）外，其它接口均不支持热插拔，开发板工作时，请不要带电插拔。
5.本开发板硬件保修时间为三个月（人为或不可抗力原因除外），技术支持时间三个月（论坛技术支持及“客户服务”下载时间不在此限）。
最后，欢迎您使用TE2440-II开发板，并提出宝贵意见！编者：飞凌嵌入式技术有限公司地址：河北保定市七一西路165号邮编：071051QQ:93644331360189317E-mail：***************.cn网址：论坛：/bbs目录一.第一章TE2440-II开发板硬件介绍 (5)1.1开发套件包含的内容 (5)1.2用户光盘内容说明 (6)1.3TE2440-II开发板外观 (6)1.4TE2440-II开发板硬件资源 (7)1.5硬件资源分配 (8)1.5.1地址空间分配以及片选信号定义 (8)1.5.2开发板接口说明 (10)1.5.3按键说明 (10)1.5.4LED指示灯说明 (11)1.5.5跳线分配表 (11)1.6TE2440-II开发板主要硬件说明 (11)1.6.1系统存储器 (11)1.6.2JTAG及复位逻辑 (12)1.6.3LCD/触摸屏接口引脚定义 (14)1.6.4网络接口 (16)1.6.5IDE（也作为总线接口）接口引脚定义 (19)1.6.6GPIO扩展口引脚定义 (21)1.6.7SD卡接口 (21)1.6.8IIS音频输入输出接口 (23)1.6.9摄像头接口: (24)1.6.10串口电路 (24)1.6.11USB接口 (26)1.6.12功能按键及用户LED指示灯 (27)1.6.13红外接收电路 (29)1.6.14温度传感器电路 (30)1.6.15EEPROM(24C02)电路 (30)1.6.16CAN总线接口电路 (31)1.7TE2440-II支持的操作系统及其驱动 (33)1.7.1Linux操作系统 (33)1.7.2WINCE操作系统 (34)二.第二章TE2440-II开发板基本使用 (35)2.1TE2440-II外部硬件连接 (35)2.2WINDOWS下驱动的安装 (35)2.2.1安装USB驱动 (35)2.2.2安装并口驱动程序 (38)2.3调试终端使用 (41)2.3.1DWN软件的使用 (41)2.3.2超级终端的使用 (42)2.4BOOTLOADER使用全攻略 (45)2.4.1bootloader简介 (45)2.4.2功能菜单说明 (46)2.4.3选择菜单说明 (47)2.4.4参数设置说明 (48)2.4.5如何烧写程序 (49)2.4.6用sjf2440.exe烧写bootloader程序 (51)2.5ADS下的LED试验 (52)2.5.1ADS安装 (52)2.5.2使用ADS创建工程 (52)2.5.3编译和链接工程 (58)2.5.4H-JTAG的安装使用 (67)2.5.5用AXD进行代码调试 (70)一.第一章TE2440-II开发板硬件介绍TE2440-II开发板为底板+核心板形式，底板为四层，核心板为六层板，开发板的布局和走线经过专业人士精心设计，工作非常可靠，可稳定运行在400MHz。
K9F1G08U0B
K9XXG08UXBINFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE.NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDEDON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.1. For updates or additional information about Samsung products, contact your nearest Samsung office.2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply.* Samsung Electronics reserves the right to change products or specification without notice.Document Title128M x 8 Bit NAND Flash Memory Revision HistoryThe attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the rightto change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questions, please contact the SAMSUNG branch office near your office.Revision No0.01.0RemarkAdvance FinalHistory1. Initial issue1. 1.8V device is eliminatedDraft DateMay 26. 2006Sep. 27. 2006GENERAL DESCRIPTIONFEATURES• Voltage Supply- 3.3V Device(K9F1G08U0B) : 2.70V ~ 3.60V • Organization- Memory Cell Array : (128M + 4M) x 8bit - Data Register : (2K + 64) x 8bit • Automatic Program and Erase - Page Program : (2K + 64)Byte - Block Erase : (128K + 4K)Byte • Page Read Operation- Page Size : (2K + 64)Byte - Random Read : 25µs(Max.) - Serial Access : 25ns(Min.)128M x 8 Bit NAND Flash Memory• Fast Write Cycle Time- Page Program time : 200µs(Typ.) - Block Erase Time : 1.5ms(Typ.)• Command/Address/Data Multiplexed I/O Port • Hardware Data Protection- Program/Erase Lockout During Power Transitions • Reliable CMOS Floating-Gate Technology-Endurance : 100K Program/Erase Cycles with 1bit/512Byte ECC)- Data Retention : 10 Years • Command Driven Operation• Intelligent Copy-Back with internal 1bit/528Byte EDC • Unique ID for Copyright Protection • Package :- K9F1G08U0B-PCB0/PIB0 : Pb-FREE PACKAGE 48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)Offered in 128Mx8bit, the K9F1G08U0B is a 1G-bit NAND Flash Memory with spare 32M-bit. Its NAND cell provides the most cost-effective solution for the solid state application market. A program operation can be performed in typical 200µs on the (2K+64)Byte page and an erase operation can be performed in typical 1.5ms on a (128K+4K)Byte block. Data in the data register can be read out at 25ns cycle time per Byte. The I/O pins serve as the ports for address and data input/output as well as command input. The on-chip write controller automates all program and erase functions including pulse repetition, where required, and internal verification and margining of data. Even the write-intensive systems can take advantage of the K9F1G08U0B ′s extended reliability of 100K program/erase cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm. The K9F1G08U0B is an optimum solu-tion for large nonvolatile storage applications such as solid state file storage and other portable applications requiring non-volatility.PRODUCT LISTPart Number Vcc Range OrganizationPKG Type K9F1G08U0B-P2.70 ~3.60Vx8TSOP1PIN CONFIGURATION (TSOP1)K9F1G08U0B-PCB0/PIB0PACKAGE DIMENSIONS48-PIN LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I)48 - TSOP1 - 1220FUnit :mm/Inch0.787±0.00820.00±0.20#1#240.20+0.07-0.030.008+0.003-0.0010.500.0197#48#250.48812.40M A X12.000.4720.10 0.004M A X 0.250.010()0.039±0.0021.00±0.050.0020.05MIN0.0471.20MAX0.45~0.750.018~0.0300.724±0.00418.40±0.100~8°0.0100.25T Y P0.125+0.0750.0350.005+0.003-0.0010.500.020()48-pin TSOP1Standard Type 12mm x 20mm123456789101112131415161718192021222324484746454443424140393837363534333231302928272625N.C N.C N.C N.C N.C N.C R/B RE CE N.C N.C Vcc Vss N.C N.C CLE ALE WE WP N.C N.C N.C N.C N.CN.C N.C N.C N.C I/O7I/O6I/O5I/O4N.C N.C N.C Vcc Vss N.C N.C N.C I/O3I/O2I/O1I/O0N.C N.C N.C N.CPIN DESCRIPTIONNOTE : Connect all V CC and V SS pins of each device to common power supply outputs. Do not leave V CC or V SS disconnected.Pin Name Pin FunctionI/O 0 ~ I/O 7DATA INPUTS/OUTPUTSThe I/O pins are used to input command, address and data, and to output data during read operations. The I/O pins float to high-z when the chip is deselected or when the outputs are disabled.CLECOMMAND LATCH ENABLEThe CLE input controls the activating path for commands sent to the command register. When active high, commands are latched into the command register through the I/O ports on the rising edge of the WE signal.ALEADDRESS LATCH ENABLEThe ALE input controls the activating path for address to the internal address registers. Addresses are latched on the rising edge of WE with ALE high.CECHIP ENABLEThe CE input is the device selection control. When the device is in the Busy state, CE high is ignored, and the device does not return to standby mode in program or erase operation.REREAD ENABLEThe RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after the falling edge of RE which also increments the internal column address counter by one.WEWRITE ENABLEThe WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse.WPWRITE PROTECTThe WP pin provides inadvertent program/erase protection during power transitions. The internal high volt-age generator is reset when the WP pin is active low.R/BREADY/BUSY OUTPUTThe R/B output indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is in process and returns to high state upon completion. It is an open drain output and does not float to high-z condition when the chip is deselected or when outputs are disabled.Vcc POWERV CC is the power supply for device. Vss GROUNDN.CNO CONNECTIONLead is not internally connected.Product IntroductionThe K9F1G08U0B is a 1,056Mbit(1,107,296,256 bit) memory organized as 65,536 rows(pages) by 2,112x8 columns. Spare 64x8 col-umns are located from column address of 2,048~2,111. A 2,112-byte data register is connected to memory cell arrays accommodat-ing data transfer between the I/O buffers and memory during page read and page program operations. The memory array is made up of 32 cells that are serially connected to form a NAND structure. Each of the 32 cells resides in a different page. A block consists of two NAND structured strings. A NAND structure consists of 32 cells. Total 1,081,344 NAND cells reside in a block. The program and read operations are executed on a page basis, while the erase operation is executed on a block basis. The memory array consists of 1,024 separately erasable 128K-byte blocks. It indicates that the bit by bit erase operation is prohibited on the K9F1G08U0B.The K9F1G08U0B has addresses multiplexed into 8 I/Os. This scheme dramatically reduces pin counts and allows system upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through I/O's by bringing WE to low while CE is low. Those are latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. Some commands require one bus cycle. For example, Reset Command, Status Read Command, etc require just one cycle bus. Some other commands, like page read and block erase and page program, require two cycles: one cycle for setup and the other cycle for execution. The 132M byte physical space requires 28 addresses, thereby requiring four cycles for addressing : 2 cycles of column address, 2 cycles of row address, in that order. Page Read and Page Program need the same four address cycles following the required command input. In Block Erase oper-ation, however, only the two row address cycles are used. Device operations are selected by writing specific commands into the com-mand register. Table 1 defines the specific commands of the K9F1G08U0B.In addition to the enhanced architecture and interface, the device incorporates copy-back program feature from one page to another page without need for transporting the data to and from the external buffer memory. Since the time-consuming serial access and data-input cycles are removed, system performance for solid-state disk application is significantly increased.Table 1. Command SetsFunction1st Cycle2nd Cycle Acceptable Command during Busy Read 00h30hRead for Copy Back00h35hRead ID90h-Reset FFh-OPage Program80h10hCopy-Back Program85h10hBlock Erase60h D0hRandom Data Input(1)85h-Random Data Output(1)05h E0hRead Status70h ORead EDC Status(2)7Bh ONOTE : 1. Random Data Input/Output can be executed in a page.2. Read EDC Status is only available on Copy Back operation.Caution : Any undefined command inputs are prohibited except for above command set of Table 1.FLASH MEMORYK9F1G08U0BDC AND OPERATING CHARACTERISTICS (Recommended operating conditions otherwise noted.)NOTE : 1. V IL can undershoot to -0.4V and V IH can overshoot to V CC +0.4V for durations of 20 ns or less. 2. Typical value is measured at Vcc=3.3V, T A =25°C. Not 100% tested.ParameterSymbol Test ConditionsK9F1G08U0B(3.3V)UnitMinTypMaxOperating CurrentPage Read with Serial Access I CC 1tRC=25nsCE=V IL, I OUT =0mA-1530mAProgram I CC 2-EraseI CC 3-Stand-by Current(TTL)I SB 1CE=V IH , WP=0V/V CC --1Stand-by Current(CMOS)I SB 2CE=V CC -0.2, WP=0V/V CC -1050µAInput Leakage Current I LI V IN =0 to Vcc(max)--±10Output Leakage Current I LO V OUT =0 to Vcc(max)--±10Input High VoltageV IH (1)-0.8xVcc -V CC +0.3V Input Low Voltage, All inputs V IL (1)--0.3-0.2xVccOutput High Voltage Level V OH K9F1G08U0A :I OH =-400µA 2.4--Output Low Voltage Level V OLK9F1G08U0A :I OL =2.1mA--0.4Output Low Current(R/B)I OL (R/B)K9F1G08U0A :V OL =0.4V810-mA RECOMMENDED OPERATING CONDITIONS(Voltage reference to GND, K9F1G08U0B-XCB0 :T A =0 to 70°C, K9F1G0808B-XIB0:T A =-40 to 85°C)ParameterSymbol K9F1G08U0B(3.3V)UnitMin Typ.Max Supply Voltage V CC 2.7 3.3 3.6V Supply VoltageV SSV ABSOLUTE MAXIMUM RATINGSNOTE :1. Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns. Maximum DC voltage on input/output pins is V CC +0.3V which, during transitions, may overshoot to V CC +2.0V for periods <20ns.2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.ParameterSymbol Rating Unit3.3V Device Voltage on any pin relative to VSSV CC-0.6 to + 4.6VV IN -0.6 to + 4.6V I/O-0.6 to Vcc + 0.3 (< 4.6V)Temperature Under BiasK9XXG08XXB-XCB0T BIAS -10 to +125°C K9XXG08XXB-XIB0-40 to +125Storage Tempera-tureK9XXG08XXB-XCB0T STG-65 to +150°CK9XXG08XXB-XIB0Short Circuit CurrentI OS5mAw w w .DFLASH MEMORYK9F1G08U0BCAPACITANCE (T A =25°C, V CC =3.3V, f=1.0MHz)NOTE : Capacitance is periodically sampled and not 100% tested.ItemSymbol Test ConditionMin Max Unit Input/Output Capacitance C I/O V IL =0V -10pF Input CapacitanceC INV IN =0V-10pFVALID BLOCKNOTE : 1. The device may include initial invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase or pro-gram factory-marked bad blocks. Refer to the attached technical notes for appropriate management of invalid blocks.2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block up to 1K program/erase cycles with 1bit/512Byte ECC.ParameterSymbol Min Typ.Max Unit K9F1G08U0BN VB1,004-1,024BlocksMODE SELECTIONNOTE : 1. X can be V IL or V IH.2. WP should be biased to CMOS high or CMOS low for standby.CLE ALE CE WERE WP ModeH L L H X Read Mode Command Input L H L H X Address Input(4clock)H L L H H Write ModeCommand Input L H L H H Address Input(4clock)L L L HH Data Input L L L H X Data Output X X X X H X DuringRead(Busy)X X X X X H DuringProgram(Busy)X X X X X H DuringErase(Busy)X X (1)X X X L Write Protect XXHXX0V/V CC (2)Stand-by AC TEST CONDITION(K9F1G08U0B-XCB0 :TA=0 to 70°C, K9F1G08U0B-XIB0:TA=-40 to 85°C, K9F1G08U0B : Vcc=2.7V~3.6V unless otherwise noted)ParameterK9F1G08U0B Input Pulse Levels 0V to Vcc Input Rise and Fall Times 5ns Input and Output Timing Levels Vcc/2Output Load1 TTL GATE and CL=50pFFLASH MEMORYK9F1G08U0BAC Timing Characteristics for Command / Address / Data InputNOTES : 1. The transition of the corresponding control pins must occur only once while WE is held low 2. tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycleParameterSymbol Min Max Unit CLE Setup Time t CLS (1)12-ns CLE Hold Time t CLH 5-ns CE Setup Time t CS (1)20-ns CE Hold Time t CH 5-ns WE Pulse Width t WP 12-ns ALE Setup Time t ALS (1)12-ns ALE Hold Time t ALH 5-ns Data Setup Time t DS (1)12-ns Data Hold Time t DH 5-ns Write Cycle Time t WC 25-ns WE High Hold Timet WH 10-ns Address to Data Loading Timet ADL (2)100-nsProgram / Erase CharacteristicsNOTE : 1. Typical value is measured at Vcc=3.3V, T A =25°C. Not 100% tested.2. Typical program time is defined as the time within which more than 50% of the whole pages are programmed at3.3V Vcc and 25°C temperature .ParameterSymbol Min Typ Max Unit Program Time t PROG -200700µs Dummy Busy Time for Two-Plane Page Program t DBSY -0.51µs Number of Partial Program Cycles Nop --4cycles Block Erase Timet BERS- 1.52msw w w .D a t a S h eAC Characteristics for OperationParameter Symbol Min Max Unit Data Transfer from Cell to Register t R-25µs ALE to RE Delay t AR10-ns CLE to RE Delay t CLR10-ns Ready to RE Low t RR20-ns RE Pulse Width t RP12-ns WE High to Busy t WB-100ns Read Cycle Time t RC25-ns RE Access Time t REA-20ns CE Access Time t CEA-25ns RE High to Output Hi-Z t RHZ-100ns CE High to Output Hi-Z t CHZ-30ns CE High to ALE or CLE Don’t Care t CSD10-ns RE High to Output Hold t RHOH15-ns RE Low to Output Hold t RLOH5-ns CE High to Output Hold t COH15-ns RE High Hold Time t REH10-ns Output Hi-Z to RE Low t IR0-ns RE High to WE Low t RHW100-ns WE High to RE Low t WHR60-ns Device Resetting Time(Read/Program/Erase)t RST-5/10/500(1)µs NOTE: 1. If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5µs.NAND Flash Technical NotesIdentifying Initial Invalid Block(s)Initial Invalid Block(s)Initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is not guaranteed by Samsung.The information regarding the initial invalid block(s) is called the initial invalid block information. Devices with initial invalid block(s)have the same quality level as devices with all valid blocks and have the same AC and DC characteristics. An initial invalid block(s)does not affect the performance of valid block(s) because it is isolated from the bit line and the common source line by a select tran-sistor. The system design must be able to mask out the initial invalid block(s) via address mapping. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block up to 1K program/erase cycles with 1bit /512Byte ECC.All device locations are erased(FFh) except locations where the initial invalid block(s) information is written prior to shipping. The ini-tial invalid block(s) status is defined by the 1st byte in the spare area. Samsung makes sure that either the 1st or 2nd page of every initial invalid block has non-FFh data at the column address of 2048. Since the initial invalid block information is also erasable in most cases, it is impossible to recover the information once it has been erased. Therefore, the system must be able to recognize the initial invalid block(s) based on the original initial invalid block information and create the initial invalid block table via the following suggested flow chart(Figure 3). Any intentional erasure of the original initial invalid block information is prohibited.*Check "FFh" at the column address 2048 Figure 3. Flow chart to create initial invalid block tableStartSet Block Address = 0Check "FFh"Increment Block AddressLast Block ?EndNoYesYesCreate (or update)NoInitialof the 1st and 2nd page in the blockInvalid Block(s) TableNAND Flash Technical Notes (Continued)Program Flow ChartStartI/O 6 = 1 ?I/O 0 = 0 ?No*Write 80hWrite AddressWrite DataWrite 10hRead Status RegisterProgram Completedor R/B = 1 ?Program ErrorYesNoYes: If program operation results in an error, map out the block including the page in error and copy thetarget data to another block.*Error in write or read operationWithin its life time, additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual data.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read fail-ure after erase or program, block replacement should be done. Because program status fail during a page program does not affect the data of the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erased empty block and reprogramming the current target data and copying the rest of the replaced block. In case of Read, ECC must be employed. To improve the efficiency of memory space, it is recommended that the read or verification failure due to single bit error be reclaimed by ECC without any block replacement. The said additional block failure rate does not include those reclaimed blocks.Failure ModeDetection and Countermeasure sequenceWrite Erase Failure Status Read after Erase --> Block Replacement Program Failure Status Read after Program --> Block Replacement ReadSingle Bit FailureVerify ECC -> ECC CorrectionECC: Error Correcting Code --> Hamming Code etc. Example) 1bit correction & 2bit detectionNAND Flash Technical Notes (Continued)Copy-Back Operation with EDC & Sector Definition for EDCGenerally, copy-back program is very powerful to move data stored in a page without utilizing any external memory. But, if the source page has one bit error due to charge loss or charge gain, then without EDC, the copy-back program operation could also accumulate bit errors.K9F1G08U0B supports copy-back with EDC to prevent cumulative bit errors. To make EDC valid, the page program operation should be performed on either whole page(2112byte) or sector(528byte). Modifying the data of a sector by Random Data Input before Copy-Back Program must be performed for the whole sector and is allowed only once per each sector. Any partial modification smaller than a sector corrupts the on-chip EDC codes.A 2,112-byte page is composed of 4 sectors of 528-byte and each 528-byte sector is composed of 512-byte main area and 16-byte spare area."A" area 512 Byte(1’st sector)"H" area (4’th sector)Main Field (2,048 Byte)16 Byte"G" area (3’rd sector)16 Byte "F" area (2’nd sector)16 Byte "E" area (1’st sector)16 Byte "B" area 512 Byte(2’nd sector)"C" area 512 Byte(3’rd sector)"D" area 512 Byte(4’th sector)Spare Field (64 Byte)Table 2. Definition of the 528-Byte SectorSector Main Field (Column 0~2,047)Spare Field (Column 2,048~2,111)Area NameColumn AddressArea NameColumn Address 1’st 528-Byte Sector "A"0 ~ 511"E"2,048 ~ 2,0632’nd 528-Byte Sector "B"512 ~ 1,023"F"2,064 ~ 2,0793’rd 528-Byte Sector "C"1,024 ~ 1,535"G"2,080 ~ 2,0954’th 528-Byte Sector"D"1,536 ~ 2,047"H"2,096 ~ 2,111Within a block, the pages must be programmed consecutively from the LSB(least significant bit) page of the block to the MSB(most significant bit) pages of the block. Random page address programming is prohibited. In this case, the definition of LSB page is the LSB among the pages to be programmed. Therefore, LSB doesn't need to be page 0.From the LSB page to MSB page DATA IN: Data (1)Data (64)(1)(2)(3)(32)(64)Data register Page 0Page 1Page 2Page 31Page 63Ex.) Random page program (Prohibition)DATA IN: Data (1)Data (64)(2)(32)(3)(1)(64)Data registerPage 0Page 1Page 2Page 31Page 63Addressing for program operation::::Read ID OperationCECLEWEALERE90hRead ID CommandMaker Code Device Code00h ECht REAAddress 1cycleI/Oxt ARDevice Device Code (2nd Cycle)3rd Cycle 4th Cycle 5th Cycle K9F1G08U0BF1h00h95h40hDevice 4th cyc.Code3rd cyc.5th cyc.4th ID DataDescription I/O7 I/O6I/O5 I/O4 I/O3I/O2I/O1 I/O0Page Size(w/o redundant area ) 1KB2KB4KB8KB0 00 11 01 1Block Size(w/o redundant area ) 64KB128KB256KB512KB0 00 11 01 1Redundant Area Size ( byte/512byte) 8161Organization x8x161Serial Access Minimum 50ns/30ns25nsReservedReserved1111ID Definition Table90 ID : Access command = 90HDescription1st Byte 2nd Byte 3rd Byte 4th Byte 5th Byte Maker CodeDevice CodeInternal Chip Number, Cell Type, Number of Simultaneously Programmed Pages, Etc Page Size, Block Size,Redundant Area Size, Organization, Serial Access Minimum Plane Number, Plane Size3rd ID DataDescription I/O7 I/O6I/O5 I/O4I/O3 I/O2I/O1 I/O0Internal Chip Number 12480 00 11 01 1Cell Type 2 Level Cell4 Level Cell8 Level Cell16 Level Cell0 00 11 01 1Number ofSimultaneouslyProgrammed Pages 12480 00 11 01 1Interleave Program Between multiple chips Not SupportSupport1Cache Program Not SupportSupport15th ID DataDescription I/O7I/O6 I/O5 I/O4I/O3 I/O2 I/O1I/O0Plane Number 12480 00 11 01 1Plane Size(w/o redundant Area) 64Mb128Mb256Mb512Mb1Gb2Gb4Gb8Gb0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1Reserved 0 0 0Figure 7. Random Data Output In a PageAddress 00hData OutputR/B RE t R30hAddress 05hE0h4Cycles2Cycles Data OutputData Field Spare Field Data Field Spare FieldI/OxCol. Add.1,2 & Row Add.1,2PAGE PROGRAMThe device is programmed basically on a page basis, but it does allow multiple partial page programming of a word or consecutive bytes up to 2,112, in a single page program cycle. The number of consecutive partial page programming operation within the same page without an intervening erase operation must not exceed 4 times for a single page. The addressing should be done in sequential order in a block. A page program cycle consists of a serial data loading period in which up to 2,112bytes of data may be loaded into the data register, followed by a non-volatile programming period where the loaded data is programmed into the appropriate cell. The serial data loading period begins by inputting the Serial Data Input command(80h), followed by the four cycle address inputs and then serial data loading. The words other than those to be programmed do not need to be loaded. The device supports random data input in a page. The column address for the next data, which will be entered, may be changed to the address which follows random data input command(85h). Random data input may be operated multiple times regardless of how many times it is done in a page.Modifying the data of a sector by Random Data Input before Copy-Back Program must be performed for the whole sector and is allowed only once per each sector. Any partial modification smaller than a sector corrupts the on-chip EDC codes.The Page Program confirm command(10h) initiates the programming process. Writing 10h alone without previously entering the serial data will not initiate the programming process. The internal write state controller automatically executes the algorithms and tim-ings necessary for program and verify, thereby freeing the system controller for other tasks. Once the program process starts, the Read Status Register command may be entered to read the status register. The system controller can detect the completion of a pro-gram cycle by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. Only the Read Status command and Reset command are valid while programming is in progress. When the Page Program is complete, the Write Status Bit(I/O 0) may be checked(Figure 8). The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command register remains in Read Status command mode until another valid command is written to the command register.Figure 8. Program & Read Status Operation80hR/B Address & Data Input I/O0PassData10h70hFailt PROGI/OxCol. Add.1,2 & Row Add.1,2"0""1"Col. Add.1,2Figure 9. Random Data Input In a Page80hR/B Address & Data Input I/O0Pass10h70hFailt PROG85hAddress & Data InputI/OxCol. Add.1,2 & Row Add1,2Col. Add.1,2 DataData"0""1"Copy-Back ProgramThe Copy-Back program is configured to quickly and efficiently rewrite data stored in one page without utilizing an external memory.Since the time-consuming cycles of serial access and re-loading cycles are removed, the system performance is improved. The ben-efit is especially obvious when a portion of a block is updated and the rest of the block also need to be copied to the newly assigned free block. The operation for performing a copy-back program is a sequential execution of page-read without serial access and copy-ing-program with the address of destination page. A read operation with "35h" command and the address of the source page moves the whole 2,112-byte data into the internal data buffer. As soon as the device returns to Ready state, Page-Copy Data-input com-mand (85h) with the address cycles of destination page followed may be written. The Program Confirm command (10h) is required to actually begin the programming operation. During tPROG, the device executes EDC of itself. Once the program process starts, the Read Status Register command (70h) or Read EDC Status command (7Bh) may be entered to read the status register. The system controller can detect the completion of a program cycle by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register.When the Copy-Back Program is complete, the Write Status Bit(I/O 0) and EDC Status Bits (I/O 1 ~ I/O 2) may be checked(Figure 10& Figure 11& Figure 12). The internal write verification detects only errors for "1"s that are not successfully programmed to "0"s and the internal EDC checks whether there is only 1-bit error for each 528-byte sector of the source page. More than 2-bit error detection is not available for each 528-byte sector. The command register remains in Read Status command mode or Read EDC Status com-mand mode until another valid command is written to the command register.During copy-back program, data modification is possible using random data input command (85h) as shown in Figure11. But EDC status bits are not available during copy back for some bits or bytes modified by Random Data Input operation. However, in case of the 528 byte sector unit modification, EDC status bits are available.Figure 10. Page Copy-Back Program Operation00hR/B Add.(4Cycles)I/O0Pass85h 70h/7Bh Failt PROGAdd.(4Cycles) t R Source Address Destination Address35h10h I/OxCol. Add.1,2 & Row Add.1,2Col. Add.1,2 & Row Add.1,2Figure 11. Page Copy-Back Program Operation with Random Data Input00hR/B Add.(4Cycles)85h 70ht PROGAdd.(4Cycles) t RSource AddressDestination AddressData 35h10h 85hData Add.(2Cycles) There is no limitation for the number of repetition.I/OxCol. Add.1,2 & Row Add.1,2Col. Add.1,2 & Row Add.1,2Col. Add.1,2Note: 1. For EDC operation, only one time random data input is possible at the same address.Note : 1. Copy-Back Program operation is allowed only within the same memory plane.2. On the same plane, It’s prohibited to operate copy-back program from an odd address page(source page) to an even address page(target page) or from an even address page(source page) to an odd address page(target page). Therefore, the copy-back program is permitted just between odd address pages or even address pages."0""1"Note: 1. For EDC operation, only one time random data input is possible at the same address.。
20-STM32CubeMX系列教程20-Nand Flash
HAL_Delay(100); /* Read data from FMC NAND memory */ HAL_NAND_Read_Page(&hnand1, &WriteReadAddr, RxBuffer, 1); printf("\r\nRead receive: \r\n"); for(i = 0; i < 2048; i++)
从上图可知，K91FG080U0E 包含 1024 Blocks，每个 Block 包含 64 Pages，每个 Page 包 含 2K Bytes 数据空间 + 64 Bytes 冗余空间。故总大小=1024 Blocks x 64 Pages x (2K+ 64) B = (1024 + 32) MBits = 1G Bits。
• 将 AHB 数据通信事务转换为适当的外部器件协议 • 满足外部存储器器件的访问时间要求
说得复杂一点，FMC 个功能就是将读写 stm32 内部地址操作转换为输出满足外部存储 器的时序读写外部存储器。例如对 STM32 内部 Ox8000 0000 地址写入一个数据，FMC 控制 器会控制对应的管脚输出一个满足 Nand Flash 的时序，发送一个数据到 Nand Flash 设备。 同理读取读取内部的寄存器，也会生成一个时序从 Nand Flash 读取一个数据。因此通过 FMC 控制外设非常简单，只需读写 STM32 内部寄存器即可实现对外部存储器的读写操作。我们只 需配置好 FMC 时序寄存器,使产生的时序满足外部存储器的访问时间要求。
printf("Type = K9F1G08U0B\r\n"); } else if ((NAND_ID.Maker_Id == 0xAD) && (NAND_ID.Device_Id == 0xF1)
K9F5608X0D资料
Revision History
Revision No. History
0.0
Initial issue
0.1
1. Leaded package devices are eliminated
0.2
1.0
1.1
1. LOCKPRE pin mode is eliminated
• Fast Write Cycle Time - Program time : 200µs(Typ.) - Block Erase Time : 2ms(Typ.)
• Command/Address/Data Multiplexed I/O Port • Hardware Data Protection
* Samsung Electronics reserves the right to change products or specification without notice.
1
元器件交易网
K9F5608R0D K9F5608U0D K9F5608D0D
Document Title
FLASH MEMORY
Draft Date
May 16th. 2005
Remark
Advance
Aug. 11th. 2005 Advance
Oct. 17th. 2005 Preliminary
Oct. 30th. 2005 Final
Dec. 30th 2005
Note : For more detailed features and specifications including FAQ, please refer to Samsung’s Flash web site. /Products/Semiconductor/Flash/TechnicalInfo/datasheets.htm
K9F1G08U0A_flash芯片手册
38
N.C
37
Vcc
36
Vss
35
N.C
34
N.C
33
N.C
32
I/O3
31
I/O2
30
I/O1
29
I/O0
28
N.C
27
N.C
26
N.C
25
N.C
PACKAGE DIMENSIONS
48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I) 48 - TSOP1 - 1220AF
Apr. 23. 2004 Preliminary May. 19. 2004 Preliminary Jan. 21. 2005 Preliminary
Feb. 14. 2005 Preliminary May. 24. 2005 May 6. 2005
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questions, please contact the SAMSUNG branch office near your office.
0.1
1. The tADL(Address to Data Loading Time) is added.
K9F4008W0A资料
1
2
3
4
Frame Register 32 Bytes
I/O0 ~ I/O7
I/O0 1st Cycle 2nd Cycle 3rd Cycle A0 A8 A16
I/O1 A1 A9 A17
I/O2 A2 A10 A18
I/O3 A3 A11 X*
(1)
I/O4 A4 A12 X*
I/O5 A5 A13 X*
VCC CE RE R/B GND N.C N.C N.C N.C N.C
ALE CE RE WE WP GND
N.C N.C N.C N.C N.C I/O7 I/O6 I/O5 I/O4 VCC
R/B VCC VSS N.C
44(40) TSOP (II)
NOTE : Connect all VCC and VSS pins of each device to common power supply outputs. Do not leave VCC, VSS or GND inputs disconnected.
Control Logic & High Voltage Generator
I/O0 Global Buffers I/O7
CLE ALE WP
Figure 2. ARRAY ORGANIZATION
Good Block
1Block = 32 Rows = 4K Bytes The 1st Block (4KB) 4K Rows (=128 Blocks) 1 Frame = 32 Bytes 1 Row = 4 Frames = 128 Bytes 1 Block = 32 Rows = 4K Bytes 1 Device = 32Bytes x 4Frames x 32Rows x 128Blocks = 4Mbits 8 bit 128Bytes
K9D1G08V0A-SSB0资料
SmartMediaTM
GENERAL DESCRIPTION
Using Nand flash memory, SmartMedia provides the most costeffective solution for the solid state mass storage market. A program operation is implemented by the single page of 528 bytes in typical 200µs and an erase operation is done by the single block of 16K bytes in typical 2ms. Data in the page can be read out at 50ns cycle time per byte. The I/O pins serve as the ports for address and data input/output as well as command inputs. The on-chip write controller automates all program and erase functions including pulse repetition, where required, and internal verification and margining of data. Even the write-intensive systems can take advantage of the K9D1G08V0X, K9S1208V0X′s extended reliability of 100K program/erase cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm. SmartMedia is an optimum solution for large nonvolatile storage applications such as solid state file storage, digital voice recorder, digital still camera and other portable applications requiring non-volatility.
K9F2808U0资料
K9F2808U0A-YCB0, K9F2808U0A-YIB0
Document Title
16M x 8 Bit NAND Flash Memory
FLASH MEMORY
Revision History
Revision No. History
0.0 0.1 0.2 Initial issue. 1. Revised real-time map-out algorithm(refer to technical notes) 1. Changed device name - KM29U128AT -> K9F2808U0A-YCB0 - KM29U128AIT -> K9F2808U0A-YIB0 1. Changed sequential row read opera tion - The Sequential Read 1 and 2 operation is allowed only within a block 2. Changed invalid block(s) marking method prior to shipping - The invalid block(s) information is written the 1st or 2nd page of the invalid block(s) with 00h data --->The invalid block(s) status is defined by the 6th byte in the spare area. Samsung makes sure that either the 1st or 2nd page of every invalid block has 00h data at the column address of 517. 1. Changed endurance : 1million -> 100K program/erase cycles 2. Changed invalid block(s) marking method prior to shipping - The invalid block(s) status is defined by the 6th byte in the spare area. Samsung makes sure that either the 1st or 2nd page of every invalid block has 00h data at the column address of 517. --->The invalid block(s) status is defined by the 6th byte in the spare area. Samsung makes sure that either the 1st or 2nd page of every invalid block has non-FFh data at the column address of 517. 1. Changed SE pin description - SE is recommended to coupled to GND or Vcc and should not be toggled during reading or programming.
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K9F1G08X0A中文翻译文档本文主要是翻译给NAND flash初学者且看到电子方面英语就有点头痛的人们看的，其实内容并不复杂，如果有什么问题，可以邮件交流（就这篇文档内容），交流之后才能互相提高。
我是硬件工程师，交流的层面最好是在硬件方面，当然有软件方面的问题，我也非常乐意学习。
本来是希望翻译一篇MLC的NAND flash的文档，因为考虑到目前MLC才是NAND flash发展的重点，但是基于已经把这篇文档翻译了很多了，所以就不想再放弃它了。
再说MLC和SLC大部分操作什么的都类似，只是参数和校验等一些地方不同，因此也就作罢。
免骂（责）和其它声明：1、我尽可能的将英语按照意译的方式进行翻译，但是科技英语有的时候还真不是那么好意译，所以有的地方看起来就会像是在看英语一样，感觉有些拗口，希望看到这些地方的时候请您不要骂我，就算是在心里面的也不要。
2、还有，基于某些地方，我觉得外国人也写的很不畅，所以翻译过来也似乎感觉好像那里也会有问题，这种地方若被您发现，请您也不要骂我，同前面。
3、希望不会误人子弟。
4、版权所有，未经允许不得转载。
上海渐华科技发展有限公司李文荣2008-7-15liwr_mail@128M ×8Bit/256M ×8Bit NAND Flash Memory产品清单 Part Number Vcc Range OrganizationPKG Type K9F1G08R0A-J 1.65~1.95VFBGA K9F1G08U0A-P TSOP1 K9F1G08U0A-F WSOP1 K9F1G08U0A-J FBGA K9F2G08U1A-I2.7V ～3.6V×852-ULGA特征●供电电压：2.7V ～3.6V ●快速写周期时间 -1.8V 器件（K9F1G08R0A ）：1.65~1.95V -编程时间：200us （典型值） -3.3V 器件（K9F1G08U0A ）：2.7V ～3.6V -块插除时间：2ms （典型值）●架构 ●命令/地址/数据复用输入/输出端口 -存储器单元阵列：（128M ＋4,096K ）bit ×8bit ●数据硬件保护 -数据寄存器：（2K ＋64）bit ×8bit -电源变换期间切断编程/插除 -高速缓冲寄存器：（2K ＋64）bit ×8bit ●可靠地CMOS 浮置栅极技术 ●自动编程和插除 -持续：100K 编程/插除周期 -页编程：（2K ＋64）Byte -数据保持：10年 -块插除：（128K ＋4K ）Byte ●命令寄存器操作●页读操作 ●完美编程表现的高速缓冲编程操作 -页大小：2K-Byte ●智能Copy-Back 操作 -随机读：25us （Max ） ●惟一的ID 版权保护 -顺序访问：35ns （Min ）-3.3V 器件50ns （Min ）-1.8V 器件 ●封装：- K9F1G08X0A-JCB0/JIB063-Ball FBGA(9.5×12)-Pb-free 封装- K9F1G08U0A-PCB0/PIB048-pin TSOP 1(12×20/0.5mm 间距) Pb-free 封装 - K9F1G08U0A-FIB048-pin WSOP 1(12×17×0.7mm) Pb-free 封装 *K9F1G08U0A-F(WSOPI)和K9F1G08U0A-F(TSOPI)是相同器件，只是封装不同- K9K2G08U1A-ICB0/IIB052- ULGA （12×17×0.65mm ） 综述128M ×8bit 的K9F1G08X0A 是一个1Gbit 并带备用的32Mbit 容量的存储器。
它的NAND 单元为固态大容量市场提供最节省-高效解决方案。
一个编程操作可在200us 内在2112字节的页上执行，而擦除操作可在2ms 内在128K 字节的块内执行。
在数据页上的数据可在30ns （1.8V 器件50ns ）内读出一个字节。
I/O 引脚可作为地址和数据输入输出以及命令输入。
在线写控制器自动操作所有编程和擦除功能，包括脉冲重复，和内部校验及数据余量。
写密集型系统通过提供带实时映射算法的ECC ，可利用K9F1G08X0A 的扩展的可靠性的100k 编程/擦除周期。
K9F1G08X0A 是大容量非易失性存储应用如固态文件存储和其它要求非易失性的便携应用的最佳解决方案。
引脚描述引脚名称引脚功能I/O0~I/O7 数据输入/输出这些I/O引脚用来输入命令，地址和数据，以及通过读操作输出数据。
当芯片未被选择时，这些I/O引脚浮置成高阻态，输出无效CLE 命令锁存使能CLE控制命令输入到命令寄存器中。
当CLE为高时，在/WE信号的上升沿，命令通过I/O口锁存到命令寄存器中。
ALE 地址锁存使能ALE控制地址输入到内部地址寄存器中。
当ALE为高时，在/WE信号的上升沿，命令通过I/O口锁存到命令寄存器中。
/CE 芯片使能信号片选信号控制芯片是否被选中。
当芯片处于忙状态，/CE为高被忽略，并且芯片不会回到standby状态。
/RE 读使能/RE为串行数据输出控制，当它处在活动状态时，则数据驱动至I/O总线上。
数据在/RE的下降沿过后tREA时间后有效，并且内部列地址计数器自动加1。
/WE 写使能/WE控制向I/O口写入。
命令，地址和数据在/WE的上升沿锁存。
/WP 写保护/WP引脚在电源切换期间提供无意的写/擦除保护。
当/WP为低时，内置高电压发生器复位。
R/B 准备/忙输出R/B输出指示器件操作的状态。
当为低时，它指示一个编程，擦除会随机读操作正在进行，并在完成后返回一个高状态。
它是一个开路集电极输出，当器件未被选择或输出无效时，它并不会浮置成高阻态。
Vcc 电源VCC是器件的电源供应。
Vss 地N.C 未连接引线内部未连接备注：连接每个器件的Vcc和Vss到公共电源输出。
不要让Vcc和Vss悬空。
备注：列地址：寄存器的开始地址 *L 必须设置为“低”。
*器件会忽略任何多于其要求的输入地址。
产品介绍K9F1G08X0A是一个1056Mbit（1,107,296,256 bit）存储器，由65,536行（页）乘2112×8列组成。
多于的64列地址为2048到2111。
一个2112字节数据寄存器和一个2112字节高速缓冲寄存器各自串接在一起。
这些串接的寄存器连接到存储器单元，方便在I/O缓冲器和存储器单元之间在页读操作和页编程操作时交换数据。
该存储器阵列是由32个串连的单元组成的一个NAND结构。
每32个单元存在不同的页里。
一个块存储区由两个NAND结构串组成。
一个NAND结构包含32个单元。
总共1081344个NAND单元存在一个块内。
编程和读操作都是基于页执行的，擦除操作则是基于块执行的。
该存储器由1024个分离的可擦除的128K字节的块组成。
它表示位擦除操作在K9F1G08XOA是不允许的。
K9F1G08X0A地址复用到8个I/O口。
这个方案引人注目的减少了引脚数目，以及允许系统在线升级更大容量密度时保持连贯性。
命令，地址和数据在/CE为低时，拉低/WE，通过I/O端口写入，它们在/WE的上升沿时被锁存住。
命令锁存使能（CLE）和地址锁存使能（ALE）是命令和地址，通过I/O口用来作各自的复用。
有些命令要求一个总线周期。
例如，复位命令，状态读命令等等，仅要求一个周期总线。
一些其它的命令，如页读、块擦除和页编程，要求两个周期：一个周期用来建立，另一个用来执行。
这132M物理空间需要28个地址，因此需要4个周期用来寻址：2个周期用来作列地址，2个周期作行地址。
页读和页编程需要相同的4个地址周期，在要求的命令输入之后。
然而，在块擦除操作中，仅2个行地址需要用到。
器件的操作是通过进入到命令寄存器中的规定的指令选择的。
表1定义了K9F1G08X0A的规定的指令。
器件在每个块存储区中提供高速缓冲编程。
在高速缓冲编程模式下，当数据存储在数据寄存器准备被编程时，可将数据写入到高速缓冲寄存器。
当有很多页数据准备编程时，通过高速缓冲编程模式，编程性能也许会得到引人注目的提高。
除增强型的体系结构和接口外，器件具有copy-back编程特征，能将一页数据拷到另一页上，而无需和外部缓冲存储器之间传输数据。
自从这个耗费时间的连续访问和数据输入周期不再需要了，作为固态磁盘应用的系统表现明显增强了。
表1. 命令设置功能第一个周期第二个周期忙期间可得的命令读00h 30h读用作copy-back 00h 35h读ID 90h －复位FFh －O页编程80h 10h高速缓冲编程*280h 15hcopy-back编程85h 10h块擦除60h D0h随机输入数据*185h －随机输出数据*105h E0h读状态70h O备注：1.随机输入/输出数据可在页里面执行。
2.高速缓冲编程和copy-back编程仅支持3.3V期间。
注意：除表1之外的任何未定义的命令输入都被禁止。
绝对最大标称值标称值参数符号 1.8V 器件 3.3V 器件 单位 V IN/OUT -0.6到+2.45 -0.6到+4.6 参考于V SS 的任何引脚的电压 V CC -0.2到+2.45-0.6到+4.6V K9F1G08X0A-XCB0 -10 to +125 偏置上的温度 K9F1G08X0A-XIB0 T BIAS -40 to +125 ℃ K9F1G08X0A-XCB0 储存温度K9F1G08X0A-XIB0 T STG -65 to +125℃ 短路电流I OS5mA备注：1. I/O 口上的最低DC 电压为-0.6V 。
在跳变时，该电平可能会有一个持续不过30ns 的最大-2.0V 的过冲。
I/O 口上的最大DC 电压为V CC ＋0.3V 。
在跳变时，该电平可能会有一个持续不过20ns的最大为V CC ＋2.0V 的过冲。
2. 假如参数超过上述绝对最大标称值，器件可能会产生永久性的损坏。
功能操作必须限制在这篇规格书内的操作部分所阐述的条件之内。
长期地在绝对最大标称值条件下工作也可能会影响器件的可靠性。
推荐工作条件（电压参考于地，K9F1G08X0A-XCB0：T A =0 to 70℃, K9F1G08X0A-XIB0：T A =-40 to 85℃） K9F1G08R0A （1.8V ） K9F1G08U0A （3.3V ） 参数 符号 Min Typ. Max Min Typ. Max 单位 V CC 1.65 1.8 1.95 2.7 3.3 3.6 V 供电电压 供电电压V SS00VDC 和工作特性（推荐工作条件，除非另有提出）备注：V IL 在跳变过程中可能会有20ns 内的-0.4V 的下冲和V CC +0.4V 的上冲。